include/video/stf-vin.h

   1 /* include/video/stf-vin.h
   2  *
   3  * Copyright 2020 starfive tech.
   4  *      Eric Tang <eric.tang@starfivetech.com>
   5  *
   6  * Generic vin notifier interface
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12 */
  13 #ifndef _VIDEO_VIN_H
  14 #define _VIDEO_VIN_H
  15
  16 #include <linux/cdev.h>
  17
  18 #define DRV_NAME "jh7110-vin"
  19 #define FB_FIRST_ADDR      0xf9000000
  20 #define FB_SECOND_ADDR     0xf97e9000
  21
  22 #define RESERVED_MEM_SIZE  0x1000000
  23
  24 #define VIN_MIPI_CONTROLLER0_OFFSET 0x00000
  25 #define VIN_CLKGEN_OFFSET           0x10000
  26 #define VIN_RSTGEN_OFFSET           0x20000
  27 #define VIN_MIPI_CONTROLLER1_OFFSET 0x30000
  28 #define VIN_SYSCONTROLLER_OFFSET    0x40000
  29
  30 #define VD_1080P    1080
  31 #define VD_720P     720
  32 #define VD_PAL      480
  33
  34 #define VD_HEIGHT_1080P     VD_1080P
  35 #define VD_WIDTH_1080P      1920
  36
  37 #define VD_HEIGHT_720P      VD_720P
  38 #define VD_WIDTH_720P       1080
  39
  40 #define VD_HEIGHT_480       480
  41 #define VD_WIDTH_640        640
  42
  43 #define SEEED_WIDTH_800       800
  44 #define SEEED_HIGH_480        480
  45
  46 #define VIN_TOP_CLKGEN_BASE_ADDR            0x11800000
  47 #define VIN_TOP_RSTGEN_BASE_ADDR            0x11840000
  48 #define VIN_TOP_IOPAD_BASE_ADDR         0x11858000
  49
  50 #define ISP_BASE_MIPI0_ADDR             0x19800000
  51 #define ISP_BASE_CLKGEN_ADDR            0x19810000
  52 #define ISP_BASE_RSTGEN_ADDR            0x19820000
  53 #define ISP_BASE_MIPI1_ADDR             0x19830000
  54 #define ISP_BASE_SYSCTRL_ADDR           0x19840000
  55 #define ISP_BASE_ISP0_ADDR                  0x19870000
  56 #define ISP_BASE_ISP1_ADDR                  0x198a0000
  57
  58
  59 //vin clk registers
  60 #define CLK_VIN_SRC_CTRL                    0x188
  61 #define CLK_ISP0_AXI_CTRL                   0x190
  62 #define CLK_ISP0NOC_AXI_CTRL        0x194
  63 #define CLK_ISPSLV_AXI_CTRL                 0x198
  64 #define CLK_ISP1_AXI_CTRL                   0x1A0
  65 #define CLK_ISP1NOC_AXI_CTRL        0x1A4
  66 #define CLK_VIN_AXI                         0x1AC
  67 #define CLK_VINNOC_AXI                  0x1B0
  68
  69
  70 #define CLK_DOM4_APB_FUNC                       0x0
  71 #define CLK_MUX_SEL                                     0xffffff
  72
  73 #define CLK_MIPI_RX0_PXL            0x4
  74
  75 #define CLK_DVP_INV                                     0x8
  76 #define CLK_U0_VIN_PCLK                         0x18
  77 #define CLK_U0_VIN_PCLK_ICG                                             (0x1<<31)
  78
  79 #define CLK_U0_VIN_SYS_CLK                      0x1c
  80 #define CLK_U0_VIN_CLK_P_AXIWR          0x30
  81 #define CLK_U0_VIN_MUX_SEL                      (BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28) | BIT(29))
  82
  83 #define CLK_U0_VIN_PIXEL_CLK_IF0    0x20
  84 #define CLK_U0_VIN_PIXEL_CLK_IF1    0x24
  85 #define CLK_U0_VIN_PIXEL_CLK_IF2    0x28
  86 #define CLK_U0_VIN_PIXEL_CLK_IF3    0x2c
  87
  88 #define CLK_U0_VIN_CLK_P_AXIWR      0x30
  89
  90 #define CLK_U0_ISPV2_TOP_WRAPPER_CLK_C  0x34u
  91 #define CLK_U0_ISPV2_MUX_SEL            (0x1<<24 | 0x1<<25 | 0x1<<26 | 0x1<<27 | 0x1<<28 | 0x1<< 29)
  92
  93 #define CLK_U0_ISPV2_CLK_ICG                                            (0x1<<31)
  94
  95 #define SOFTWARE_RESET_ASSERT0_ASSERT_SET 0x38U
  96 #define SOFTWARE_RESET_ASSERT0_ASSERT_SET_STATE 0x3CU
  97 #define RST_U0_ISPV2_TOP_WRAPPER_RST_P  BIT(0)
  98 #define RST_U0_ISPV2_TOP_WRAPPER_RST_C  BIT(1)
  99 #define RSTN_U0_VIN_RST_N_PCLK  BIT(4)
 100 #define RSTN_U0_VIN_RST_N_SYS_CLK       BIT(9)
 101 #define RSTN_U0_VIN_RST_P_AXIRD BIT(10)
 102 #define RSTN_U0_VIN_RST_P_AXIWR BIT(11)
 103
 104
 105 #define CLK_POLARITY                            (0x1<<30)
 106
 107 #define M31DPHY_APBCFGSAIF__SYSCFG_0    0x0
 108 #define M31DPHY_APBCFGSAIF__SYSCFG_4    0x4
 109 #define M31DPHY_APBCFGSAIF__SYSCFG_8    0x8
 110 #define M31DPHY_APBCFGSAIF__SYSCFG_12   0xc
 111 #define M31DPHY_APBCFGSAIF__SYSCFG_16   0x10
 112 #define M31DPHY_APBCFGSAIF__SYSCFG_20   0x14
 113 #define M31DPHY_APBCFGSAIF__SYSCFG_24   0x18
 114 #define M31DPHY_APBCFGSAIF__SYSCFG_28   0x1c
 115 #define M31DPHY_APBCFGSAIF__SYSCFG_32   0x20
 116 #define M31DPHY_APBCFGSAIF__SYSCFG_36   0x24
 117 #define M31DPHY_APBCFGSAIF__SYSCFG_40   0x28
 118 #define M31DPHY_APBCFGSAIF__SYSCFG_44   0x2c
 119 #define M31DPHY_APBCFGSAIF__SYSCFG_48   0x30
 120 #define M31DPHY_APBCFGSAIF__SYSCFG_52   0x34
 121 #define M31DPHY_APBCFGSAIF__SYSCFG_56   0x38
 122 #define M31DPHY_APBCFGSAIF__SYSCFG_60   0x3c
 123 #define M31DPHY_APBCFGSAIF__SYSCFG_64   0x40
 124 #define M31DPHY_APBCFGSAIF__SYSCFG_68   0x44
 125 #define M31DPHY_APBCFGSAIF__SYSCFG_72   0x48
 126 #define M31DPHY_APBCFGSAIF__SYSCFG_76   0x4c
 127 #define M31DPHY_APBCFGSAIF__SYSCFG_80   0x50
 128 #define M31DPHY_APBCFGSAIF__SYSCFG_84   0x54
 129 #define M31DPHY_APBCFGSAIF__SYSCFG_88   0x58
 130 #define M31DPHY_APBCFGSAIF__SYSCFG_92   0x5c
 131 #define M31DPHY_APBCFGSAIF__SYSCFG_96   0x60
 132 #define M31DPHY_APBCFGSAIF__SYSCFG_100  0x64
 133 #define M31DPHY_APBCFGSAIF__SYSCFG_104  0x68
 134 #define M31DPHY_APBCFGSAIF__SYSCFG_108  0x6c
 135 #define M31DPHY_APBCFGSAIF__SYSCFG_112  0x70
 136 #define M31DPHY_APBCFGSAIF__SYSCFG_116  0x74
 137 #define M31DPHY_APBCFGSAIF__SYSCFG_120  0x78
 138 #define M31DPHY_APBCFGSAIF__SYSCFG_124  0x7c
 139 #define M31DPHY_APBCFGSAIF__SYSCFG_128  0x80
 140 #define M31DPHY_APBCFGSAIF__SYSCFG_132  0x84
 141 #define M31DPHY_APBCFGSAIF__SYSCFG_136  0x88
 142 #define M31DPHY_APBCFGSAIF__SYSCFG_140  0x8c
 143 #define M31DPHY_APBCFGSAIF__SYSCFG_144  0x90
 144 #define M31DPHY_APBCFGSAIF__SYSCFG_184  0xb8
 145
 146 //pmu registers
 147 #define SW_DEST_POWER_ON                        0x0C
 148 #define SW_DEST_POWER_OFF                       0x10
 149 #define SW_ENCOURAGE                            0x44
 150
 151
 152 //isp clk registers
 153 #define CLK_DPHY_CFGCLK_ISPCORE_2X_CTRL    0x00
 154 #define CLK_DPHY_REFCLK_ISPCORE_2X_CTRL    0x04
 155 #define CLK_DPHY_TXCLKESC_IN_CTRL          0x08
 156 #define CLK_MIPI_RX0_PXL_CTRL       0x0c
 157 #define CLK_MIPI_RX1_PXL_CTRL       0x10
 158 #define CLK_MIPI_RX0_PXL_0_CTRL     0X14
 159 #define CLK_MIPI_RX0_PXL_1_CTRL     0X18
 160 #define CLK_MIPI_RX0_PXL_2_CTRL     0X1C
 161 #define CLK_MIPI_RX0_PXL_3_CTRL     0X20
 162 #define CLK_MIPI_RX0_SYS0_CTRL      0x24
 163 #define CLK_MIPI_RX1_PXL_0_CTRL     0X28
 164 #define CLK_MIPI_RX1_PXL_1_CTRL     0X2C
 165 #define CLK_MIPI_RX1_PXL_2_CTRL     0X30
 166 #define CLK_MIPI_RX1_PXL_3_CTRL     0X34
 167 #define CLK_MIPI_RX1_SYS1_CTRL      0x38
 168 #define CLK_ISP_CTRL               0x3c
 169 #define CLK_ISP_2X_CTRL            0x40
 170 #define CLK_ISP_MIPI_CTRL          0x44
 171 #define CLK_C_ISP_CTRL             0x64
 172 #define CLK_CSI2RX0_APB_CTRL        0x58
 173
 174
 175 #define CLK_VIN_AXI_WR_CTRL         0x5C
 176
 177 #define SOFTWARE_RESET_ASSERT0          0x0
 178 #define SOFTWARE_RESET_ASSERT1          0x4
 179 #define SOFTWARE_RESET_STATUS           0x4
 180
 181 #define IOPAD_REG81                     0x144
 182 #define IOPAD_REG82                     0x148
 183 #define IOPAD_REG83                     0x14C
 184 #define IOPAD_REG84                     0x150
 185 #define IOPAD_REG85                     0x154
 186 #define IOPAD_REG86                     0x158
 187 #define IOPAD_REG87                 0x15C
 188 #define IOPAD_REG88                 0x160
 189 #define IOPAD_REG89                 0x164
 190
 191 //sys control REG DEFINE
 192 #define SYSCONSAIF_SYSCFG_0                                             0X0
 193 #define U0_VIN_SCFG_SRAM_CONFIG     (BIT(0) | BIT(1))
 194
 195 #define SYSCONSAIF_SYSCFG_4                     0x4
 196 #define U0_VIN_CNFG_AXIRD_END_ADDR 0xffffffff
 197 #define SYSCONSAIF_SYSCFG_8                     0x8
 198 #define U0_VIN_CNFG_AXIRD_LINE_CNT_END (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13))
 199 #define U0_VIN_CNFG_AXIRD_LINE_CNT_START (BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25))
 200 #define SYSCONSAIF_SYSCFG_12            0xc
 201 #define U0_VIN_CNFG_AXIRD_PIX_CNT_END  (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12))
 202 #define U0_VIN_CNFG_AXIRD_PIX_CNT_START (BIT(13) | BIT(14) | BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) | BIT(25))
 203 #define U0_VIN_CNFG_AXIRD_PIX_CT        (BIT(26) | BIT(27))
 204 #define SYSCONSAIF_SYSCFG_16            0x10
 205 #define U0_VIN_CNFG_AXIRD_START_ADDR 0xFFFFFFFF
 206 #define SYSCONSAIF_SYSCFG_20            0x14
 207 #define U0_VIN_CNFG_AXIWR0_EN           BIT(4)
 208 #define U0_VIN_CNFG_AXIWR0_CHANNEL_SEL (BIT(0) | BIT(1) | BIT(2) | BIT(3))
 209 #define SYSCONSAIF_SYSCFG_24            0x18
 210 #define U0_VIN_CNFG_AXIWR0_END_ADDR 0xFFFFFFFF
 211
 212 #define SYSCONSAIF_SYSCFG_28            0x1c
 213 #define U0_VIN_CNFG_AXIWR0_INTR_CLEAN BIT(0)
 214 #define U0_VIN_CNFG_AXIWR0_MASK         BIT(1)
 215 #define U0_VIN_CNFG_AXIWR0_PIX_CNT_END (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12))
 216 #define U0_VIN_CNFG_AXIWR0_PIX_CT (BIT(13) | BIT(14))
 217 #define UO_VIN_CNFG_AXIWR0_PIXEL_HEIGH_BIT_SEL (BIT(15) | BIT(16))
 218 #define SYSCONSAIF_SYSCFG_32            0x20
 219
 220 #define SYSCONSAIF_SYSCFG_36                    0x24
 221 #define UO_VIN_CNFG_COLOR_BAR_EN        BIT(0)
 222 #define U0_VIN_CNFG_DVP_HS_POS          (0x1<<1)
 223 #define U0_VIN_CNFG_DVP_SWAP_EN         BIT(2)
 224 #define U0_VIN_CNFG_DVP_VS_POS          (0x1<<3)
 225 #define U0_VIN_CNFG_GEN_EN_AXIRD        BIT(4)
 226 #define U0_VIN_CNFG_ISP_DVP_EN0         BIT(5)
 227 #define U0_VIN_CNFG_MIPI_BYTE_EN_ISP0   (BIT(6) |BIT(7))
 228 #define U0_VIN_CNFG_P_I_MIPI_CHANNEL_SEL0       (BIT(8) |BIT(9) | BIT(10) | BIT(11))
 229 #define U0_VIN_CNFG_P_I_MIPI_HEADER_EN0 BIT(12)
 230
 231 #define U0_VIN_CNFG_PIX_NUM                     (0x1<<13 | 0x1<<14 | 0x1<<15 | 0x1<<16)
 232 #define U0_VIN_CNFG_AXIRD_AXI_CNT_END   (BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13))
 233
 234 #define U0_VIN_CNFG_AXI_DVP_EN          BIT(2)
 235 #define U0_VIN_CNFG_AXIRD_INTR_MASK     BIT(1)
 236 #define U0_VIN_CNFG_AXIWRD_INTR_MASK    BIT(1)
 237 #define U0_VIN_CNFG_AXIWR0_START_ADDR   0xffffffff
 238 #define U0_VIN_CNFG_COLOR_BAR_EN        0X0
 239 #define U0_VIN_CNFG_AXIWR0_PIX_CNT_CT (BIT(13) | BIT(14))
 240 #define U0_VIN_CNFG_AXIWR0_PIX_CNT_CNT_END (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) | BIT(12))
 241 #define U0_VIN_CNFG_AXIWR0_PIXEL_HITH_BIT_SEL (BIT(15) | BIT(16))
 242
 243 #define SYSCTRL_REG4                0x10
 244 #define SYSCTRL_DPHY_CTRL               0x14
 245 #define SYSCTRL_VIN_AXI_CTRL        0x18
 246 #define SYSCTRL_VIN_WR_START_ADDR       0x28
 247 #define SYSCTRL_VIN_RD_END_ADDR     0x2C
 248 #define SYSCTRL_VIN_WR_PIX_TOTAL        0x30
 249 #define SYSCTRL_VIN_RD_PIX_TOTAL        0x34
 250 #define SYSCTRL_VIN_RW_CTRL             0x38
 251 #define SYSCTRL_VIN_SRC_CHAN_SEL        0x24
 252 #define SYSCTRL_VIN_SRC_DW_SEL      0x40
 253 #define SYSCTRL_VIN_RD_VBLANK       0x44
 254 #define SYSCTRL_VIN_RD_VEND             0x48
 255 #define SYSCTRL_VIN_RD_HBLANK       0x4C
 256 #define SYSCTRL_VIN_RD_HEND             0x50
 257 #define SYSCTRL_VIN_INTP_CTRL       0x54
 258
 259 #define ISP_NO_SCALE_ENABLE     (0x1<<20)
 260 #define ISP_MULTI_FRAME_ENABLE  (0x1<<17)
 261 #define ISP_SS0_ENABLE          (0x1<<11)
 262 #define ISP_SS1_ENABLE          (0x1<<12)
 263 #define ISP_RESET               (0x1<<1)
 264 #define ISP_ENBALE              (0x1)
 265
 266
 267
 268  //ISP REG DEFINE
 269 #define ISP_REG_DVP_POLARITY_CFG            0x00000014
 270 #define ISP_REG_RAW_FORMAT_CFG              0x00000018
 271 #define ISP_REG_CFA_MODE                    0x00000A1C
 272 #define ISP_REG_PIC_CAPTURE_START_CFG       0x0000001C
 273 #define ISP_REG_PIC_CAPTURE_END_CFG         0x00000020
 274 #define ISP_REG_PIPELINE_XY_SIZE            0x00000A0C
 275 #define ISP_REG_Y_PLANE_START_ADDR          0x00000A80
 276 #define ISP_REG_UV_PLANE_START_ADDR         0x00000A84
 277 #define ISP_REG_STRIDE                      0x00000A88
 278 #define ISP_REG_PIXEL_COORDINATE_GEN        0x00000A8C
 279 #define ISP_REG_PIXEL_AXI_CONTROL           0x00000A90
 280 #define ISP_REG_SS_AXI_CONTROL              0x00000AC4
 281 #define ISP_REG_RGB_TO_YUV_COVERSION0       0x00000E40
 282 #define ISP_REG_RGB_TO_YUV_COVERSION1       0x00000E44
 283 #define ISP_REG_RGB_TO_YUV_COVERSION2       0x00000E48
 284 #define ISP_REG_RGB_TO_YUV_COVERSION3       0x00000E4C
 285 #define ISP_REG_RGB_TO_YUV_COVERSION4       0x00000E50
 286 #define ISP_REG_RGB_TO_YUV_COVERSION5       0x00000E54
 287 #define ISP_REG_RGB_TO_YUV_COVERSION6       0x00000E58
 288 #define ISP_REG_RGB_TO_YUV_COVERSION7       0x00000E5C
 289 #define ISP_REG_RGB_TO_YUV_COVERSION8       0x00000E60
 290 #define ISP_REG_CSI_MODULE_CFG              0x00000010
 291 #define ISP_REG_ISP_CTRL_1                  0x00000A08
 292 #define ISP_REG_ISP_CTRL_0                  0x00000A00
 293 #define ISP_REG_DC_AXI_ID                   0x00000044
 294 #define ISP_REG_CSI_INPUT_EN_AND_STATUS     0x00000000
 295
 296 //CSI registers
 297 #define DEVICE_CONFIG           0x00
 298 #define SOFT_RESET              0x04
 299 #define STATIC_CFG              0x08
 300 #define ERROR_BYPASS_CFG        0x10
 301 #define MONITOR_IRQS            0x18
 302 #define MONITOR_IRQS_MASK_CFG   0x1c
 303 #define INFO_IRQS               0x20
 304 #define INFO_IRQS_MASK_CFG      0x24
 305 #define ERROR_IRQS              0x28
 306 #define ERROR_IRQS_MASK_CFG     0x2c
 307 #define DPHY_LANE_CONTROL       0x40
 308 #define DPHY_STATUS             0x48
 309 #define DPHY_ERR_STATUS_IRQ     0x4C
 310 #define DPHY_ERR_IRQ_MASK_CFG   0x50
 311 #define INTEGRATION_DEBUG       0x60
 312 #define ERROR_DEBUG             0x74
 313
 314 #define STREAM0_CTRL            0x100
 315 #define STREAM0_STATUS          0x104
 316 #define STREAM0_DATA_CFG        0x108
 317 #define STREAM0_CFG             0x10c
 318 #define STREAM0_MONITOR_CTRL    0x110
 319 #define STREAM0_MONITOR_FRAME   0x114
 320 #define STREAM0_MONITOR_LB      0x118
 321 #define STREAM0_TIMER           0x11c
 322 #define STREAM0_FCC_CFG         0x120
 323 #define STREAM0_FCC_CTRL        0x124
 324 #define STREAM0_FIFO_FILL_LVL   0x128
 325
 326 //m31_dphy registers
 327 #define M31DPHY_APBCFGSAIF__SYSCFG_188      0xbc
 328 #define M31DPHY_APBCFGSAIF__SYSCFG_192      0xc0
 329 #define M31DPHY_APBCFGSAIF__SYSCFG_196      0xc4
 330 #define M31DPHY_APBCFGSAIF__SYSCFG_200      0xc8
 331
 332 typedef enum
 333 {
 334     DT_RAW6  = 0x28,
 335     DT_RAW7  = 0x29,
 336     DT_RAW8  = 0x2a,
 337     DT_RAW10 = 0x2b,
 338     DT_RAW12 = 0x2c,
 339     DT_RAW14 = 0x2d,
 340 } mipicam_data_type_t;
 341
 342
 343 enum VIN_SOURCE_FORMAT {
 344         SRC_COLORBAR_VIN_ISP = 0,
 345         SRC_DVP_SENSOR_VIN,
 346         SRC_DVP_SENSOR_VIN_ISP,//need replace sensor
 347         SRC_CSI2RX_VIN_ISP,
 348         SRC_DVP_SENSOR_VIN_OV5640,
 349 };
 350
 351 struct reg_name {
 352         char name[10];
 353 };
 354
 355 typedef struct
 356 {
 357     int dlane_nb;
 358     int dlane_map[4];
 359     int dlane_en[4];
 360     int dlane_pn_swap[4];
 361     int clane_nb;
 362     int clane_map[2];
 363     int clane_pn_swap[2];
 364 } csi2rx_dphy_cfg_t;
 365
 366 typedef struct
 367 {
 368     int lane_nb;
 369     int dlane_map[4];
 370     int dt;
 371     int hsize;
 372     int vsize;
 373 } csi2rx_cfg_t;
 374
 375
 376 typedef struct
 377 {
 378     int mipi_id, w, h, dt, bpp, fps,lane;
 379         u8  clane_swap;
 380     u8  clane_pn_swap;
 381     u8  dlane_swap[4];
 382     u8  dlane_pn_swap[4];
 383 } csi_format;
 384
 385 struct vin_params {
 386         void *paddr;
 387         unsigned long size;
 388 };
 389
 390 struct vin_buf {
 391         void *vaddr;
 392         dma_addr_t paddr;
 393         u32 size;
 394 };
 395
 396 struct vin_framesize {
 397         u32 width;
 398         u32 height;
 399 };
 400
 401 struct vin_format {
 402         enum VIN_SOURCE_FORMAT format;
 403         u8 fps;
 404 };
 405
 406 struct stf_vin_dev {
 407         /* Protects the access of variables shared within the interrupt */
 408         spinlock_t irqlock;
 409         int irq;
 410         struct device *dev;
 411         struct cdev vin_cdev;
 412         void __iomem *base;
 413         void __iomem *csi2rx_base;
 414         void __iomem *clkgen_base;
 415         void __iomem *rstgen_base;
 416         void __iomem *sysctrl_base;
 417         void __iomem *isp_base;
 418         void __iomem *vin_top_clkgen_base;
 419         void __iomem *vin_top_rstgen_base;
 420         void __iomem *vin_top_iopad_base;
 421         void __iomem *pmu_test;
 422         void __iomem *sys_crg;
 423         struct vin_framesize frame;
 424         struct vin_format format;
 425         bool isp;
 426         int isp_irq;
 427         int isp_csi_irq;
 428         int isp_scd_irq;
 429         int isp_irq_csiline;
 430         u32 major;
 431         struct vin_buf buf;
 432
 433         wait_queue_head_t wq;
 434         bool condition;
 435         int odd;
 436
 437         csi_format csi_fmt;
 438 };
 439
 440 extern int vin_notifier_register(struct notifier_block *nb);
 441 extern void vin_notifier_unregister(struct notifier_block *nb);
 442 extern int vin_notifier_call(unsigned long e, void *v);
 443 #endif