include/video/sprd_isp.h

   1 /*
   2  * Copyright (C) 2012 Spreadtrum Communications Inc.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13  #ifndef _ISP_DRV_KERNEL_H_
  14  #define _ISP_DRV_KERNEL_H_
  15
  16 #define ISP_BYPASS_EB                      1
  17 #define ISP_BYPASS_DIS                      0
  18 #define ISP_AWBM_ITEM                      1024
  19 #define ISP_HIST_ITEM                      256
  20 #define ISP_HDR_COMP_ITEM                  64
  21 #define ISP_HDR_P2E_ITEM                   32
  22 #define ISP_HDR_E2P_ITEM                   32
  23 #define ISP_AEM_ITEM                       1024
  24
  25
  26 #define ISP_RAW_AWBM_ITEM                  256
  27 #define ISP_RAW_AEM_ITEM                   1024
  28 #define ISP_3D_LUT_ITEM                    729
  29 #define ISP_RAW_AFM_ITEM                   25
  30 #define ISP_YIQ_AFM_ITEM                   100
  31 #define ISP_HSV_ITEM                       361
  32
  33
  34 #define ISP_CMC_MATRIX_TAB_MAX             9
  35 #define ISP_GAMMA_NODE_MAX                 66
  36 #define ISP_CCE_MATRIX_TAB_MAX             9
  37 #define ISP_CCE_UVD_NUM                    7
  38 #define ISP_CCE_UVC0_NUM                   2
  39 #define ISP_CCE_UVC1_NUM                   3
  40 #define ISP_AFM_WIN_NUM                    9
  41 #define ISP_CSS_LOWER_NUM                  7
  42 #define ISP_CSS_LOWER_SUM_NUM              7
  43 #define ISP_CSS_RATIO_NUM                  8
  44 #define ISP_NLC_R_NODE_NUM                 29
  45 #define ISP_NLC_G_NODE_NUM                 29
  46 #define ISP_NLC_B_NODE_NUM                 29
  47 #define ISP_NLC_L_NODE_NUM                 27
  48 #define ISP_YIQ_YGAMMA_XNODE_NUM           8
  49 #define ISP_YIQ_YGAMMA_YNODE_NUM           10
  50 #define ISP_YIQ_YGAMMA_NODE_INDEX_NUM      9
  51 #define ISP_PINGPANG_YUV_YGAMC_NUM         129
  52
  53
  54 enum isp_chip_id {
  55         ISP_CHIP_ID_INVALID = 0x00,
  56         ISP_CHIP_ID_SC8820 = 0xA55A8820,
  57         ISP_CHIP_ID_SC9630 = 0xA55A9630,
  58         ISP_CHIP_ID_SC9930 = 0xA55A9930
  59 };
  60
  61 enum isp_interrupt_mode {
  62         ISP_INT_VIDEO_MODE = 0x00,
  63         ISP_INT_CAPTURE_MODE,
  64         ISP_INT_CLEAR_MODE
  65 };
  66
  67  enum isp_clk_sel {
  68         ISP_CLK_480M = 0,
  69         ISP_CLK_384M,
  70         ISP_CLK_312M,
  71         ISP_CLK_256M,
  72         ISP_CLK_128M,
  73         ISP_CLK_76M8,
  74         ISP_CLK_48M,
  75         ISP_CLK_NONE
  76 };
  77
  78 enum {
  79         ISP_LNC_STATUS_OK = (1<<0),
  80 };
  81
  82 enum {
  83         ISP_INT_HIST_STORE = (1<<0),
  84         ISP_INT_STORE = (1<<1),
  85         ISP_INT_LSC_LOAD = (1<<2),
  86         ISP_INT_HIST_CAL = (1<<3),
  87         ISP_INT_HIST_RST = (1<<4),
  88         ISP_INT_FETCH_BUF_FULL = (1<<5),
  89         ISP_INT_STORE_BUF_FULL = (1<<6),
  90         ISP_INT_STORE_ERR = (1<<7),
  91         ISP_INT_SHADOW = (1<<8),
  92         ISP_INT_PREVIEW_STOP = (1<<9),
  93         ISP_INT_AWB_DONE = (1<<10),
  94         ISP_INT_AF_DONE = (1<<11),
  95         ISP_INT_SLICE_CNT = (1<<12),
  96         ISP_INT_AE_DONE = (1<<13),
  97         ISP_INT_ANTI_FLICKER = (1<<14),
  98         ISP_INT_AWB_START = (1<<15),
  99         ISP_INT_AF_START = (1<<16),
 100         ISP_INT_AE_START = (1<<17),
 101         ISP_INT_DCAM_SOF = (1<<18),
 102         ISP_INT_DCAM_EOF = (1<<19),
 103         ISP_INT_AFM_WIN8 = (1<<20),
 104         ISP_INT_AFM_WIN7 = (1<<21),
 105         ISP_INT_AFM_WIN6 = (1<<22),
 106         ISP_INT_AFM_WIN5 = (1<<23),
 107         ISP_INT_AFM_WIN4 = (1<<24),
 108         ISP_INT_AFM_WIN3 = (1<<25),
 109         ISP_INT_AFM_WIN2 = (1<<26),
 110         ISP_INT_AFM_WIN1 = (1<<27),
 111         ISP_INT_AFM_WIN0 = (1<<28),
 112 };
 113
 114 /*********pike**********/
 115 enum {
 116         ISP_INT_P_ISP_ALL_DONE = (1<<0),
 117         ISP_INT_P_STORE_DONE = (1<<1),
 118         ISP_INT_P_LENS_LOAD = (1<<2),
 119         ISP_INT_P_ISP_START = (1<<3),
 120         ISP_INT_P_ISP_BUF_FULL = (1<<4),
 121         ISP_INT_P_DCAM_BUF_FULL = (1<<5),
 122         ISP_INT_P_STORE_BUF_FULL = (1<<6),
 123         ISP_INT_P_SHADOW_DONE = (1<<7),
 124         ISP_INT_P_AWBM_DONE = (1<<8),
 125         ISP_INT_P_AFM_DONE = (1<<9),
 126         ISP_INT_P_AEM_DONE = (1<<10),
 127         ISP_INT_P_AEM2_DONE = (1<<11),
 128         ISP_INT_P_ANTI_FILCKER_DONE = (1<<12),
 129         ISP_INT_P_BINNING_DONE = (1<<13),
 130         ISP_INT_P_DCAM_SOF = (1<<14),
 131         ISP_INT_P_DCAM_EOF = (1<<15),
 132         ISP_INT_P_HIST_CAL = (1<<16),
 133         ISP_INT_P_HIST_RST = (1<<17),
 134         ISP_INT_P_HIST2 = (1<<18),
 135         ISP_INT_P_LENS_ERR = (1<<19),
 136         ISP_INT_P_AWBM_ERR = (1<<20),
 137         ISP_INT_P_BINNING_ERR = (1<<21),
 138         ISP_INT_P_BINNING_ERR1 = (1<<22),
 139         ISP_INT_P_BPC_ERR2 = (1<<23),
 140         ISP_INT_P_BPC_ERR1 = (1<<24),
 141         ISP_INT_P_BPC_ERR0 = (1<<25),
 142         ISP_INT_P_AFM_START = (1<<26),
 143         ISP_INT_P_AEM_START = (1<<27),
 144         ISP_INT_P_AEM2_START = (1<<28),
 145 };
 146
 147 enum {
 148         ISP_INT_P_AFM_Y_WIN0 = (1<<0),
 149         ISP_INT_P_AFM_Y_WIN1 = (1<<1),
 150         ISP_INT_P_AFM_Y_WIN2 = (1<<2),
 151         ISP_INT_P_AFM_Y_WIN3 = (1<<3),
 152         ISP_INT_P_AFM_Y_WIN4 = (1<<4),
 153         ISP_INT_P_AFM_Y_WIN5 = (1<<5),
 154         ISP_INT_P_AFM_Y_WIN6 = (1<<6),
 155         ISP_INT_P_AFM_Y_WIN7 = (1<<7),
 156         ISP_INT_P_AFM_Y_WIN8 = (1<<8),
 157         ISP_INT_P_AFM_Y_WIN9 = (1<<9),
 158         ISP_INT_P_AFM_Y_WIN10 = (1<<10),
 159         ISP_INT_P_AFM_Y_WIN11 = (1<<11),
 160         ISP_INT_P_AFM_Y_WIN12 = (1<<12),
 161         ISP_INT_P_AFM_Y_WIN13 = (1<<13),
 162         ISP_INT_P_AFM_Y_WIN14 = (1<<14),
 163         ISP_INT_P_AFM_Y_WIN15 = (1<<15),
 164         ISP_INT_P_AFM_Y_WIN16 = (1<<16),
 165         ISP_INT_P_AFM_Y_WIN17 = (1<<17),
 166         ISP_INT_P_AFM_Y_WIN18 = (1<<18),
 167         ISP_INT_P_AFM_Y_WIN19 = (1<<19),
 168         ISP_INT_P_AFM_Y_WIN20 = (1<<20),
 169         ISP_INT_P_AFM_Y_WIN21 = (1<<21),
 170         ISP_INT_P_AFM_Y_WIN22 = (1<<22),
 171         ISP_INT_P_AFM_Y_WIN23 = (1<<23),
 172         ISP_INT_P_AFM_Y_WIN24 = (1<<24),
 173 };
 174
 175 enum {
 176         ISP_INT_P_AFM_RGB_WIN0 = (1<<0),
 177         ISP_INT_P_AFM_RGB_WIN1 = (1<<1),
 178         ISP_INT_P_AFM_RGB_WIN2 = (1<<2),
 179         ISP_INT_P_AFM_RGB_WIN3 = (1<<3),
 180         ISP_INT_P_AFM_RGB_WIN4 = (1<<4),
 181         ISP_INT_P_AFM_RGB_WIN5 = (1<<5),
 182         ISP_INT_P_AFM_RGB_WIN6 = (1<<6),
 183         ISP_INT_P_AFM_RGB_WIN7 = (1<<7),
 184         ISP_INT_P_AFM_RGB_WIN8 = (1<<8),
 185         ISP_INT_P_AFM_RGB_WIN9 = (1<<9),
 186         ISP_INT_P_AFM_RGB_WIN10 = (1<<10),
 187         ISP_INT_P_AFM_RGB_WIN11 = (1<<11),
 188         ISP_INT_P_AFM_RGB_WIN12 = (1<<12),
 189         ISP_INT_P_AFM_RGB_WIN13 = (1<<13),
 190         ISP_INT_P_AFM_RGB_WIN14 = (1<<14),
 191         ISP_INT_P_AFM_RGB_WIN15 = (1<<15),
 192         ISP_INT_P_AFM_RGB_WIN16 = (1<<16),
 193         ISP_INT_P_AFM_RGB_WIN17 = (1<<17),
 194         ISP_INT_P_AFM_RGB_WIN18 = (1<<18),
 195         ISP_INT_P_AFM_RGB_WIN19 = (1<<19),
 196         ISP_INT_P_AFM_RGB_WIN20 = (1<<20),
 197         ISP_INT_P_AFM_RGB_WIN21 = (1<<21),
 198         ISP_INT_P_AFM_RGB_WIN22 = (1<<22),
 199         ISP_INT_P_AFM_RGB_WIN23 = (1<<23),
 200         ISP_INT_P_AFM_RGB_WIN24 = (1<<24),
 201 };
 202
 203 enum {
 204         ISP_INT_P_YUV_DONE = (1<<0),
 205         ISP_INT_P_YUV_POSTCDN = (1<<1),
 206         ISP_INT_P_YUV_CDN_DONE = (1<<2),
 207         ISP_INT_P_YUV_EE_DONE = (1<<3),
 208         ISP_INT_P_YUV_NLM_DONE = (1<<4),
 209         ISP_INT_P_YUV_PRF_UV_DONE = (1<<5),
 210         ISP_INT_P_YUV_PRF_Y_DONE = (1<<6),
 211         ISP_INT_P_YUV_START = (1<<7),
 212         ISP_INT_P_FRGB_CCE_DONE = (1<<8),
 213         ISP_INT_P_FRGB_CCE_START = (1<<9),
 214         ISP_INT_P_FRGB_DONE = (1<<10),
 215         ISP_INT_P_FRGB_START = (1<<11),
 216         ISP_INT_P_FRGB_CF_AE_DONE = (1<<12),
 217         ISP_INT_P_FRGB_CF_AE_START = (1<<13),
 218         ISP_INT_P_RRGB_DONE = (1<<14),
 219         ISP_INT_P_RRGB_BDN_DONE = (1<<15),
 220         ISP_INT_P_RRGB_PWD_DONE = (1<<16),
 221         ISP_INT_P_RRGB_BPC_DONE = (1<<17),
 222         ISP_INT_P_RRGB_LENS_DONE = (1<<18),
 223         ISP_INT_P_RRGB_NLM_DONE = (1<<19),
 224         ISP_INT_P_RRGB_START = (1<<20),
 225 };
 226
 227 /*********tshark2***********/
 228 enum {
 229         ISP_INT_ISP_ALL_DONE = (1<<0),
 230         ISP_INT_SHADOW_DONE = (1<<1),
 231         ISP_INT_STORE_DONE = (1<<2),
 232         ISP_INT_ISP_STRAT = (1<<3),
 233         ISP_INT_FETCH_BUFFER_FULL = (1<<4),
 234         ISP_INT_STORE_BUFFER_FULL = (1<<5),
 235         ISP_INT_ISP2DCAM_AFIFO_FULL = (1<<6),
 236         ISP_INT_LSC_LOAD_DONE = (1<<7),
 237         ISP_INT_AEM_START = (1<<8),
 238         ISP_INT_AEM_DONE = (1<<9),
 239         ISP_INT_AEM2_START = (1<<10),
 240         ISP_INT_AEM2_DONE = (1<<11),
 241         ISP_INT_AFM_Y_START = (1<<12),
 242         ISP_INT_AFM_Y_DONE = (1<<13),
 243         ISP_INT_AFM_RGB_START = (1<<14),
 244         ISP_INT_AFM_RGB_DONE = (1<<15),
 245         ISP_INT_AWBM_START = (1<<16),
 246         ISP_INT_AWBM_DONE = (1<<17),
 247         ISP_INT_BINNING_DONE = (1<<18),
 248         ISP_INT_BINNING_START = (1<<19),
 249         ISP_INT_AFL_START = (1<<20),
 250         ISP_INT_AFL_DONE = (1<<21),
 251         ISP_INT_DCAMERA_SOF = (1<<22),
 252         ISP_INT_DCAMERA_EOF = (1<<23),
 253         ISP_INT_HIST_START = (1<<24),
 254         ISP_INT_HIST_DONE = (1<<25),
 255         ISP_INT_HIST2_START = (1<<26),
 256         ISP_INT_HIST2_DONE = (1<<27),
 257         ISP_INT_HIST2_WIN0_DONE = (1<<28),
 258         ISP_INT_HIST2_WIN1_DONE = (1<<29),
 259         ISP_INT_HIST2_WIN2_DONE = (1<<30),
 260         ISP_INT_HIST2_WIN3_DONE = (1<<31),
 261 };
 262
 263 enum {
 264         ISP_INT_AFM_Y_WIN0 = (1<<0),
 265         ISP_INT_AFM_Y_WIN1 = (1<<1),
 266         ISP_INT_AFM_Y_WIN2 = (1<<2),
 267         ISP_INT_AFM_Y_WIN3 = (1<<3),
 268         ISP_INT_AFM_Y_WIN4 = (1<<4),
 269         ISP_INT_AFM_Y_WIN5 = (1<<5),
 270         ISP_INT_AFM_Y_WIN6 = (1<<6),
 271         ISP_INT_AFM_Y_WIN7 = (1<<7),
 272         ISP_INT_AFM_Y_WIN8 = (1<<8),
 273         ISP_INT_AFM_Y_WIN9 = (1<<9),
 274         ISP_INT_AFM_Y_WIN10 = (1<<10),
 275         ISP_INT_AFM_Y_WIN11 = (1<<11),
 276         ISP_INT_AFM_Y_WIN12 = (1<<12),
 277         ISP_INT_AFM_Y_WIN13 = (1<<13),
 278         ISP_INT_AFM_Y_WIN14 = (1<<14),
 279         ISP_INT_AFM_Y_WIN15 = (1<<15),
 280         ISP_INT_AFM_Y_WIN16 = (1<<16),
 281         ISP_INT_AFM_Y_WIN17 = (1<<17),
 282         ISP_INT_AFM_Y_WIN18 = (1<<18),
 283         ISP_INT_AFM_Y_WIN19 = (1<<19),
 284         ISP_INT_AFM_Y_WIN20 = (1<<20),
 285         ISP_INT_AFM_Y_WIN21 = (1<<21),
 286         ISP_INT_AFM_Y_WIN22 = (1<<22),
 287         ISP_INT_AFM_Y_WIN23 = (1<<23),
 288         ISP_INT_AFM_Y_WIN24 = (1<<24),
 289         ISP_INT_DISPATCH_BUF_FULL = (1<<25),
 290         ISP_INT_AWBM_ERR = (1<<26),
 291         ISP_INT_BINNING_ERR1 = (1<<27),
 292         ISP_INT_BINNING_ERR0 = (1<<28),
 293         ISP_INT_BPC_ERR2 = (1<<29),
 294         ISP_INT_BPC_ERR1 = (1<<30),
 295         ISP_INT_BPC_ERR0 = (1<<31),
 296 };
 297
 298 enum {
 299         ISP_INT_AFM_RGB_WIN0 = (1<<0),
 300         ISP_INT_AFM_RGB_WIN1 = (1<<1),
 301         ISP_INT_AFM_RGB_WIN2 = (1<<2),
 302         ISP_INT_AFM_RGB_WIN3 = (1<<3),
 303         ISP_INT_AFM_RGB_WIN4 = (1<<4),
 304         ISP_INT_AFM_RGB_WIN5 = (1<<5),
 305         ISP_INT_AFM_RGB_WIN6 = (1<<6),
 306         ISP_INT_AFM_RGB_WIN7 = (1<<7),
 307         ISP_INT_AFM_RGB_WIN8 = (1<<8),
 308         ISP_INT_AFM_RGB_WIN9 = (1<<9),
 309         ISP_INT_AFM_RGB_WIN10 = (1<<10),
 310         ISP_INT_AFM_RGB_WIN11 = (1<<11),
 311         ISP_INT_AFM_RGB_WIN12 = (1<<12),
 312         ISP_INT_AFM_RGB_WIN13 = (1<<13),
 313         ISP_INT_AFM_RGB_WIN14 = (1<<14),
 314         ISP_INT_AFM_RGB_WIN15 = (1<<15),
 315         ISP_INT_AFM_RGB_WIN16 = (1<<16),
 316         ISP_INT_AFM_RGB_WIN17 = (1<<17),
 317         ISP_INT_AFM_RGB_WIN18 = (1<<18),
 318         ISP_INT_AFM_RGB_WIN19 = (1<<19),
 319         ISP_INT_AFM_RGB_WIN20 = (1<<20),
 320         ISP_INT_AFM_RGB_WIN21 = (1<<21),
 321         ISP_INT_AFM_RGB_WIN22 = (1<<22),
 322         ISP_INT_AFM_RGB_WIN23 = (1<<23),
 323         ISP_INT_AFM_RGB_WIN24 = (1<<24),
 324 };
 325
 326 enum {
 327         ISP_INT_EVT_STOP = (1<<31),
 328 };
 329
 330 enum {
 331         ISP_INT_EVT_HIST_STORE = (1<<0),
 332         /*ISP_INT_EVT_STORE = (1<<1),*/
 333         /*ISP_INT_EVT_LSC_LOAD = (1<<2),*/
 334         ISP_INT_EVT_HIST_CAL = (1<<3),
 335         ISP_INT_EVT_HIST_RST = (1<<4),
 336         /*ISP_INT_EVT_FETCH_BUF_FULL = (1<<5),*/
 337         /*ISP_INT_EVT_STORE_BUF_FULL = (1<<6),*/
 338         ISP_INT_EVT_STORE_ERR = (1<<7),
 339         /*ISP_INT_EVT_SHADOW = (1<<8),*/
 340         ISP_INT_EVT_PREVIEW_STOP = (1<<9),
 341         /*ISP_INT_EVT_AWB = (1<<10),*/
 342         /*ISP_INT_EVT_AF = (1<<11),*/
 343         ISP_INT_EVT_SLICE_CNT = (1<<12),
 344         /*ISP_INT_EVT_AE = (1<<13),*/
 345         /*ISP_INT_EVT_ANTI_FLICKER = (1<<14),*/
 346         /*ISP_INT_EVT_AWBM_START = (1<<15),*/
 347         /*ISP_INT_EVT_AFM_START = (1<<16),*/
 348         /*ISP_INT_EVT_AE_START = (1<<17),*/
 349         /*ISP_INT_EVT_DCAM_SOF = (1<<18),*/
 350         /*ISP_INT_EVT_DCAM_EOF = (1<<19),*/
 351         /*ISP_INT_EVT_AFM_WIN8 = (1<<20),*/
 352         /*ISP_INT_EVT_AFM_WIN7 = (1<<21),*/
 353         /*ISP_INT_EVT_AFM_WIN6 = (1<<22),*/
 354         /*ISP_INT_EVT_AFM_WIN5 = (1<<23),*/
 355         /*ISP_INT_EVT_AFM_WIN4 = (1<<24),*/
 356         /*ISP_INT_EVT_AFM_WIN3 = (1<<25),*/
 357         /*ISP_INT_EVT_AFM_WIN2 = (1<<26),*/
 358         /*ISP_INT_EVT_AFM_WIN1 = (1<<27),*/
 359         /*ISP_INT_EVT_AFM_WIN0 = (1<<28),*/
 360 };
 361
 362 /*******tshark2*******/
 363 enum {
 364         ISP_INT_EVT_ISP_ALL_DONE = (1<<0),
 365         ISP_INT_EVT_SHADOW_DONE = (1<<1),
 366         ISP_INT_EVT_STORE_DONE = (1<<2),
 367         ISP_INT_EVT_ISP_STRAT = (1<<3),
 368         ISP_INT_EVT_FETCH_BUF_FULL = (1<<4),
 369         ISP_INT_EVT_STORE_BUF_FULL = (1<<5),
 370         ISP_INT_EVT_ISP2DCAM_AFIFO_FULL = (1<<6),
 371         ISP_INT_EVT_LSC_LOAD = (1<<7),
 372         ISP_INT_EVT_AEM_START = (1<<8),
 373         ISP_INT_EVT_AEM_DONE = (1<<9),
 374         ISP_INT_EVT_AEM2_START = (1<<10),
 375         ISP_INT_EVT_AEM2_DONE = (1<<11),
 376         ISP_INT_EVT_AFM_Y_START = (1<<12),
 377         ISP_INT_EVT_AFM_Y_DONE = (1<<13),
 378         ISP_INT_EVT_AFM_RGB_START = (1<<14),
 379         ISP_INT_EVT_AFM_RGB_DONE = (1<<15),
 380         ISP_INT_EVT_AWBM_START = (1<<16),
 381         ISP_INT_EVT_AWBM_DONE = (1<<17),
 382         ISP_INT_EVT_BINNING_DONE = (1<<18),
 383         ISP_INT_EVT_BINNING_START = (1<<19),
 384         ISP_INT_EVT_AFL_START = (1<<20),
 385         ISP_INT_EVT_AFL_DONE = (1<<21),
 386         ISP_INT_EVT_DCAM_SOF = (1<<22),
 387         ISP_INT_EVT_DCAM_EOF = (1<<23),
 388         ISP_INT_EVT_HIST_START = (1<<24),
 389         ISP_INT_EVT_HIST_DONE = (1<<25),
 390         ISP_INT_EVT_HIST2_START = (1<<26),
 391         ISP_INT_EVT_HIST2_DONE = (1<<27),
 392         ISP_INT_EVT_HIST2_WIN0_DONE = (1<<28),
 393         ISP_INT_EVT_HIST2_WIN1_DONE = (1<<29),
 394         ISP_INT_EVT_HIST2_WIN2_DONE = (1<<30),
 395         ISP_INT_EVT_HIST2_WIN3_DONE = (1<<31),
 396 };
 397
 398 enum {
 399         ISP_INT_EVT_AFM_Y_WIN0 = (1<<0),
 400         ISP_INT_EVT_AFM_Y_WIN1 = (1<<1),
 401         ISP_INT_EVT_AFM_Y_WIN2 = (1<<2),
 402         ISP_INT_EVT_AFM_Y_WIN3 = (1<<3),
 403         ISP_INT_EVT_AFM_Y_WIN4 = (1<<4),
 404         ISP_INT_EVT_AFM_Y_WIN5 = (1<<5),
 405         ISP_INT_EVT_AFM_Y_WIN6 = (1<<6),
 406         ISP_INT_EVT_AFM_Y_WIN7 = (1<<7),
 407         ISP_INT_EVT_AFM_Y_WIN8 = (1<<8),
 408         ISP_INT_EVT_AFM_Y_WIN9 = (1<<9),
 409         ISP_INT_EVT_AFM_Y_WIN10 = (1<<10),
 410         ISP_INT_EVT_AFM_Y_WIN11 = (1<<11),
 411         ISP_INT_EVT_AFM_Y_WIN12 = (1<<12),
 412         ISP_INT_EVT_AFM_Y_WIN13 = (1<<13),
 413         ISP_INT_EVT_AFM_Y_WIN14 = (1<<14),
 414         ISP_INT_EVT_AFM_Y_WIN15 = (1<<15),
 415         ISP_INT_EVT_AFM_Y_WIN16 = (1<<16),
 416         ISP_INT_EVT_AFM_Y_WIN17 = (1<<17),
 417         ISP_INT_EVT_AFM_Y_WIN18 = (1<<18),
 418         ISP_INT_EVT_AFM_Y_WIN19 = (1<<19),
 419         ISP_INT_EVT_AFM_Y_WIN20 = (1<<20),
 420         ISP_INT_EVT_AFM_Y_WIN21 = (1<<21),
 421         ISP_INT_EVT_AFM_Y_WIN22 = (1<<22),
 422         ISP_INT_EVT_AFM_Y_WIN23 = (1<<23),
 423         ISP_INT_EVT_AFM_Y_WIN24 = (1<<24),
 424         ISP_INT_EVT_DISPATCH_BUF_FULL = (1<<25),
 425         ISP_INT_EVT_AWBM_ERR = (1<<26),
 426         ISP_INT_EVT_BINNING_ERR1 = (1<<27),
 427         ISP_INT_EVT_BINNING_ERR0 = (1<<28),
 428         ISP_INT_EVT_BPC_ERR2 = (1<<29),
 429         ISP_INT_EVT_BPC_ERR1 = (1<<30),
 430         ISP_INT_EVT_BPC_ERR0 = (1<<31),
 431 };
 432
 433 enum {
 434         ISP_INT_EVT_AFM_RGB_WIN0 = (1<<0),
 435         ISP_INT_EVT_AFM_RGB_WIN1 = (1<<1),
 436         ISP_INT_EVT_AFM_RGB_WIN2 = (1<<2),
 437         ISP_INT_EVT_AFM_RGB_WIN3 = (1<<3),
 438         ISP_INT_EVT_AFM_RGB_WIN4 = (1<<4),
 439         ISP_INT_EVT_AFM_RGB_WIN5 = (1<<5),
 440         ISP_INT_EVT_AFM_RGB_WIN6 = (1<<6),
 441         ISP_INT_EVT_AFM_RGB_WIN7 = (1<<7),
 442         ISP_INT_EVT_AFM_RGB_WIN8 = (1<<8),
 443         ISP_INT_EVT_AFM_RGB_WIN9 = (1<<9),
 444         ISP_INT_EVT_AFM_RGB_WIN10 = (1<<10),
 445         ISP_INT_EVT_AFM_RGB_WIN11 = (1<<11),
 446         ISP_INT_EVT_AFM_RGB_WIN12 = (1<<12),
 447         ISP_INT_EVT_AFM_RGB_WIN13 = (1<<13),
 448         ISP_INT_EVT_AFM_RGB_WIN14 = (1<<14),
 449         ISP_INT_EVT_AFM_RGB_WIN15 = (1<<15),
 450         ISP_INT_EVT_AFM_RGB_WIN16 = (1<<16),
 451         ISP_INT_EVT_AFM_RGB_WIN17 = (1<<17),
 452         ISP_INT_EVT_AFM_RGB_WIN18 = (1<<18),
 453         ISP_INT_EVT_AFM_RGB_WIN19 = (1<<19),
 454         ISP_INT_EVT_AFM_RGB_WIN20 = (1<<20),
 455         ISP_INT_EVT_AFM_RGB_WIN21 = (1<<21),
 456         ISP_INT_EVT_AFM_RGB_WIN22 = (1<<22),
 457         ISP_INT_EVT_AFM_RGB_WIN23 = (1<<23),
 458         ISP_INT_EVT_AFM_RGB_WIN24 = (1<<24),
 459 };
 460
 461 enum isp_block {
 462         ISP_BLOCK_FETCH,
 463         ISP_BLOCK_BLC,
 464         ISP_BLOCK_2D_LSC,
 465         ISP_BLOCK_AWB,
 466         ISP_BLOCK_BPC,
 467         ISP_BLOCK_BDN,
 468         ISP_BLOCK_GRGB,
 469         ISP_BLOCK_CFA,
 470         ISP_BLOCK_CMC,
 471         ISP_BLOCK_GAMMA,
 472         ISP_BLOCK_CCE,
 473         ISP_BLOCK_PRE_FILTER,
 474         ISP_BLOCK_BRIGHTNESS,
 475         ISP_BLOCK_CONTRAST,
 476         ISP_BLOCK_HIST,
 477         ISP_BLOCK_ACA,
 478         ISP_BLOCK_AFM,
 479         ISP_BLOCK_EDGE,
 480         ISP_BLOCK_EMBOSS,
 481         ISP_BLOCK_FCS,
 482         ISP_BLOCK_CSS,
 483         ISP_BLOCK_CSA,
 484         ISP_BLOCK_STORE,
 485         ISP_BLOCK_FEEDER,
 486         ISP_BLOCK_ARBITER,
 487         ISP_BLOCK_HDR,
 488         ISP_BLOCK_NLC,
 489         ISP_BLOCK_NAWBM,
 490         ISP_BLOCK_PRE_WAVELET,
 491         ISP_BLOCK_BINNING4AWB,
 492         ISP_BLOCK_PRE_GLB_GAIN,
 493         ISP_BLOCK_COMMON,
 494         ISP_BLOCK_GLB_GAIN,
 495         ISP_BLOCK_RGB_GAIN,
 496         ISP_BLOCK_YIQ,
 497         ISP_BLOCK_HUE,
 498         ISP_BLOCK_NBPC,
 499 /***************Tshark2**************************************/
 500         ISP_BLOCK_1D_LSC,
 501         ISP_BLOCK_RAW_AEM,
 502
 503         ISP_BLOCK_RGB_GAIN2,
 504 //      ISP_BLOCK_VST,
 505         ISP_BLOCK_NLM,
 506 //      ISP_BLOCK_IVST,
 507
 508         ISP_BLOCK_CMC8,
 509         ISP_BLOCK_CT,
 510         ISP_BLOCK_HSV,
 511         ISP_BLOCK_CSC,
 512         ISP_BLOCK_PRE_CDN_RGB,
 513         ISP_BLOCK_POSTERIZE,
 514         ISP_BLOCK_AFM_V1,
 515         ISP_BLOCK_YIQ_AEM,
 516         ISP_BLOCK_ANTI_FLICKER,
 517         ISP_BLOCK_YIQ_AFM,
 518         ISP_BLOCK_YUV_PRECDN,
 519         ISP_BLOCK_PRE_FILTER_V1,
 520         ISP_BLOCK_HIST2,
 521         ISP_BLOCK_YUV_CDN,
 522         ISP_BLOCK_HUA,
 523         ISP_BLOCK_POST_CDN,
 524         ISP_BLOCK_YGAMMA,
 525         ISP_BLOCK_YDELAY,
 526         ISP_BLOCK_IIRCNR,
 527         ISP_BLOCK_DISPATCH,
 528         ISP_BLOCK_ARBITER_V1,
 529         ISP_BLOCK_COMMON_V1,
 530         ISP_BLOCK_RAW_SIZER,
 531 /***************pike**************************************/
 532 //      ISP_BLOCK_WDR,
 533         ISP_BLOCK_RGB2Y,
 534         ISP_BLOCK_UV_PREFILTER,
 535         ISP_BLOCK_YUV_NLM
 536
 537 };
 538
 539 enum isp_fetch_property {
 540         ISP_PRO_FETCH_BLOCK,
 541         ISP_PRO_FETCH_SLICE_SIZE,
 542         ISP_PRO_FETCH_START_ISP,
 543 };
 544
 545 enum isp_blc_property {
 546         ISP_PRO_BLC_BLOCK,
 547         ISP_PRO_BLC_SLICE_SIZE,
 548         ISP_PRO_BLC_SLICE_INFO,
 549 };
 550
 551 enum isp_2d_lsc_property {
 552         ISP_PRO_2D_LSC_BLOCK,
 553         ISP_PRO_2D_LSC_BYPASS,
 554         ISP_PRO_2D_LSC_PARAM_UPDATE,
 555         ISP_PRO_2D_LSC_POS,
 556         ISP_PRO_2D_LSC_GRID_SIZE,
 557         ISP_PRO_2D_LSC_LOAD_BUF_SEL,
 558         ISP_PRO_2D_LSC_SLICE_SIZE,
 559         ISP_PRO_2D_LSC_TRANSADDR,
 560
 561 };
 562
 563 enum isp_1d_lsc_property {
 564         ISP_PRO_1D_LSC_BLOCK,
 565         ISP_PRO_1D_LSC_SLICE_SIZE,
 566         ISP_PRO_1D_LSC_POS,
 567 };
 568
 569 enum isp_awb_property {
 570         ISP_PRO_AWB_BLOCK,
 571         ISP_PRO_AWBM_STATISTICS,
 572         ISP_PRO_AWBM_BYPASS,
 573         ISP_PRO_AWBM_MODE,
 574         ISP_PRO_AWBM_SKIP_NUM,
 575         ISP_PRO_AWBM_SKIP_NUM_CLR,
 576         ISP_PRO_AWBM_BLOCK_OFFSET,
 577         ISP_PRO_AWBM_BLOCK_SIZE,
 578         ISP_PRO_AWBM_SHIFT,
 579         ISP_PRO_AWBM_THR_BYPASS,
 580         ISP_PRO_AWBM_WR_POS,
 581         ISP_PRO_AWBM_NW_POS,
 582         ISP_PRO_AWBM_CLCTOR_POS,
 583         ISP_PRO_AWBM_CLCTOR_PIXEL_NUM,
 584         ISP_PRO_AWBM_THR_VALUE,
 585         ISP_PRO_AWBM_MEM_ADDR,
 586         ISP_PRO_AWBC_BYPASS,
 587         ISP_PRO_AWBC_GAIN,
 588         ISP_PRO_AWBC_THRD,
 589         ISP_PRO_AWBC_GAIN_OFFSET,
 590 };
 591
 592 enum isp_bpc_property {
 593         ISP_PRO_BPC_BLOCK,
 594         ISP_PRO_BPC_BYPASS,
 595         ISP_PRO_BPC_MODE,
 596         ISP_PRO_BPC_PARAM_COMMON,
 597         ISP_PRO_BPC_THRD,
 598         ISP_PRO_BPC_MAP_ADDR,
 599         ISP_PRO_BPC_PIXEL_NUM,
 600         ISP_PRO_BPC_DIFF_THRD,
 601 };
 602
 603 enum isp_wavelet_denoise_property {
 604         ISP_PRO_BDN_BLOCK,
 605         ISP_PRO_BDN_BYPASS,
 606         ISP_PRO_BDN_SLICE_SIZE,
 607         ISP_PRO_BDN_DISWEI,
 608         ISP_PRO_BDN_RANWEI,
 609 };
 610
 611 enum isp_grgb_property {
 612         ISP_PRO_GRGB_BLOCK,
 613         ISP_PRO_GRGB_BYPASS,
 614         ISP_PRO_GRGB_THRD,
 615 };
 616
 617 enum isp_cfa_property {
 618         ISP_PRO_CFA_BLOCK,
 619         ISP_PRO_CFA_THRD,
 620         ISP_PRO_CFA_SLICE_SIZE,
 621         ISP_PRO_CFA_SLICE_INFO,
 622 };
 623
 624 enum isp_cmc_property {
 625         ISP_PRO_CMC_BLOCK,
 626         ISP_PRO_CMC_BYPASS,
 627         ISP_PRO_CMC_MATRIX,
 628 };
 629
 630 enum isp_gamma_property {
 631         ISP_PRO_GAMMA_BLOCK,
 632         ISP_PRO_GAMMA_BYPASS,
 633         ISP_PRO_GAMMA_NODE,
 634 };
 635
 636 enum isp_cce_property {
 637         ISP_PRO_CCE_BLOCK_MATRIX,
 638         ISP_PRO_CCE_BLOCK_UV,
 639         ISP_PRO_CCE_UVDIVISION_BYPASS,
 640         ISP_PRO_CCE_MODE,
 641         ISP_PRO_CCE_MATRIX,
 642         ISP_PRO_CCE_SHIFT,
 643         ISP_PRO_CCE_UVD_THRD,
 644         ISP_PRO_CCE_UVC_PARAM,
 645 };
 646
 647 enum isp_prefilter_property {
 648         ISP_PRO_PREF_BLOCK,
 649         ISP_PRO_PREF_BYPASS,
 650         ISP_PRO_PREF_WRITEBACK,
 651         ISP_PRO_PREF_THRD,
 652         ISP_PRO_PREF_SLICE_SIZE,
 653         ISP_PRO_PREF_SLICE_INFO,
 654 };
 655
 656 enum isp_brightness_property {
 657         ISP_PRO_BRIGHT_BLOCK,
 658         ISP_PRO_BRIGHT_SLICE_SIZE,
 659         ISP_PRO_BRIGHT_SLICE_INFO,
 660 };
 661
 662 enum isp_contrast_property {
 663         ISP_PRO_CONTRAST_BLOCK,
 664 };
 665
 666 enum isp_hist_property {
 667         ISP_PRO_HIST_BLOCK,
 668         ISP_PRO_HIST_BYPASS,
 669         ISP_PRO_HIST_AUTO_RST_DISABLE,
 670         ISP_PRO_HIST_MODE,
 671         ISP_PRO_HIST_RATIO,
 672         ISP_PRO_HIST_MAXMIN,
 673         ISP_PRO_HIST_CLEAR_EB,
 674         ISP_PRO_HIST_STATISTIC,
 675         ISP_PRO_HIST_STATISTIC_NUM,
 676         ISP_PRO_HIST_SLICE_SIZE,
 677 };
 678
 679 enum isp_autocont_property {
 680         ISP_PRO_ACA_BLOCK,
 681         ISP_PRO_ACA_BYPASS,
 682         ISP_PRO_ACA_MODE,
 683         ISP_PRO_ACA_MAXMIN,
 684         ISP_PRO_ACA_ADJUST,
 685 };
 686
 687 enum isp_afm_property {
 688         ISP_PRO_AFM_BLOCK,
 689         ISP_PRO_AFM_BYPASS,
 690         ISP_PRO_AFM_SHIFT,
 691         ISP_PRO_AFM_MODE,
 692         ISP_PRO_AFM_SKIP_NUM,
 693         ISP_PRO_AFM_SKIP_NUM_CLR,
 694         ISP_PRO_AFM_WIN,
 695         ISP_PRO_AFM_STATISTIC,
 696         ISP_PRO_AFM_WIN_NUM
 697 };
 698
 699 enum isp_edge_property {
 700         ISP_PRO_EDGE_BLOCK,
 701         ISP_PRO_EDGE_BYPASS,
 702         ISP_PRO_EDGE_PARAM,
 703 };
 704
 705 enum isp_emboss_property {
 706         ISP_PRO_EMBOSS_BLOCK,
 707         ISP_PRO_EMBOSS_BYPASS,
 708         ISP_PRO_EMBOSS_PARAM,
 709 };
 710
 711 enum isp_fcs_property {
 712         ISP_PRO_FCS_BLOCK,
 713         ISP_PRO_FCS_BYPASS,
 714         ISP_PRO_FCS_MODE,
 715 };
 716
 717 enum isp_css_property {
 718         ISP_PRO_CSS_BLOCK,
 719         ISP_PRO_CSS_BYPASS,
 720         ISP_PRO_CSS_THRD,
 721         ISP_PRO_CSS_SLICE_SIZE,
 722         ISP_PRO_CSS_RATIO,
 723 };
 724
 725 enum isp_csa_property {
 726         ISP_PRO_CSA_BLOCK,
 727         ISP_PRO_CSA_BYPASS,
 728         ISP_PRO_CSA_FACTOR,
 729 };
 730
 731 enum isp_store_property {
 732         ISP_PRO_STORE_BLOCK,
 733         ISP_PRO_STORE_SLICE_SIZE,
 734 };
 735
 736 enum isp_feeder_property {
 737         ISP_PRO_FEEDER_BLOCK,
 738         ISP_PRO_FEEDER_DATA_TYPE,
 739         ISP_PRO_FEEDER_SLICE_SIZE,
 740 };
 741
 742 enum isp_hdr_property {
 743         ISP_PRO_HDR_BLOCK,
 744         ISP_PRO_HDR_BYPASS,
 745         ISP_PRO_HDR_LEVEL,
 746         ISP_PRO_HDR_INDEX,
 747         ISP_PRO_HDR_TAB,
 748 };
 749
 750 enum isp_nlc_property {
 751         ISP_PRO_NLC_BLOCK,
 752         ISP_PRO_NLC_BYPASS,
 753         ISP_PRO_NLC_R_NODE,
 754         ISP_PRO_NLC_G_NODE,
 755         ISP_PRO_NLC_B_NODE,
 756         ISP_PRO_NLC_L_NODE,
 757 };
 758
 759 enum isp_nawbm_property {
 760         ISP_PRO_NAWBM_BLOCK,
 761         ISP_PRO_NAWBM_BYPASS,
 762 };
 763
 764 enum isp_pre_wavelet_property {
 765         ISP_PRO_PRE_WAVELET_BLOCK,
 766         ISP_PRO_PRE_WAVELET_BYPASS,
 767 };
 768
 769 enum isp_binging4awb_property {
 770         ISP_PRO_BINNING4AWB_BLOCK,
 771         ISP_PRO_BINNING4AWB_BYPASS,
 772         ISP_PRO_BINNING4AWB_SCALING_RATIO,
 773         ISP_PRO_BINNING4AWB_MEM_ADDR,
 774         ISP_PRO_BINNING4AWB_STATISTICS_BUF,
 775         ISP_PRO_BINNING4AWB_TRANSADDR,
 776 };
 777
 778 enum isp_pre_glb_gain_property {
 779         ISP_PRO_PRE_GLB_GAIN_BLOCK,
 780 };
 781
 782 enum isp_common_property {
 783         ISP_PRO_COMMON_START,
 784         ISP_PRO_COMMON_IN_MODE,
 785         ISP_PRO_COMMON_OUT_MODE,
 786         ISP_PRO_COMMON_FETCH_ENDIAN,
 787         ISP_PRO_COMMON_BPC_ENDIAN,
 788         ISP_PRO_COMMON_STORE_ENDIAN,
 789         ISP_PRO_COMMON_FETCH_DATA_FORMAT,
 790         ISP_PRO_COMMON_STORE_FORMAT,
 791         ISP_PRO_COMMON_BURST_SIZE,
 792         ISP_PRO_COMMON_MEM_SWITCH,
 793         ISP_PRO_COMMON_SHADOW,
 794         ISP_PRO_COMMON_SHADOW_ALL,
 795         ISP_PRO_COMMON_BAYER_MODE,
 796         ISP_PRO_COMMON_INT_REGISTER,
 797         ISP_PRO_COMMON_INT_CLEAR,
 798         ISP_PRO_COMMON_GET_INT_RAW,
 799         ISP_PRO_COMMON_PMU_RAW_MASK,
 800         ISP_PRO_COMMON_HW_MASK,
 801         ISP_PRO_COMMON_HW_ENABLE,
 802         ISP_PRO_COMMON_PMU_SEL,
 803         ISP_PRO_COMMON_SW_ENABLE,
 804         ISP_PRO_COMMON_PREVIEW_STOP,
 805         ISP_PRO_COMMON_SET_SHADOW_CONTROL,
 806         ISP_PRO_COMMON_SHADOW_CONTROL_CLEAR,
 807         ISP_PRO_COMMON_AXI_STOP,
 808         ISP_PRO_COMMON_SLICE_CNT_ENABLE,
 809         ISP_PRO_COMMON_PREFORM_CNT_ENABLE,
 810         ISP_PRO_COMMON_SET_SLICE_NUM,
 811         ISP_PRO_COMMON_GET_SLICE_NUM,
 812         ISP_PRO_COMMON_PERFORM_CNT_RSTATUS,
 813         ISP_PRO_COMMON_PERFORM_CNT_STATUS,
 814 };
 815
 816 enum isp_glb_gain_property {
 817         ISP_PRO_GLB_GAIN_BLOCK,
 818         ISP_PRO_GLB_GAIN_BYPASS,
 819         ISP_PRO_GLB_GAIN_SET,
 820         ISP_PRO_GLB_GAIN_SLICE_SIZE,
 821 };
 822
 823 enum isp_rgb_gain_property {
 824         ISP_PRO_RGB_GAIN_BLOCK,
 825 };
 826
 827 enum isp_yiq_property {
 828         ISP_RPO_YIQ_BLOCK_YGAMMA,
 829         ISP_RPO_YIQ_BLOCK_AE,
 830         ISP_RPO_YIQ_BLOCK_FLICKER,
 831         ISP_PRO_YIQ_YGAMMA_BYPASS,
 832         ISP_PRO_YIQ_YGAMMA_XNODE,
 833         ISP_PRO_YIQ_YGAMMA_YNODE,
 834         ISP_PRO_YIQ_YGAMMA_INDEX,
 835         ISP_PRO_YIQ_AE_BYPASS,
 836         ISP_PRO_YIQ_AE_SOURCE_SEL,
 837         ISP_PRO_YIQ_AE_MODE,
 838         ISP_PRO_YIQ_AE_SKIP_NUM,
 839         ISP_PRO_YIQ_FLICKER_BYPASS,
 840         ISP_PRO_YIQ_FLICKER_MODE,
 841         ISP_PRO_YIQ_FLICKER_VHEIGHT,
 842         ISP_PRO_YIQ_FLICKER_LINE_CONTER,
 843         ISP_PRO_YIQ_FLICKER_LINE_STEP,
 844         ISP_PRO_YIQ_FLICKER_LINE_START,
 845 };
 846
 847 enum isp_hue_property {
 848         ISP_PRO_HUE_BLOCK,
 849         ISP_PRO_HUE_BYPASS,
 850         ISP_PRO_HUE_FACTOR,
 851 };
 852
 853 enum isp_nbpc_property {
 854         ISP_PRO_NBPC_BLOCK,
 855         ISP_PRO_NBPC_BYPASS,
 856 };
 857
 858 /****************Tshark2****************************/
 859 enum isp_raw_aem_property {
 860         ISP_PRO_RAW_AEM_BLOCK,
 861         ISP_PRO_RAW_AEM_BYPASS,
 862         ISP_PRO_RAW_AEM_STATISTICS,
 863         ISP_PRO_RAW_AEM_SKIP_NUM,
 864         ISP_PRO_RAW_AEM_SHIFT,
 865         ISP_PRO_RAW_AEM_OFFSET,
 866         ISP_PRO_RAW_AEM_BLK_SIZE,
 867         ISP_PRO_RAW_AEM_SLICE_SIZE,
 868 };
 869
 870 enum isp_ct_property {
 871         ISP_PRO_CT_BLOCK,
 872 };
 873
 874 enum isp_csc_property {
 875         ISP_PRO_CSC_BLOCK,
 876         ISP_PRO_CSC_PIC_SIZE,
 877 };
 878
 879 enum isp_posterize_property {
 880         ISP_PRO_POSTERIZE_BLOCK,
 881 };
 882
 883 enum isp_yuv_precdn_property {
 884         ISP_PRO_YUV_PRECDN_BLOCK,
 885 };
 886
 887 enum isp_cdn_property {
 888         ISP_PRO_YUV_CDN_BLOCK,
 889 #if 0
 890         ISP_PRO_CDN_STATUS0,
 891         ISP_PRO_CDN_STATUS1,
 892         ISP_PRO_CDN_BYPASS,
 893         ISP_PRO_CDN_FILTER_BYPASS,
 894         ISP_PRO_CDN_MEDIAN_WRITEBACK_EN,
 895         ISP_PRO_CDN_MEDIAN_MODE,
 896         ISP_PRO_CDN_GAUSSIAN_MODE,
 897         ISP_PRO_CDN_MEDIAN_THR,
 898         ISP_PRO_CDN_MEDIAN_THRUV,
 899         ISP_PRO_CDN_RANWEI,
 900 #endif
 901 };
 902
 903 enum isp_rgbg2_property {
 904         ISP_PRO_RGB_GAIN2_BLOCK,
 905 };
 906
 907 struct isp_addr {
 908         uint32_t chn0;
 909         uint32_t chn1;
 910         uint32_t chn2;
 911 };
 912
 913 struct isp_pitch{
 914         uint32_t chn0;
 915         uint32_t chn1;
 916         uint32_t chn2;
 917 };
 918
 919 struct isp_blc_rb {
 920         uint32_t r;
 921         uint32_t b;
 922         uint32_t gr;
 923         uint32_t gb;
 924 };
 925
 926 struct isp_aem_statistics {
 927         uint32_t val[ISP_AEM_ITEM];
 928 };
 929
 930 struct isp_raw_aem_statistics {
 931         uint32_t r[ISP_RAW_AEM_ITEM];
 932         uint32_t g[ISP_RAW_AEM_ITEM];
 933         uint32_t b[ISP_RAW_AEM_ITEM];
 934 };
 935
 936 struct isp_awbm_statistics {
 937         uint32_t r[ISP_AWBM_ITEM];
 938         uint32_t g[ISP_AWBM_ITEM];
 939         uint32_t b[ISP_AWBM_ITEM];
 940 };
 941
 942 struct isp_raw_awbm_statistics {
 943         uint32_t num0;
 944         uint32_t num1;
 945         uint32_t num2;
 946         uint32_t num3;
 947         uint32_t num4;
 948         uint32_t num_t;
 949         uint32_t block_r;
 950         uint32_t block_g;
 951         uint32_t block_b;
 952 };
 953
 954 struct isp_awbc_rgb {
 955         uint32_t r;
 956         uint32_t g;
 957         uint32_t b;
 958 };
 959
 960 struct isp_bpc_common {
 961         uint32_t pattern_type;
 962         uint32_t detect_thrd;
 963         uint32_t super_bad_thrd;
 964 };
 965
 966 struct isp_bpc_thrd {
 967         uint32_t flat;
 968         uint32_t std;
 969         uint32_t texture;
 970 };
 971
 972 struct isp_grgb_thrd {
 973         uint32_t edge;
 974         uint32_t diff;
 975 };
 976
 977 struct isp_cfa_thrd {
 978         uint32_t edge;
 979         uint32_t ctrl;
 980 };
 981
 982 struct isp_cmc_matrix_tab {
 983         uint16_t val[ISP_CMC_MATRIX_TAB_MAX];
 984         uint16_t reserved;
 985 };
 986
 987 struct isp_gamma_node {
 988         uint32_t val[ISP_GAMMA_NODE_MAX];
 989 };
 990
 991 struct isp_cce_matrix_tab {
 992         uint16_t matrix[ISP_CCE_MATRIX_TAB_MAX];
 993         uint16_t reserved;
 994 };
 995
 996 struct isp_cce_shift {
 997         uint32_t y_shift;
 998         uint32_t u_shift;
 999         uint32_t v_shift;
1000 };
1001
1002 struct isp_cce_uvd {
1003         uint8_t uvd[ISP_CCE_UVD_NUM];
1004         uint8_t reserved;
1005 };
1006
1007 struct isp_cce_uvc {
1008         uint8_t uvc0[ISP_CCE_UVC0_NUM];
1009         uint8_t reserved0;
1010         uint8_t reserved1;
1011         uint8_t uvc1[ISP_CCE_UVC1_NUM];
1012         uint8_t reserved2;
1013 };
1014
1015 struct isp_prefilter_thrd {
1016         uint32_t y_thrd;
1017         uint32_t u_thrd;
1018         uint32_t v_thrd;
1019 };
1020
1021 struct isp_hist_ratio {
1022         uint32_t low_ratio;
1023         uint32_t high_ratio;
1024 };
1025
1026 struct isp_hist_maxmin {
1027         uint32_t in_min;
1028         uint32_t in_max;
1029         uint32_t out_min;
1030         uint32_t out_max;
1031 };
1032
1033 struct isp_aca_maxmin {
1034         uint32_t in_min;
1035         uint32_t in_max;
1036         uint32_t out_min;
1037         uint32_t out_max;
1038 };
1039
1040 struct isp_aca_adjust {
1041         uint32_t diff;
1042         uint32_t small;
1043         uint32_t big;
1044 };
1045
1046 struct isp_img_coord {
1047         uint32_t start_x;
1048         uint32_t start_y;
1049         uint32_t end_x;
1050         uint32_t end_y;
1051 };
1052
1053 struct isp_afm_statistic {
1054         uint32_t val;
1055 };
1056
1057 struct isp_edge_thrd {
1058         uint32_t detail;
1059         uint32_t smooth;
1060         uint32_t strength;
1061 };
1062
1063 struct isp_css_thrd {
1064         uint8_t lower_thrd[ISP_CSS_LOWER_NUM];
1065         uint8_t luma_thrd;
1066         uint8_t lower_sum_thrd[ISP_CSS_LOWER_SUM_NUM];
1067         uint8_t chroma_thrd;
1068 };
1069
1070 struct isp_css_ratio {
1071         uint8_t ratio[ISP_CSS_RATIO_NUM];
1072 };
1073
1074 struct isp_coord {
1075         uint32_t start_x;
1076         uint32_t start_y;
1077         uint32_t end_x;
1078         uint32_t end_y;
1079 };
1080
1081 struct isp_scaling_ratio {
1082         uint8_t vertical;
1083         uint8_t horizontal;
1084 };
1085
1086 struct isp_b4awb_phys {
1087         uint32_t phys0;
1088         uint32_t phys1;
1089 };
1090
1091 struct isp_hdr_rgb_index {
1092         uint32_t r;
1093         uint32_t g;
1094         uint32_t b;
1095 };
1096
1097 struct isp_hdr_tab {
1098         uint8_t com[ISP_HDR_COMP_ITEM * 4];
1099         uint8_t p2e[ISP_HDR_P2E_ITEM * 4];
1100         uint8_t e2p[ISP_HDR_E2P_ITEM * 4];
1101 };
1102
1103 struct isp_nlc_r_node {
1104         uint16_t r_node[ISP_NLC_R_NODE_NUM];
1105         uint16_t reserved;
1106 };
1107
1108 struct isp_nlc_g_node {
1109         uint16_t g_node[ISP_NLC_G_NODE_NUM];
1110         uint16_t reserved;
1111 };
1112
1113 struct isp_nlc_b_node {
1114         uint16_t b_node[ISP_NLC_B_NODE_NUM];
1115         uint16_t reserved;
1116 };
1117
1118 struct isp_nlc_l_node {
1119         uint16_t l_node[ISP_NLC_L_NODE_NUM];
1120         uint16_t reserved;
1121 };
1122
1123 struct isp_bayer_mode {
1124         uint32_t nlc_bayer;
1125         uint32_t awbc_bayer;
1126         uint32_t wave_bayer;
1127         uint32_t cfa_bayer;
1128         uint32_t gain_bayer;
1129 };
1130
1131 struct isp_fetch_endian {
1132         uint32_t endian;
1133         uint32_t bit_recorder;
1134 };
1135
1136 struct isp_rgb_gain {
1137         uint32_t r_gain;
1138         uint32_t g_gain;
1139         uint32_t b_gain;
1140 };
1141
1142 struct isp_rgb_gain_offset {
1143         uint32_t r_offset;
1144         uint32_t g_offset;
1145         uint32_t b_offset;
1146 };
1147
1148 struct isp_ygamma_xnode {
1149         uint8_t x_node[ISP_YIQ_YGAMMA_XNODE_NUM];
1150 };
1151
1152 struct isp_ygamma_ynode {
1153         uint8_t y_node[ISP_YIQ_YGAMMA_YNODE_NUM];
1154         uint8_t reserved0;
1155         uint8_t reserved1;
1156 };
1157
1158 struct isp_ygamma_node_index {
1159         uint8_t node_index[ISP_YIQ_YGAMMA_NODE_INDEX_NUM];
1160         uint8_t reserved0;
1161         uint8_t reserved1;
1162         uint8_t reserved2;
1163 };
1164
1165 struct isp_dev_fetch_info {
1166         uint32_t bypass;
1167         uint32_t substract;
1168         struct isp_addr addr;
1169         struct isp_pitch pitch;
1170         uint32_t mipi_word_num;
1171         uint32_t mipi_byte_rel_pos;
1172 };
1173
1174 struct isp_dev_blc_info {
1175         uint32_t bypass;
1176         uint32_t mode;
1177         uint32_t r;
1178         uint32_t b;
1179         uint32_t gr;
1180         uint32_t gb;
1181 };
1182
1183 struct isp_dev_lsc_info {
1184         uint32_t bypass;
1185         uint32_t grid_pitch;
1186         uint32_t grid_mode;
1187         uint32_t endian;
1188         uint32_t buf_addr[2]; //compatible with 64bit cpu
1189         uint32_t buf_len;
1190 };
1191
1192 struct isp_dev_awb_info {
1193         /*AWBM*/
1194         uint32_t awbm_bypass;
1195         uint32_t mode;
1196         uint32_t skip_num;
1197         uint32_t offset_x;
1198         uint32_t offset_y;
1199         uint32_t win_w;
1200         uint32_t win_h;
1201         uint32_t shift;
1202         /*AWBC*/
1203         uint32_t awbc_bypass;
1204         uint32_t r_gain;
1205         uint32_t g_gain;
1206         uint32_t b_gain;
1207         uint32_t r_thrd;
1208         uint32_t g_thrd;
1209         uint32_t b_thrd;
1210         uint32_t r_offset;
1211         uint32_t g_offset;
1212         uint32_t b_offset;
1213 };
1214
1215 struct isp_dev_bpc_info {
1216         uint32_t bypass;
1217         uint32_t mode;
1218         uint32_t flat_thrd;
1219         uint32_t std_thrd;
1220         uint32_t texture_thrd;
1221         uint32_t map_addr;
1222 };
1223
1224 struct isp_dev_wavelet_denoise_info {
1225         uint32_t bypass;
1226         uint32_t diswei_level;
1227         uint32_t ranwei_level;
1228 };
1229
1230 struct isp_dev_grgb_info {
1231         uint32_t bypass;
1232         uint32_t edge_thrd;
1233         uint32_t diff_thrd;
1234 };
1235
1236 struct isp_dev_cfa_info {
1237         uint32_t edge_thrd;
1238         uint32_t ctrl_thrd;
1239 };
1240
1241 struct isp_dev_cmc_info {
1242         uint32_t bypass;
1243         uint16_t matrix[ISP_CMC_MATRIX_TAB_MAX];
1244         uint16_t reserved;
1245 };
1246
1247 struct isp_dev_gamma_info {
1248         uint32_t bypass;
1249         uint32_t node[ISP_GAMMA_NODE_MAX];
1250 };
1251
1252 struct isp_dev_cce_matrix_info {
1253         uint32_t mode;
1254         uint16_t matrix[ISP_CCE_MATRIX_TAB_MAX];
1255         uint16_t reserved;
1256         uint32_t y_shift;
1257         uint32_t u_shift;
1258         uint32_t v_shift;
1259 };
1260
1261 struct isp_dev_cce_uv_info {
1262         uint32_t bypass;
1263         uint32_t mode;
1264         uint8_t uvd[ISP_CCE_UVD_NUM];
1265         uint8_t reserved0;
1266         uint8_t uvc0[ISP_CCE_UVC0_NUM];
1267         uint8_t reserved1;
1268         uint8_t reserved2;
1269         uint8_t uvc1[ISP_CCE_UVC1_NUM];
1270         uint8_t reserved3;
1271 };
1272
1273 struct isp_dev_prefilter_info {
1274         uint32_t bypass;
1275         uint32_t writeback;
1276         uint32_t y_thrd;
1277         uint32_t u_thrd;
1278         uint32_t v_thrd;
1279 };
1280
1281 struct isp_dev_hist_info {
1282         uint32_t bypass;
1283         uint32_t auto_rst_disable;
1284         uint32_t mode;
1285         uint32_t low_sum_ratio;
1286         uint32_t high_sum_ratio;
1287         uint32_t in_min;
1288         uint32_t in_max;
1289         uint32_t out_min;
1290         uint32_t out_max;
1291         uint32_t clr_eb;
1292 };
1293
1294 struct isp_dev_aca_info {
1295         uint32_t bypass;
1296         uint32_t mode;
1297         uint32_t in_min;
1298         uint32_t in_max;
1299         uint32_t out_min;
1300         uint32_t out_max;
1301         uint32_t diff_thrd;
1302         uint32_t small_thrd;
1303         uint32_t big_thrd;
1304 };
1305
1306 struct isp_dev_afm_info {
1307         uint32_t bypass;
1308         uint32_t shift;
1309         uint32_t mode;
1310         uint32_t skip_num;
1311         uint32_t skip_num_clr;
1312         struct isp_img_coord win[ISP_AFM_WIN_NUM];
1313 };
1314
1315 struct isp_dev_edge_info {
1316         uint32_t bypass;
1317         uint32_t detail_thrd;
1318         uint32_t smooth_thrd;
1319         uint32_t strength;
1320 };
1321
1322 struct isp_dev_emboss_info {
1323         uint32_t bypass;
1324         uint32_t step;
1325 };
1326
1327 struct isp_dev_fcs_info {
1328         uint32_t bypass;
1329         uint32_t mode;
1330 };
1331
1332 struct isp_dev_css_info {
1333         uint32_t bypass;
1334         uint8_t lower_thrd[ISP_CSS_LOWER_NUM];
1335         uint8_t luma_thrd;
1336         uint8_t lower_sum_thrd[ISP_CSS_LOWER_SUM_NUM];
1337         uint8_t chroma_thrd;
1338         uint8_t ratio[ISP_CSS_RATIO_NUM];
1339 };
1340
1341 struct isp_dev_csa_info {
1342         uint32_t bypass;
1343         uint32_t factor;
1344 };
1345
1346 struct isp_dev_store_info {
1347         uint32_t bypass;
1348         uint32_t substract;
1349         struct isp_addr addr;
1350         struct isp_pitch pitch;
1351 };
1352
1353 struct isp_dev_feeder_info {
1354         uint32_t data_type;
1355 };
1356
1357 struct isp_dev_hdr_info {
1358         uint32_t bypass;
1359         uint32_t level;
1360         uint32_t r_index;
1361         uint32_t g_index;
1362         uint32_t b_index;
1363         uint8_t com[ISP_HDR_COMP_ITEM * 4];
1364         uint8_t p2e[ISP_HDR_P2E_ITEM * 4];
1365         uint8_t e2p[ISP_HDR_E2P_ITEM * 4];
1366 };
1367
1368 struct isp_dev_nlc_info {
1369         uint32_t bypass;
1370         uint16_t r_node[ISP_NLC_R_NODE_NUM];
1371         uint16_t reserved0;
1372         uint16_t g_node[ISP_NLC_G_NODE_NUM];
1373         uint16_t reserved1;
1374         uint16_t b_node[ISP_NLC_B_NODE_NUM];
1375         uint16_t reserved2;
1376         uint16_t l_node[ISP_NLC_L_NODE_NUM];
1377         uint16_t reserved3;
1378 };
1379
1380 struct isp_dev_nawbm_info {
1381         uint32_t bypass;
1382 };
1383
1384 struct isp_dev_pre_wavelet_info {
1385         uint32_t bypass;
1386 };
1387
1388 struct isp_dev_binning4awb_info {
1389         uint32_t bypass;
1390 };
1391
1392 struct isp_dev_glb_gain_info {
1393         uint32_t bypass;
1394         uint32_t gain;
1395 };
1396
1397 struct isp_dev_rgb_gain_info {
1398         uint32_t bypass;
1399         uint32_t r_gain;
1400         uint32_t g_gain;
1401         uint32_t b_gain;
1402         uint32_t r_offset;
1403         uint32_t g_offset;
1404         uint32_t b_offset;
1405 };
1406
1407 struct isp_dev_yiq_ygamma_info {
1408         uint32_t bypass;
1409         uint8_t x_node[ISP_YIQ_YGAMMA_XNODE_NUM];
1410         uint8_t y_node[ISP_YIQ_YGAMMA_YNODE_NUM];
1411         uint8_t reserved0;
1412         uint8_t reserved1;
1413         uint8_t node_index[ISP_YIQ_YGAMMA_NODE_INDEX_NUM];
1414         uint8_t reserved2;
1415         uint8_t reserved3;
1416         uint8_t reserved4;
1417 };
1418
1419 struct isp_dev_yiq_ae_info {
1420         uint32_t bypass;
1421         uint32_t src_sel;
1422         uint32_t mode;
1423         uint32_t skip_num;
1424 };
1425
1426 struct isp_dev_yiq_flicker_info {
1427         uint32_t bypass;
1428         uint32_t mode;
1429         uint32_t v_height;
1430         uint32_t line_counter;
1431         uint32_t line_step;
1432         uint32_t line_start;
1433 };
1434
1435 struct isp_dev_hue_info {
1436         uint32_t bypass;
1437         uint32_t theta;
1438 };
1439
1440 struct isp_dev_nbpc_info {
1441         uint32_t bypass;
1442 };
1443
1444
1445 /*********************Tshark2**********************/
1446 #define ISP_PINGPANG_CTM_NUM 729
1447 #define ISP_CTM_PARAM_NUM   (729 * 4)
1448 #define ISP_PINGPANG_HSV_NUM 361
1449 #define ISP_HSV_PARAM_NUM (361 * 2)
1450 #define ISP_PINGPANG_FRGB_GAMC_NUM 129
1451 #define ISP_PINGPANG_YUV_YGAMMA_NUM 129
1452 #define ISP_VST_IVST_NUM 1024
1453 #define ISP_AFM_WIN_NUM_V1 25
1454
1455 enum isp_dev_capability {
1456         ISP_CAPABILITY_CHIP_ID,
1457         ISP_CAPABILITY_SINGLE_SIZE,
1458         ISP_CAPABILITY_CONTINE_SIZE,
1459         ISP_CAPABILITY_AWB_WIN,
1460         ISP_CAPABILITY_AWB_DEFAULT_GAIN,
1461         ISP_CAPABILITY_AF_MAX_WIN_NUM,
1462 };
1463
1464 enum isp_int_property {
1465         ISP_PRO_INT_STATUS,
1466         ISP_PRO_INT_EN0,
1467         ISP_PRO_INT_CLR0,
1468         ISP_PRO_INT_RAW0,
1469         ISP_PRO_INT_INT0,
1470         ISP_PRO_INT_EN1,
1471         ISP_PRO_INT_CLR1,
1472         ISP_PRO_INT_RAW1,
1473         ISP_PRO_INT_INT1,
1474         ISP_PRO_INT_EN2,
1475         ISP_PRO_INT_CLR2,
1476         ISP_PRO_INT_RAW2,
1477         ISP_PRO_INT_INT2,
1478         ISP_PRO_INT_EN3,
1479         ISP_PRO_INT_CLR3,
1480         ISP_PRO_INT_RAW3,
1481         ISP_PRO_INT_INT3,
1482         ISP_PRO_INT_ALL_DONE_CTRL,
1483 };
1484
1485 enum isp_dispatch_property {
1486         ISP_PRO_DISPATCH_BLOCK,
1487         ISP_PRO_DISPATCH_CH0_BAYER,
1488         ISP_PRO_DISPATCH_CH1_BAYER,
1489         ISP_PRO_DISPATCH_CH0_SIZE,
1490         ISP_PRO_DISPATCH_CH1_SIZE,
1491 };
1492
1493 enum isp_arbiter_property {
1494         ISP_PRO_ARBITER_BLOCK,
1495         ISP_PRO_ARBITER_WR_STATUS,
1496         ISP_PRO_ARBITER_RD_STATUS,
1497         ISP_PRO_ARBITER_PARAM,
1498         ISP_PRO_ARBITER_ENDIAN_CH0,
1499         ISP_PRO_ARBITER_ENDIAN_CH1,
1500         ISP_PRO_ARBITER_CTRL,
1501 };
1502
1503 enum isp_axi_property {
1504         ISP_PRO_AXI_BLOCK,
1505         ISP_PRO_AXI_WR_MASTER_STATUS,
1506         ISP_PRO_AXI_RD_MASTER_STATUS,
1507         ISP_PRO_AXI_ITI2AXIM_CTRL,
1508         ISP_PRO_AXI_CONVERT_WR_CTRL,
1509 };
1510
1511 enum isp_raw_sizer_property {
1512         ISP_PRO_RAW_SIZER_BLOCK,
1513         ISP_PRO_RAW_SIZER_BYPASS,
1514         ISP_PRO_RAW_SIZER_BPC_BYPASS,
1515         ISP_PRO_RAW_SIZER_CROP_BYPASS,
1516         ISP_PRO_RAW_SIZER_CROP_SRC,
1517         ISP_PRO_RAW_SIZER_CROP_DST,
1518         ISP_PRO_RAW_SIZER_CROP_START,
1519         ISP_PRO_RAW_SIZER_DST,
1520         ISP_PRO_RAW_SIZER_BPC_SHIFT,
1521         ISP_PRO_RAW_SIZER_BPC_MULTI,
1522         ISP_PRO_RAW_SIZER_BPC_MIN_DIFF,
1523         ISP_PRO_RAW_SIZER_HCOEFF,
1524         ISP_PRO_RAW_SIZER_VCOEFF,
1525         ISP_PRO_RAW_SIZER_H_INIT_PARA,
1526         ISP_PRO_RAW_SIZER_V_INIT_PARA,
1527 };
1528
1529 enum isp_common_property_v1 {
1530         ISP_PRO_COMMON_BLOCK,
1531         ISP_PRO_COMMON_VERSION,
1532         ISP_PRO_COMMON_STATUS0,
1533         ISP_PRO_COMMON_STATUS1,
1534         ISP_PRO_COMMON_CH0_FETCH_SEL,
1535         ISP_PRO_COMMON_CH0_SIZER_SEL,
1536         ISP_PRO_COMMON_CH0_STORE_SEL,
1537         ISP_PRO_COMMON_CH1_FETCH_SEL,
1538         ISP_PRO_COMMON_CH1_SIZER_SEL,
1539         ISP_PRO_COMMON_CH1_STORE_SEL,
1540         ISP_PRO_COMMON_FETCH_COLOR_SPACE_SEL,
1541         ISP_PRO_COMMON_STORE_COLOR_SPACE_SEL,
1542         ISP_PRO_COMMON_AWBM_POS_SEL,
1543         ISP_PRO_COMMON_CH0_AEM2_POS,
1544         ISP_PRO_COMMON_CH0_Y_AFM_POS,
1545         ISP_PRO_COMMON_CH1_AEM2_POS,
1546         ISP_PRO_COMMON_CH1_Y_AFM_POS,
1547         ISP_PRO_COMMON_LBUF_OFFSET,
1548         ISP_PRO_COMMON_SHADOW_ALL_CTRL,
1549         ISP_PRO_COMMON_AWBM_SHADOW,
1550         ISP_PRO_COMMON_AE_SHADOW,
1551         ISP_PRO_COMMON_AF_SHADOW,
1552         ISP_PRO_COMMON_AFL_SHADOW,
1553         ISP_PRO_COMMON_COMM_SHADOW,
1554         ISP_PRO_COMMON_3A_SINGLE_FRAME_CTRL,
1555 };
1556
1557 enum isp_pwd_property {
1558         ISP_PRO_PWD_BLOCK,
1559         ISP_PRO_PWD_SLICE_SIZE,
1560 };
1561
1562 enum isp_awbm_property {
1563         ISP_PRO_AWBM_BLOCK,
1564 };
1565
1566 enum isp_awbc_property {
1567         ISP_PRO_AWBC_BLOCK,
1568 };
1569
1570 enum isp_grgb_property_v1 {
1571         ISP_PRO_GRGB_BLOCK_v1,
1572 };
1573
1574 enum isp_nlm_property {
1575         ISP_PRO_VST_BLOCK,
1576         ISP_PRO_NLM_BLOCK,
1577         ISP_PRO_IVST_BLOCK,
1578 };
1579
1580 enum isp_wdr_property {
1581         ISP_PRO_WDR_BLOCK,
1582 };
1583
1584 enum isp_cmc8_property {
1585         ISP_PRO_CMC8_BLOCK,
1586 };
1587
1588 enum isp_hsv_property {
1589         ISP_PRO_HSV_BLOCK,
1590 };
1591
1592 enum isp_pre_cdn_rgb_property {
1593         ISP_PRO_PRE_CDN_RGB_BLOCK,
1594 };
1595
1596 enum isp_rgb_afm_property {
1597         ISP_PRO_RGB_AFM_BLOCK,
1598         ISP_PRO_RGB_AFM_FRAME_SIZE,
1599         ISP_PRO_RGB_AFM_TYPE1_STATISTIC,
1600         ISP_PRO_RGB_AFM_TYPE2_STATISTIC,
1601         ISP_PRO_RGB_AFM_BYPASS,
1602         ISP_PRO_RGB_AFM_MODE,
1603         ISP_PRO_RGB_AFM_SKIP_NUM,
1604         ISP_PRO_RGB_AFM_SKIP_NUM_CLR,
1605         ISP_PRO_RGB_AFM_SPSMD_RTGBOT_ENABLE,
1606         ISP_PRO_RGB_AFM_SPSMD_DIAGONAL_ENABLE,
1607         ISP_PRO_RGB_AFM_SPSMD_CAL_MOD,
1608         ISP_PRO_RGB_AFM_SEL_FILTER1,
1609         ISP_PRO_RGB_AFM_SEL_FILTER2,
1610         ISP_PRO_RGB_AFM_SOBEL_TYPE,
1611         ISP_PRO_RGB_AFM_SPSMD_TYPE,
1612         ISP_PRO_RGB_AFM_SOBEL_THRESHOLD,
1613         ISP_PRO_RGB_AFM_SPSMD_THRESHOLD,
1614         ISP_PRO_RGB_AFM_FRAME_RANGE,
1615         ISP_PRO_RGB_AFM_WIN,
1616         ISP_PRO_RGB_AFM_WIN_NUM,
1617 };
1618
1619 enum isp_rgb2y_property {
1620         ISP_PRO_RGB2Y_BLOCK,
1621 };
1622
1623 enum isp_yiq_aem_property {
1624         ISP_PRO_YIQ_AEM_BLOCK,
1625         ISP_PRO_YIQ_AEM_SLICE_SIZE,
1626 };
1627
1628 enum isp_anti_flicker_property {
1629         ISP_PRO_ANTI_FLICKER_BLOCK,
1630         ISP_PRO_ANTI_FLICKER_STATISTIC,
1631         ISP_PRO_ANTI_FLICKER_BYPASS,
1632 };
1633
1634 enum isp_yiq_afm_property {
1635         ISP_PRO_YIQ_AFM_BLOCK,
1636         ISP_PRO_YIQ_AFM_SLICE_SIZE,
1637         ISP_PRO_YIQ_AFM_WIN,
1638         ISP_PRO_YIQ_AFM_WIN_NUM,
1639         ISP_PRO_YIQ_AFM_STATISTIC,
1640 };
1641
1642 enum isp_prefilter_property_v1 {
1643         ISP_PRO_PREF_BLOCK_V1,
1644 };
1645
1646 enum isp_uv_prefilter_property {
1647         ISP_PRO_UV_PREFILTER_BLOCK,
1648 };
1649
1650 enum isp_hist2_property {
1651         ISP_PRO_HIST2_BLOCK,
1652 };
1653
1654 enum isp_iircnr_property {
1655         ISP_PRO_IIRCNR_BLOCK,
1656         ISP_PRO_YRANDOM_BLOCK,
1657 };
1658
1659 enum isp_post_cdn_property {
1660         ISP_PRO_POST_CDN_BLOCK,
1661 };
1662
1663 enum isp_ygamma_property {
1664         ISP_PRO_YGAMMA_BLOCK,
1665 };
1666
1667 enum isp_ydelay_property {
1668         ISP_PRO_YDELAY_BLOCK,
1669 };
1670
1671 enum isp_yuv_nlm_property {
1672         ISP_PRO_YUV_NLM_BLOCK,
1673         ISP_PRO_YUV_NLM_SLICE_SIZE,
1674 };
1675
1676 enum isp_pingpang_property {
1677         ISP_PRO_PINGPANG_CTM_BLOCK,
1678         ISP_PRO_PINGPANG_HSV_BLOCK,
1679         ISP_PRO_PINGPANG_FRGB_GAMC_BLOCK,
1680 };
1681
1682 struct isp_memory {
1683         unsigned long addr;
1684         uint32_t len;
1685 };
1686
1687 struct isp_reg_bits {
1688         unsigned long reg_addr;
1689         unsigned long reg_value;
1690 };
1691
1692 struct isp_reg_param {
1693         unsigned long reg_param;
1694         uint32_t counts;
1695 };
1696
1697 struct isp_irq {
1698         uint32_t irq_val0;
1699         uint32_t irq_val1;
1700         uint32_t irq_val2;
1701         uint32_t irq_val3;
1702         uint32_t reserved;
1703         int32_t ret_val;
1704 };
1705
1706 struct isp_interrupt {
1707         uint32_t isp_id;
1708         uint32_t int_mode;
1709 };
1710
1711 struct isp_capability {
1712         uint32_t isp_id;
1713         uint32_t index;
1714         void * property_param;
1715 };
1716
1717 struct isp_io_param {
1718         uint32_t isp_id;
1719         uint32_t sub_block;
1720         uint32_t property;
1721         void * property_param;
1722 };
1723
1724 struct isp_img_offset {
1725         uint32_t x;
1726         uint32_t y;
1727 };
1728
1729 struct isp_img_size {
1730         uint32_t width;
1731         uint32_t height;
1732 };
1733
1734 struct img_offset {
1735         uint32_t x;
1736         uint32_t y;
1737 };
1738
1739 struct isp_lsc_addr {
1740         uint32_t phys_addr;
1741         uint32_t virt_addr;
1742         uint32_t buf_len;
1743 };
1744
1745 //*nlc*//
1746 struct nlc_node {
1747         uint16_t r_node[29];
1748         uint16_t reserved0;
1749         uint16_t g_node[29];
1750         uint16_t reserved1;
1751         uint16_t b_node[29];
1752         uint16_t reserved2;
1753         uint16_t l_node[27];
1754         uint16_t reserved3;
1755 };
1756
1757 //*awbm*//
1758 struct awbm_rect_pos {
1759         uint32_t start_x[5];
1760         uint32_t start_y[5];
1761         uint32_t end_x[5];
1762         uint32_t end_y[5];
1763 };
1764
1765 struct awbm_circle_pos {
1766         uint32_t x[5];
1767         uint32_t y[5];
1768         uint32_t r[5];
1769 };
1770
1771 struct awbm_pixel_num {
1772         uint32_t pixel_num[5];
1773 };
1774
1775 struct awbm_thr {
1776         uint32_t r_high;
1777         uint32_t r_low;
1778         uint32_t g_high;
1779         uint32_t g_low;
1780         uint32_t b_high;
1781         uint32_t b_low;
1782 };
1783
1784 //**awbc//
1785 struct awbc_param {
1786         uint32_t r;
1787         uint32_t b;
1788         uint32_t gr;
1789         uint32_t gb;
1790 };
1791
1792 struct awbc_rgb {
1793         uint32_t r;
1794         uint32_t g;
1795         uint32_t b;
1796 };
1797
1798 struct sobel_thrd {
1799     uint32_t min;
1800     uint32_t max;
1801 };
1802
1803 struct spsmd_thrd {
1804     uint32_t min;
1805     uint32_t max;
1806 };
1807
1808 struct cce_shift {
1809         uint32_t y_shift;
1810         uint32_t u_shift;
1811         uint32_t v_shift;
1812 };
1813
1814 struct gamma_node {
1815         uint32_t val[66];
1816 };
1817
1818 //*cmc8 and cmc10*//
1819 struct cmc_matrix {
1820         uint16_t val[9];
1821         uint16_t reserved;
1822 };
1823
1824 struct coordinate_xy {
1825          int16_t node_x;
1826          int16_t node_y;
1827 };
1828
1829 struct csa_factor_v1 {
1830         uint32_t factor_u;
1831         uint32_t factor_v;
1832 };
1833
1834 struct isp_raw_afm_statistic {
1835         uint32_t val[ISP_RAW_AFM_ITEM];
1836 };
1837
1838 struct isp_yiq_afm_statistic {
1839         uint32_t val[ISP_YIQ_AFM_ITEM];
1840 };
1841
1842 struct arbiter_endian_v1 {
1843         uint32_t bpc_endian;
1844         uint32_t lens_endian;
1845         uint32_t store_endian;
1846         uint32_t fetch_bit_reorder;
1847         uint32_t fetch_endian;
1848 };
1849
1850 struct arbiter_param_v1 {
1851         uint32_t pause_cycle;
1852         uint32_t reset;
1853 };
1854
1855
1856 struct isp_dev_pre_glb_gain_info {
1857         uint32_t bypass;
1858         uint32_t gain;
1859 };
1860
1861 struct isp_dev_rgb_gain_info_v1 {
1862         uint32_t bypass;
1863         uint32_t global_gain;
1864         uint32_t r_gain;
1865         uint32_t g_gain;
1866         uint32_t b_gain;
1867 };
1868
1869 struct isp_dev_pre_wavelet_info_v1 {
1870         uint32_t bypass;
1871         uint32_t radial_bypass;
1872         uint32_t gain_thrs0;
1873         uint32_t gain_thrs1;
1874         uint32_t bitshift0;
1875         uint32_t bitshift1;
1876         uint32_t offset;
1877         uint32_t nsr_slope;
1878         uint32_t lum_ratio;
1879         uint32_t center_pos_x;
1880         uint32_t center_pos_y;
1881         uint32_t delta_x2;
1882         uint32_t delta_y2;
1883         uint32_t r2_thr;
1884         uint32_t p_param1;
1885         uint32_t p_param2;
1886         uint32_t addback;
1887         uint32_t gain_max_thr;
1888         uint32_t pos_x;
1889         uint32_t pos_y;
1890         uint32_t lum_shink_level;
1891 };
1892
1893 struct isp_dev_nlc_info_v1 {
1894         uint32_t bypass;
1895         struct nlc_node node;
1896 };
1897
1898 struct isp_dev_2d_lsc_info {
1899         uint32_t bypass;
1900         uint32_t buf_sel;
1901         uint32_t grid_address;
1902         uint32_t offset_x;
1903         uint32_t offset_y;
1904         uint32_t loader_enable;
1905         uint32_t grid_pitch;
1906         uint32_t grid_width;
1907         uint32_t grid_x_num;
1908         uint32_t grid_y_num;
1909         uint32_t grid_num_t;
1910         uint32_t load_buf_sel;
1911         uint32_t load_chn_sel;
1912         uint32_t endian;
1913         struct isp_img_size slice_size;
1914         uint32_t relative_x;
1915         uint32_t relative_y;
1916         uint32_t q_value[2][5];
1917         uint32_t buf_addr[2]; //compatible with 64bit cpu
1918         uint32_t buf_len;
1919 };
1920
1921 struct isp_dev_1d_lsc_info {
1922         uint32_t bypass;
1923         uint32_t gain_max_thr;
1924         uint32_t center_r0c0_row_y;
1925         uint32_t center_r0c0_col_x;
1926         uint32_t center_r0c1_row_y;
1927         uint32_t center_r0c1_col_x;
1928         uint32_t center_r1c0_row_y;
1929         uint32_t center_r1c0_col_x;
1930         uint32_t center_r1c1_row_y;
1931         uint32_t center_r1c1_col_x;
1932         uint32_t delta_square_r0c0_x;
1933         uint32_t delta_square_r0c0_y;
1934         uint32_t delta_square_r0c1_x;
1935         uint32_t delta_square_r0c1_y;
1936         uint32_t delta_square_r1c0_x;
1937         uint32_t delta_square_r1c0_y;
1938         uint32_t delta_square_r1c1_x;
1939         uint32_t delta_square_r1c1_y;
1940         uint32_t coef_r0c0_p1;
1941         uint32_t coef_r0c0_p2;
1942         uint32_t coef_r0c1_p1;
1943         uint32_t coef_r0c1_p2;
1944         uint32_t coef_r1c0_p1;
1945         uint32_t coef_r1c0_p2;
1946         uint32_t coef_r1c1_p1;
1947         uint32_t coef_r1c1_p2;
1948         struct img_offset start_pos;
1949 };
1950
1951 struct isp_dev_binning4awb_info_v1 {
1952         uint32_t bypass;
1953         uint32_t endian;
1954         uint32_t burst_mode;
1955         uint32_t vx;
1956         uint32_t mem_fifo_clr;
1957         uint32_t hx;
1958         uint32_t mem_addr;
1959         uint32_t pitch;
1960 };
1961
1962 struct isp_dev_awbm_info_v1 {
1963         uint32_t bypass;
1964         uint32_t mode;
1965         uint32_t skip_num;
1966         struct img_offset block_offset;
1967         struct isp_img_size block_size;
1968         uint32_t shift;
1969         uint32_t thr_bypass;
1970         struct awbm_rect_pos rect_pos;
1971         struct awbm_circle_pos circle_pos;
1972         struct awbm_rect_pos clctor_pos;
1973         struct awbm_pixel_num pix_num;
1974         struct awbm_thr thr;
1975         struct isp_img_size slice_size;
1976         uint32_t skip_num_clear;
1977         uint32_t mem_addr;
1978 };
1979
1980 struct isp_dev_awbc_info_v1 {
1981         uint32_t bypass;
1982         uint32_t alpha_bypass;
1983         uint32_t alpha_value;
1984         uint32_t buf_sel;
1985         struct awbc_param gain;
1986         struct awbc_rgb thrd;
1987         struct awbc_param gain_offset;
1988         struct awbc_param gain_buff;
1989         struct awbc_param gain_offset_buff;
1990 };
1991
1992 struct isp_dev_awb_info_v1 {
1993         /*AWBM*/
1994         uint32_t awbm_bypass;
1995         uint32_t mode;
1996         uint32_t skip_num;
1997         struct img_offset block_offset;
1998         struct isp_img_size block_size;
1999         uint32_t shift;
2000         uint32_t thr_bypass;
2001         struct awbm_rect_pos rect_pos;
2002         struct awbm_circle_pos circle_pos;
2003         struct awbm_rect_pos clctor_pos;
2004         struct awbm_pixel_num pix_num;
2005         struct awbm_thr thr;
2006         struct isp_img_size slice_size;
2007         uint32_t skip_num_clear;
2008         uint32_t mem_addr;
2009         /*AWBC*/
2010         uint32_t awbc_bypass;
2011         uint32_t alpha_bypass;
2012         uint32_t alpha_value;
2013         uint32_t buf_sel;
2014         struct awbc_param gain;
2015         struct awbc_rgb thrd;
2016         struct awbc_param gain_offset;
2017         struct awbc_param gain_buff;
2018         struct awbc_param gain_offset_buff;
2019 };
2020
2021 struct isp_dev_awb_info_v2 {
2022         /*AWBM*/
2023         uint32_t awbm_bypass;
2024         uint32_t mode;
2025         uint32_t skip_num;
2026         struct img_offset block_offset;
2027         struct isp_img_size block_size;
2028         uint32_t shift;
2029         uint32_t thr_bypass;
2030         struct awbm_rect_pos rect_pos;
2031         struct awbm_circle_pos circle_pos;
2032         struct awbm_rect_pos clctor_pos;
2033         struct awbm_pixel_num pix_num;
2034         struct awbm_thr thr;
2035         struct isp_img_size slice_size;
2036         uint32_t skip_num_clear;
2037         uint32_t position_sel;
2038         uint32_t mem_addr;
2039         /*AWBC*/
2040         uint32_t awbc_bypass;
2041         uint32_t alpha_bypass;
2042         uint32_t alpha_value;
2043         uint32_t buf_sel;
2044         struct awbc_param gain;
2045         struct awbc_rgb thrd;
2046         struct awbc_param gain_offset;
2047         struct awbc_param gain_buff;
2048         struct awbc_param gain_offset_buff;
2049 };
2050
2051
2052 struct isp_dev_raw_aem_info {
2053         uint32_t bypass;
2054         uint32_t shift;
2055         uint32_t mode;
2056 };
2057
2058 struct isp_dev_bpc_info_v1 {
2059         uint32_t bypass;
2060         uint32_t pvd_bypass;
2061         uint32_t bpc_mode;
2062         uint32_t mask_mode;
2063         uint32_t kmin;
2064         uint32_t kmax;
2065         uint32_t cntr_threshold;
2066         uint32_t bad_map_hw_fifo_clr_en;
2067         uint32_t ktimes;
2068         uint32_t bpc_map_fifo_clr;
2069         uint32_t delta;
2070         uint32_t bad_pixel_num;
2071         uint32_t flat_factor;
2072         uint32_t safe_factor;
2073         uint32_t spike_coeff;
2074         uint32_t dead_coeff;
2075         uint16_t intercept_b[8];
2076         uint16_t slope_k[8];
2077         uint16_t lut_level[8];
2078         uint32_t new_old_sel;
2079         uint32_t map_done_sel;
2080         uint32_t bpc_map_addr_new;
2081         uint32_t level;
2082 };
2083
2084 struct isp_dev_bdn_info_v1 {
2085         uint32_t bypass;
2086         uint32_t radial_bypass;
2087         uint32_t addback;
2088         uint32_t dis[10][2];
2089         uint32_t ran[10][8];
2090         uint32_t offset_x;
2091         uint32_t offset_y;
2092         uint32_t squ_x2;
2093         uint32_t squ_y2;
2094         uint32_t coef;
2095         uint32_t coef2;
2096         uint32_t start_pos_x;
2097         uint32_t start_pos_y;
2098         uint32_t offset;
2099         uint32_t dis_level;
2100         uint32_t ran_level;
2101 };
2102
2103 struct isp_dev_grgb_info_v1 {
2104         uint32_t bypass;
2105         uint32_t edge;
2106         uint32_t diff;
2107         uint32_t grid;
2108 };
2109
2110 struct isp_dev_rgb_gain2_info {
2111         uint32_t bypass;
2112         uint32_t r_gain;
2113         uint32_t g_gain;
2114         uint32_t b_gain;
2115         uint32_t r_offset;
2116         uint32_t g_offset;
2117         uint32_t b_offset;
2118 };
2119
2120 struct isp_dev_vst_info_v1 {
2121         uint32_t bypass;
2122         uint32_t buf_sel;
2123 };
2124
2125 struct isp_dev_nlm_info_v1 {
2126         uint32_t bypass;
2127         uint32_t imp_opt_bypass;
2128         uint32_t flat_opt_bypass;
2129         uint32_t flat_thr_bypass;
2130         uint32_t direction_mode_bypass;
2131         uint32_t buf_sel;
2132         uint8_t strength[5];
2133         uint8_t cnt[5];
2134         uint16_t thresh[5];
2135         uint32_t streng_th;
2136         uint32_t texture_dec;
2137         //uint32_t is_flat;
2138         uint32_t addback;
2139         uint32_t opt_mode;
2140         uint32_t dist_mode;
2141         uint8_t w_shift[3];
2142         uint8_t reserved;
2143         uint32_t cnt_th;
2144         uint32_t tdist_min_th;
2145         uint32_t diff_th;
2146         uint16_t lut_w[72];
2147         //void *vst_addr;
2148         uint32_t vst_addr[2]; //compatible with 64bit cpu
2149         uint32_t vst_len;
2150         //void *ivst_addr;
2151         uint32_t ivst_addr[2]; //compatible with 64bit cpu
2152         uint32_t ivst_len;
2153         //void *nlm_addr;
2154         uint32_t nlm_addr[2]; //compatible with 64bit cpu
2155         uint32_t nlm_len;
2156         uint32_t strength_level;
2157 };
2158
2159 struct isp_dev_nlm_info_v2 {
2160         uint32_t bypass;
2161         uint32_t imp_opt_bypass;
2162         uint32_t flat_opt_bypass;
2163 //      uint32_t flat_thr_bypass;
2164 //      uint32_t direction_mode_bypass;
2165         uint32_t buf_sel;
2166         uint8_t strength[5];
2167         uint8_t cnt[5];
2168         uint16_t thresh[5];
2169         uint32_t streng_th;
2170         uint32_t texture_dec;
2171         uint32_t is_flat;
2172         uint32_t addback;
2173 //      uint32_t opt_mode;
2174 //      uint32_t dist_mode;
2175 //      uint32_t w_shift[3];
2176 //      uint32_t cnt_th;
2177 //      uint32_t tdist_min_th;
2178 //      uint32_t diff_th;
2179         uint16_t lut_w[72];
2180         uint32_t vst_addr[2]; //compatible with 64bit cpu
2181         uint32_t vst_len;
2182         uint32_t ivst_addr[2]; //compatible with 64bit cpu
2183         uint32_t ivst_len;
2184         uint32_t nlm_addr[2]; //compatible with 64bit cpu
2185         uint32_t nlm_len;
2186         uint32_t strength_level;
2187
2188 };
2189
2190
2191 struct isp_dev_ivst_info_v1 {
2192         uint32_t bypass;
2193         uint32_t buf_sel;
2194 };
2195
2196 struct isp_dev_cfa_info_v1 {
2197         uint32_t  bypass;
2198         uint32_t  ee_bypass;
2199         uint32_t  doee_base;
2200         uint32_t  gbuf_addr_max;
2201         uint32_t  avg_mode;
2202         uint32_t  grid_gain;
2203         uint32_t  cfa_uni_dir_intplt_tr ;
2204         uint32_t  cfai_ee_uni_dir_tr;
2205         uint32_t  cfai_ee_edge_tr;
2206         uint32_t  cfai_ee_diagonal_tr;
2207         uint32_t  cfai_ee_grid_tr;
2208         uint32_t  cfai_doee_clip_tr;
2209         uint32_t  cfai_ee_saturation_level;
2210         uint32_t  plt_diff_tr;
2211         uint32_t  grid_min_tr ;
2212         uint32_t  strength_tr_neg;
2213         uint32_t  strength_tr_pos;
2214         uint32_t  ee_strength_neg;
2215         uint32_t  ee_strength_pos;
2216         uint32_t  inter_chl_gain;
2217 };
2218
2219 struct isp_dev_cmc10_info {
2220         uint32_t bypass;
2221         uint32_t buf_sel;
2222         uint32_t alpha;
2223         uint32_t alpha_bypass;
2224         struct cmc_matrix matrix;
2225         struct cmc_matrix matrix_buf;
2226 };
2227
2228 struct isp_dev_gamma_info_v1 {
2229         uint32_t bypass;
2230         struct coordinate_xy nodes[ISP_PINGPANG_FRGB_GAMC_NUM];
2231 };
2232
2233 struct isp_dev_cmc8_info_v1 {
2234         uint32_t bypass;
2235         uint32_t buf_sel;
2236         uint32_t alpha;
2237         uint32_t alpha_bypass;
2238         struct cmc_matrix matrix;
2239         struct cmc_matrix matrix_buf;
2240 };
2241
2242 struct isp_dev_ct_info {
2243         uint32_t bypass;
2244         //void *data_ptr;
2245         uint32_t data_ptr[2]; //compatible with 64bit cpu
2246         uint32_t size;
2247 };
2248
2249 struct isp_dev_cce_info_v1 {
2250         uint32_t mode;
2251         uint16_t matrix[9];
2252         uint16_t reserved0;
2253         uint16_t y_offset;
2254         uint16_t u_offset;
2255         uint16_t v_offset;
2256         uint16_t reserved1;
2257 };
2258
2259 struct isp_dev_cce_uvd_info {
2260         uint32_t uvdiv_bypass;
2261         uint32_t lum_th_h_len;
2262         uint32_t lum_th_h;
2263         uint32_t lum_th_l_len;
2264         uint32_t lum_th_l;
2265         uint32_t chroma_min_h;
2266         uint32_t chroma_min_l;
2267         uint32_t chroma_max_h;
2268         uint32_t chroma_max_l;
2269         uint32_t u_th1_h;
2270         uint32_t u_th1_l;
2271         uint32_t u_th0_h;
2272         uint32_t u_th0_l;
2273         uint32_t v_th1_h;
2274         uint32_t v_th1_l;
2275         uint32_t v_th0_h;
2276         uint32_t v_th0_l;
2277         uint8_t ratio[9];
2278         uint8_t reserved[3];
2279         uint32_t base;
2280         uint32_t level;
2281 };
2282
2283 struct isp_dev_hsv_info_v1 {
2284         uint32_t bypass;
2285         uint32_t buf_sel;
2286         //void *data_ptr;
2287         uint32_t data_ptr[2]; //compatible with 64bit cpu
2288         uint32_t size;
2289 };
2290
2291 struct isp_dev_csc_info {
2292         uint32_t bypass;
2293         uint32_t red_centre_x;
2294         uint32_t red_centre_y;
2295         uint32_t blue_centre_x;
2296         uint32_t blue_centre_y;
2297         uint32_t red_x2_init;
2298         uint32_t red_y2_init;
2299         uint32_t blue_x2_init;
2300         uint32_t blue_y2_init;
2301         uint32_t red_threshold;
2302         uint32_t blue_threshold;
2303         uint32_t red_p1_param;
2304         uint32_t red_p2_param;
2305         uint32_t blue_p1_param;
2306         uint32_t blue_p2_param;
2307         uint32_t max_gain_thr;
2308         struct isp_img_size img_size;
2309         struct img_offset start_pos;
2310 };
2311
2312 struct isp_dev_pre_cdn_rgb_info {
2313         uint32_t bypass;
2314         uint32_t median_mode;
2315         uint32_t median_thr;
2316         uint32_t thru0;
2317         uint32_t thru1;
2318         uint32_t thrv0;
2319         uint32_t thrv1;
2320         uint32_t level;
2321 };
2322
2323 struct isp_dev_posterize_info {
2324         uint32_t bypass;
2325         uint8_t  posterize_level_bottom[8];
2326         uint8_t  posterize_level_top[8];
2327         uint8_t  posterize_level_out[8];
2328 };
2329
2330 struct isp_dev_rgb_afm_info_v1 {
2331         uint32_t bypass;
2332         uint32_t mode;
2333         uint32_t skip_num;
2334         uint32_t skip_num_clear;
2335         uint32_t spsmd_rtgbot_enable;
2336         uint32_t spsmd_diagonal_enable;
2337         uint32_t spsmd_cal_mode;
2338         uint32_t af_sel_filter1;
2339         uint32_t af_sel_filter2;
2340         uint32_t sobel_type;
2341         uint32_t spsmd_type;
2342         uint32_t sobel_threshold_min;
2343         uint32_t sobel_threshold_max;
2344         uint32_t spsmd_threshold_min;
2345         uint32_t spsmd_threshold_max;
2346         uint32_t frame_width;
2347         uint32_t frame_height;
2348         struct isp_coord coord[ISP_AFM_WIN_NUM_V1];
2349 };
2350
2351 struct isp_dev_rgb2y_info {
2352         uint32_t signal_sel;
2353 };
2354
2355 struct isp_dev_yiq_aem_info_v1 {
2356         uint32_t ygamma_bypass;
2357         int16_t  gamma_xnode[10];
2358         int16_t  gamma_ynode[10];
2359         uint32_t gamma_node_idx[10];
2360         uint32_t aem_bypass;
2361         uint32_t aem_mode;
2362         uint32_t aem_skip_num;
2363         uint32_t offset_x;
2364         uint32_t offset_y;
2365         uint32_t width;
2366         uint32_t height;
2367 };
2368
2369 struct isp_dev_yiq_aem_info_v2 {
2370         uint32_t ygamma_bypass;
2371         uint32_t gamma_xnode[10];
2372         uint32_t gamma_ynode[10];
2373         uint32_t gamma_node_idx[10];
2374         uint32_t aem_bypass;
2375         uint32_t aem_mode;
2376         uint32_t aem_skip_num;
2377         uint32_t offset_x;
2378         uint32_t offset_y;
2379         uint32_t avgshift;
2380         uint32_t width;
2381         uint32_t height;
2382 };
2383
2384
2385 struct isp_dev_anti_flicker_info_v1 {
2386         uint32_t bypass;
2387         uint32_t mode;
2388         uint32_t skip_frame_num;
2389         uint32_t line_step;
2390         uint32_t frame_num;
2391         uint32_t vheight;
2392         uint32_t start_col;
2393         uint32_t end_col;
2394         uint32_t addr;
2395 };
2396
2397 struct isp_dev_yiq_afm_info_v1 {
2398         uint32_t bypass;
2399         uint32_t mode;
2400         uint32_t source_pos;
2401         uint32_t shift;
2402         uint32_t skip_num;
2403         uint32_t skip_num_clear;
2404         uint32_t format;
2405         uint32_t iir_bypass;
2406         struct isp_coord coord[25];
2407         int16_t IIR_c[11];
2408         uint16_t reserved;
2409 };
2410
2411 struct isp_dev_yiq_afm_info_v2 {
2412         uint32_t bypass;
2413         uint32_t mode;
2414         uint32_t shift;
2415         uint32_t skip_num;
2416         uint32_t skip_num_clear;
2417         uint32_t af_position;
2418         uint32_t format;
2419         uint32_t iir_bypass;
2420         struct isp_coord coord[25];
2421         int IIR_c[11];
2422 };
2423
2424
2425 struct isp_dev_yuv_precdn_info {
2426         uint32_t bypass;
2427         uint32_t mode;
2428         uint32_t median_writeback_en;
2429         uint32_t median_mode;
2430         uint32_t den_stren;
2431         uint32_t uv_joint;
2432         uint8_t median_thr_u[2];
2433         uint8_t median_thr_v[2];
2434         uint32_t median_thr;
2435         uint32_t uv_thr;
2436         uint32_t y_thr;
2437         uint8_t r_segu[2][7];
2438         uint8_t r_segv[2][7];
2439         uint8_t r_segy[2][7];
2440         uint8_t r_distw[25];
2441         uint8_t reserved;
2442         uint32_t level;
2443 };
2444
2445 struct isp_dev_prefilter_info_v1 {
2446         uint32_t bypass;
2447         uint32_t writeback;
2448         uint32_t thrd;
2449 };
2450
2451 struct isp_dev_uv_prefilter_info {
2452         uint32_t bypass;
2453         uint32_t writeback;
2454         uint32_t nr_thr_u;
2455         uint32_t nr_thr_v;
2456 };
2457
2458 struct isp_dev_brightness_info {
2459         uint32_t bypass;
2460         uint32_t factor;
2461 };
2462
2463 struct isp_dev_contrast_info {
2464         uint32_t bypass;
2465         uint32_t factor;
2466 };
2467
2468 struct isp_dev_hist_info_v1 {
2469         uint32_t bypass;
2470         uint32_t off;
2471         uint32_t buf_rst_en;
2472         uint32_t pof_rst_en;//pike have no this bit
2473         uint32_t skip_num;
2474         uint32_t skip_num_clr;
2475         uint32_t mode;
2476         uint32_t low_ratio;
2477         uint32_t high_ratio;
2478         uint32_t big_adj;
2479         uint32_t small_adj;
2480         uint32_t dif_adj;
2481 };
2482
2483 struct isp_dev_hist2_info_v1 {
2484         uint32_t bypass;
2485         uint32_t en;//pike has no this bit
2486         uint32_t skip_num;
2487         uint32_t skip_num_clr;
2488         uint32_t mode;
2489         int32_t  hist_roi_x_s[4];
2490         int32_t  hist_roi_y_s[4];
2491         uint32_t hist_roi_x_e[4];
2492         uint32_t hist_roi_y_e[4];
2493 };
2494
2495 struct isp_dev_autocont_info_v1 {
2496         uint32_t bypass;
2497         uint32_t mode;
2498         uint32_t in_min;
2499         uint32_t in_max;
2500         uint32_t out_min;
2501         uint32_t out_max;
2502 };
2503
2504 struct isp_dev_yuv_cdn_info {
2505         uint32_t bypass;
2506         uint32_t filter_bypass;
2507         uint32_t median_writeback_en;
2508         uint32_t median_mode;
2509         uint32_t gaussian_mode;
2510         uint32_t median_thr;
2511         uint32_t median_thru0;
2512         uint32_t median_thru1;
2513         uint32_t median_thrv0;
2514         uint32_t median_thrv1;
2515         uint32_t rangewu[31];
2516         uint32_t rangewv[31];
2517         uint32_t level;
2518 };
2519
2520 struct isp_dev_edge_info_v1 {
2521         uint32_t bypass;
2522         /*CFG0*/
2523         uint32_t ee_str_m_n;
2524         uint32_t ee_str_m_p;
2525         uint32_t ee_str_d_n;
2526         uint32_t ee_str_d_p;
2527         uint32_t mode;
2528         /*CFG1*/
2529         uint32_t ee_incr_d_n;
2530         uint32_t ee_incr_d_p;
2531         uint32_t ee_thr_d_n;
2532         uint32_t ee_thr_d_p;
2533         /*CFG2*/
2534         uint32_t ee_flat_thr_1;
2535         uint32_t ee_flat_thr_2;
2536         uint32_t ee_incr_m_n;
2537         uint32_t ee_incr_m_p;
2538         /*CFG3*/
2539         uint32_t ee_txt_thr_1;
2540         uint32_t ee_txt_thr_2;
2541         uint32_t ee_txt_thr_3;
2542         /*CFG4*/
2543         uint32_t ee_corner_sm_n;
2544         uint32_t ee_corner_sm_p;
2545         uint32_t ee_corner_gain_n;
2546         uint32_t ee_corner_gain_p;
2547         uint32_t ee_corner_th_n;
2548         uint32_t ee_corner_th_p;
2549         uint32_t ee_corner_cor;
2550         /*CFG5*/
2551         uint32_t ee_smooth_strength;
2552         uint32_t ee_smooth_thr;
2553         uint32_t sigma;
2554         uint32_t ee_flat_smooth_mode;
2555         uint32_t ee_edge_smooth_mode;
2556         /*CFG6*/
2557         uint32_t ee_incr_b_n;
2558         uint32_t ee_incr_b_p;
2559         uint32_t ee_str_b_n;
2560         uint32_t ee_str_b_p;
2561         /*CFG7*/
2562         uint8_t ratio[2];
2563         uint16_t reserved;
2564         uint32_t ipd_flat_thr;
2565         uint32_t ipd_bypass;
2566         uint32_t ee_clip_after_smooth_en;
2567
2568         //pike has no ADP_CFG0 ADP_CFG1 ADP_CFG2 registers
2569         /*ADP_CFG0*/
2570         uint32_t ee_t1_cfg;
2571         uint32_t ee_t2_cfg;
2572         uint32_t ee_t3_cfg;
2573         /*ADP_CFG1*/
2574         uint32_t ee_t4_cfg;
2575         uint32_t ee_cv_clip_n;
2576         uint32_t ee_cv_clip_p;
2577         /*ADP_CFG2*/
2578         uint32_t ee_r1_cfg;
2579         uint32_t ee_r2_cfg;
2580         uint32_t ee_r3_cfg;
2581         /*LEVEL*/
2582         uint32_t ee_level;
2583 };
2584
2585 struct isp_dev_css_info_v1 {
2586         uint32_t bypass;
2587         uint32_t lh_chrom_th;
2588         uint8_t  chrom_lower_th[7];
2589         uint8_t  reserved0;
2590         uint8_t  chrom_high_th[7];
2591         uint8_t  reserved1;
2592         uint32_t lum_low_shift;
2593         uint32_t lum_hig_shift;
2594         uint8_t  lh_ratio[8];
2595         uint8_t  ratio[8];
2596         uint32_t lum_low_th;
2597         uint32_t lum_ll_th;
2598         uint32_t lum_hig_th;
2599         uint32_t lum_hh_th;
2600         uint32_t u_th_0_l;
2601         uint32_t u_th_0_h;
2602         uint32_t v_th_0_l;
2603         uint32_t v_th_0_h;
2604         uint32_t u_th_1_l;
2605         uint32_t u_th_1_h;
2606         uint32_t v_th_1_l;
2607         uint32_t v_th_1_h;
2608         uint32_t cutoff_th;
2609 };
2610
2611 struct isp_dev_csa_info_v1 {
2612         uint32_t bypass;
2613         uint32_t factor_u;
2614         uint32_t factor_v;
2615         struct csa_factor_v1 factor;
2616 };
2617
2618 struct isp_dev_hue_info_v1 {
2619         uint32_t bypass;
2620         uint32_t theta;
2621 };
2622
2623 struct isp_dev_post_cdn_info {
2624         uint32_t bypass;
2625         uint32_t downsample_bypass;
2626         uint32_t mode;
2627         uint32_t writeback_en;
2628         uint32_t uvjoint;
2629         uint32_t median_mode;
2630         uint32_t adapt_med_thr;
2631         uint32_t uvthr0;
2632         uint32_t uvthr1;
2633         uint32_t thru0;
2634         uint32_t thru1;
2635         uint32_t thrv0;
2636         uint32_t thrv1;
2637         uint8_t r_segu[2][7];
2638         uint8_t r_segv[2][7];
2639         uint8_t r_distw[15][5];
2640         uint8_t reserved;
2641         uint32_t start_row_mod4;
2642         uint32_t level;
2643 };
2644
2645 struct isp_dev_emboss_info_v1 {
2646         uint32_t y_bypass;
2647         uint32_t uv_bypass;
2648         uint32_t y_step;
2649         uint32_t uv_step;
2650 };
2651
2652 struct isp_dev_ygamma_info {
2653         uint32_t bypass;
2654         uint32_t buf_sel;
2655         struct coordinate_xy nodes[ISP_PINGPANG_YUV_YGAMC_NUM];
2656 };
2657
2658 struct isp_dev_ydelay_info {
2659         uint32_t bypass;
2660 };
2661
2662 struct isp_dev_yuv_nlm_info {
2663         uint32_t nlm_bypass;
2664         uint32_t nlm_radial_bypass;
2665         uint32_t nlm_adaptive_bypass;
2666         uint32_t nlm_vst_bypass;
2667         uint32_t edge_str_req[7];
2668         uint32_t edge_str_cmp[7];
2669         uint32_t edge_range_l;
2670         uint32_t edge_range_h;
2671         uint32_t edge_time_str;
2672         uint32_t avg_mode;
2673         uint32_t den_strength;
2674         uint32_t center_x;
2675         uint32_t center_y;
2676         uint32_t center_x2;
2677         uint32_t center_y2;
2678         uint32_t radius;
2679         uint32_t radius_p1;
2680         uint32_t radius_p2;
2681         uint32_t gain_max;
2682         uint32_t start_col;
2683         uint32_t start_raw;
2684         uint32_t add_back;
2685         uint32_t lut_w[24];
2686         uint32_t lut_vs[64];
2687 };
2688
2689 struct isp_dev_iircnr_info_v1 {
2690         uint32_t bypass;
2691         uint32_t mode;
2692         uint32_t y_th;
2693         uint32_t uv_th;
2694         uint32_t uv_pg_th;
2695         uint32_t uv_dist;
2696         uint32_t uv_low_thr2;
2697         uint32_t uv_low_thr1;
2698         uint32_t uv_s_th;
2699         uint32_t alpha_low_u;
2700         uint32_t alpha_low_v;
2701         uint32_t uv_high_thr2;
2702         uint32_t ymd_u;
2703         uint32_t ymd_v;
2704         uint32_t slope;
2705         uint32_t factor;
2706         uint32_t iirnr_level;
2707 };
2708
2709 struct isp_dev_yrandom_info_v1 {
2710         uint32_t bypass;
2711         uint32_t seed;
2712         uint32_t mode;
2713         uint32_t init;
2714         uint32_t offset;
2715         uint32_t shift;
2716         uint32_t takeBit[8];
2717 };
2718
2719 struct isp_dev_fetch_info_v1 {
2720         uint32_t bypass;
2721         uint32_t substract;
2722         uint32_t color_format;
2723 //      struct isp_img_size slice_size;
2724         struct isp_addr addr;
2725         struct isp_pitch pitch;
2726         uint32_t mipi_word_num;
2727         uint32_t mipi_byte_rel_pos;
2728 };
2729
2730 struct isp_dev_store_info_v1 {
2731         uint32_t bypass;
2732         uint32_t substract;
2733         uint32_t color_format;
2734 //      struct isp_img_size size;
2735         struct isp_addr addr;
2736         struct isp_pitch pitch;
2737 };
2738
2739 struct isp_dev_dispatch_info_v1 {
2740         uint32_t bayer_ch0;
2741         uint32_t bayer_ch1;
2742 };
2743
2744 struct isp_dev_arbiter_info_v1 {
2745         struct arbiter_endian_v1 endian_ch0;
2746         struct arbiter_endian_v1 endian_ch1;
2747         struct arbiter_param_v1 para;
2748 };
2749
2750 struct isp_dev_axi_info_v1 {
2751         uint32_t iti2axim_ctrl;
2752         uint32_t convert_wr_ctrl;
2753 };
2754
2755 struct isp_raw_sizer_init_para {
2756         uint32_t half_dst_wd_remain;
2757         uint32_t residual_half_wd;
2758         uint32_t adv_b_init_residual;
2759         uint32_t adv_a_init_residual;
2760         uint32_t offset_incr_init_b;
2761         uint32_t offset_incr_init_a;
2762         uint32_t offset_base_incr;
2763 };
2764
2765 struct isp_common_lbuf_param_v1 {
2766         uint32_t cfae_lbuf_offset;
2767         uint32_t comm_lbuf_offset;
2768         uint32_t ydly_lbuf_offset;
2769         uint32_t awbm_lbuf_offset;
2770 };
2771
2772 struct isp_dev_common_info_v1 {
2773         uint32_t fetch_sel_0;
2774         uint32_t sizer_sel_0;
2775         uint32_t store_sel_0;
2776         uint32_t fetch_sel_1;
2777         uint32_t sizer_sel_1;
2778         uint32_t store_sel_1;
2779         uint32_t fetch_color_format;
2780         uint32_t store_color_format;
2781         uint32_t awbm_pos;
2782         uint32_t y_afm_pos_0;
2783         uint32_t y_aem_pos_0;
2784         uint32_t y_afm_pos_1;
2785         uint32_t y_aem_pos_1;
2786         struct isp_common_lbuf_param_v1 lbuf_off;
2787 };
2788
2789 struct isp_dev_common_info_v2 {
2790         uint32_t fetch_sel_0;
2791         uint32_t sizer_sel_0;
2792         uint32_t store_sel_0;
2793         uint32_t fetch_sel_1;
2794         uint32_t sizer_sel_1;
2795         uint32_t store_sel_1;
2796         uint32_t fetch_color_format;
2797         uint32_t store_color_format;
2798         uint32_t awbm_pos;
2799         uint32_t y_afm_pos_0;
2800         uint32_t y_aem_pos_0;
2801         uint32_t y_afm_pos_1;
2802         uint32_t y_aem_pos_1;
2803         uint32_t lbuf_off;
2804 };
2805
2806
2807 struct isp_dev_pingpang_ctm_info_v1 {
2808         uint8_t val;
2809 };
2810
2811 struct isp_dev_pingpang_hsv_info_v1 {
2812         uint16_t val;
2813 };
2814
2815
2816 struct isp_dev_pingpang_frgb_gamc_info_v1 {
2817         uint32_t r_node;
2818         uint32_t g_node;
2819         uint32_t b_node;
2820 };
2821
2822 #define ISP_IO_MAGIC         'R'
2823 #define ISP_IO_CAPABILITY    _IOR(ISP_IO_MAGIC, 0, struct isp_capability)
2824 #define ISP_IO_IRQ           _IOR(ISP_IO_MAGIC, 1, struct isp_irq)
2825 #define ISP_IO_READ          _IOR(ISP_IO_MAGIC, 2, struct isp_reg_param)
2826 #define ISP_IO_WRITE         _IOW(ISP_IO_MAGIC, 3, struct isp_reg_param)
2827 #define ISP_IO_RST           _IOW(ISP_IO_MAGIC, 4, uint32_t)
2828 #define ISP_IO_STOP          _IOW(ISP_IO_MAGIC, 5, uint32_t)
2829 #define ISP_IO_INT           _IOW(ISP_IO_MAGIC, 6, uint32_t)
2830 #define ISP_IO_CFG_PARAM     _IOWR(ISP_IO_MAGIC, 7, struct isp_io_param)
2831 #define ISP_REG_READ    _IOR(ISP_IO_MAGIC, 8, struct isp_reg_bits)
2832
2833 #endif