2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 #ifndef _ISP_DRV_KERNEL_H_
14 #define _ISP_DRV_KERNEL_H_
16 #define ISP_BYPASS_EB 1
17 #define ISP_BYPASS_DIS 0
18 #define ISP_AWBM_ITEM 1024
19 #define ISP_HIST_ITEM 256
20 #define ISP_HDR_COMP_ITEM 64
21 #define ISP_HDR_P2E_ITEM 32
22 #define ISP_HDR_E2P_ITEM 32
23 #define ISP_AEM_ITEM 1024
26 #define ISP_RAW_AWBM_ITEM 256
27 #define ISP_RAW_AEM_ITEM 1024
28 #define ISP_3D_LUT_ITEM 729
29 #define ISP_RAW_AFM_ITEM 25
30 #define ISP_YIQ_AFM_ITEM 100
31 #define ISP_HSV_ITEM 361
34 #define ISP_CMC_MATRIX_TAB_MAX 9
35 #define ISP_GAMMA_NODE_MAX 66
36 #define ISP_CCE_MATRIX_TAB_MAX 9
37 #define ISP_CCE_UVD_NUM 7
38 #define ISP_CCE_UVC0_NUM 2
39 #define ISP_CCE_UVC1_NUM 3
40 #define ISP_AFM_WIN_NUM 9
41 #define ISP_CSS_LOWER_NUM 7
42 #define ISP_CSS_LOWER_SUM_NUM 7
43 #define ISP_CSS_RATIO_NUM 8
44 #define ISP_NLC_R_NODE_NUM 29
45 #define ISP_NLC_G_NODE_NUM 29
46 #define ISP_NLC_B_NODE_NUM 29
47 #define ISP_NLC_L_NODE_NUM 27
48 #define ISP_YIQ_YGAMMA_XNODE_NUM 8
49 #define ISP_YIQ_YGAMMA_YNODE_NUM 10
50 #define ISP_YIQ_YGAMMA_NODE_INDEX_NUM 9
51 #define ISP_PINGPANG_YUV_YGAMC_NUM 129
55 ISP_CHIP_ID_INVALID = 0x00,
56 ISP_CHIP_ID_SC8820 = 0xA55A8820,
57 ISP_CHIP_ID_SC9630 = 0xA55A9630,
58 ISP_CHIP_ID_SC9930 = 0xA55A9930
61 enum isp_interrupt_mode {
62 ISP_INT_VIDEO_MODE = 0x00,
79 ISP_LNC_STATUS_OK = (1<<0),
83 ISP_INT_HIST_STORE = (1<<0),
84 ISP_INT_STORE = (1<<1),
85 ISP_INT_LSC_LOAD = (1<<2),
86 ISP_INT_HIST_CAL = (1<<3),
87 ISP_INT_HIST_RST = (1<<4),
88 ISP_INT_FETCH_BUF_FULL = (1<<5),
89 ISP_INT_STORE_BUF_FULL = (1<<6),
90 ISP_INT_STORE_ERR = (1<<7),
91 ISP_INT_SHADOW = (1<<8),
92 ISP_INT_PREVIEW_STOP = (1<<9),
93 ISP_INT_AWB_DONE = (1<<10),
94 ISP_INT_AF_DONE = (1<<11),
95 ISP_INT_SLICE_CNT = (1<<12),
96 ISP_INT_AE_DONE = (1<<13),
97 ISP_INT_ANTI_FLICKER = (1<<14),
98 ISP_INT_AWB_START = (1<<15),
99 ISP_INT_AF_START = (1<<16),
100 ISP_INT_AE_START = (1<<17),
101 ISP_INT_DCAM_SOF = (1<<18),
102 ISP_INT_DCAM_EOF = (1<<19),
103 ISP_INT_AFM_WIN8 = (1<<20),
104 ISP_INT_AFM_WIN7 = (1<<21),
105 ISP_INT_AFM_WIN6 = (1<<22),
106 ISP_INT_AFM_WIN5 = (1<<23),
107 ISP_INT_AFM_WIN4 = (1<<24),
108 ISP_INT_AFM_WIN3 = (1<<25),
109 ISP_INT_AFM_WIN2 = (1<<26),
110 ISP_INT_AFM_WIN1 = (1<<27),
111 ISP_INT_AFM_WIN0 = (1<<28),
114 /*********pike**********/
116 ISP_INT_P_ISP_ALL_DONE = (1<<0),
117 ISP_INT_P_STORE_DONE = (1<<1),
118 ISP_INT_P_LENS_LOAD = (1<<2),
119 ISP_INT_P_ISP_START = (1<<3),
120 ISP_INT_P_ISP_BUF_FULL = (1<<4),
121 ISP_INT_P_DCAM_BUF_FULL = (1<<5),
122 ISP_INT_P_STORE_BUF_FULL = (1<<6),
123 ISP_INT_P_SHADOW_DONE = (1<<7),
124 ISP_INT_P_AWBM_DONE = (1<<8),
125 ISP_INT_P_AFM_DONE = (1<<9),
126 ISP_INT_P_AEM_DONE = (1<<10),
127 ISP_INT_P_AEM2_DONE = (1<<11),
128 ISP_INT_P_ANTI_FILCKER_DONE = (1<<12),
129 ISP_INT_P_BINNING_DONE = (1<<13),
130 ISP_INT_P_DCAM_SOF = (1<<14),
131 ISP_INT_P_DCAM_EOF = (1<<15),
132 ISP_INT_P_HIST_CAL = (1<<16),
133 ISP_INT_P_HIST_RST = (1<<17),
134 ISP_INT_P_HIST2 = (1<<18),
135 ISP_INT_P_LENS_ERR = (1<<19),
136 ISP_INT_P_AWBM_ERR = (1<<20),
137 ISP_INT_P_BINNING_ERR = (1<<21),
138 ISP_INT_P_BINNING_ERR1 = (1<<22),
139 ISP_INT_P_BPC_ERR2 = (1<<23),
140 ISP_INT_P_BPC_ERR1 = (1<<24),
141 ISP_INT_P_BPC_ERR0 = (1<<25),
142 ISP_INT_P_AFM_START = (1<<26),
143 ISP_INT_P_AEM_START = (1<<27),
144 ISP_INT_P_AEM2_START = (1<<28),
148 ISP_INT_P_AFM_Y_WIN0 = (1<<0),
149 ISP_INT_P_AFM_Y_WIN1 = (1<<1),
150 ISP_INT_P_AFM_Y_WIN2 = (1<<2),
151 ISP_INT_P_AFM_Y_WIN3 = (1<<3),
152 ISP_INT_P_AFM_Y_WIN4 = (1<<4),
153 ISP_INT_P_AFM_Y_WIN5 = (1<<5),
154 ISP_INT_P_AFM_Y_WIN6 = (1<<6),
155 ISP_INT_P_AFM_Y_WIN7 = (1<<7),
156 ISP_INT_P_AFM_Y_WIN8 = (1<<8),
157 ISP_INT_P_AFM_Y_WIN9 = (1<<9),
158 ISP_INT_P_AFM_Y_WIN10 = (1<<10),
159 ISP_INT_P_AFM_Y_WIN11 = (1<<11),
160 ISP_INT_P_AFM_Y_WIN12 = (1<<12),
161 ISP_INT_P_AFM_Y_WIN13 = (1<<13),
162 ISP_INT_P_AFM_Y_WIN14 = (1<<14),
163 ISP_INT_P_AFM_Y_WIN15 = (1<<15),
164 ISP_INT_P_AFM_Y_WIN16 = (1<<16),
165 ISP_INT_P_AFM_Y_WIN17 = (1<<17),
166 ISP_INT_P_AFM_Y_WIN18 = (1<<18),
167 ISP_INT_P_AFM_Y_WIN19 = (1<<19),
168 ISP_INT_P_AFM_Y_WIN20 = (1<<20),
169 ISP_INT_P_AFM_Y_WIN21 = (1<<21),
170 ISP_INT_P_AFM_Y_WIN22 = (1<<22),
171 ISP_INT_P_AFM_Y_WIN23 = (1<<23),
172 ISP_INT_P_AFM_Y_WIN24 = (1<<24),
176 ISP_INT_P_AFM_RGB_WIN0 = (1<<0),
177 ISP_INT_P_AFM_RGB_WIN1 = (1<<1),
178 ISP_INT_P_AFM_RGB_WIN2 = (1<<2),
179 ISP_INT_P_AFM_RGB_WIN3 = (1<<3),
180 ISP_INT_P_AFM_RGB_WIN4 = (1<<4),
181 ISP_INT_P_AFM_RGB_WIN5 = (1<<5),
182 ISP_INT_P_AFM_RGB_WIN6 = (1<<6),
183 ISP_INT_P_AFM_RGB_WIN7 = (1<<7),
184 ISP_INT_P_AFM_RGB_WIN8 = (1<<8),
185 ISP_INT_P_AFM_RGB_WIN9 = (1<<9),
186 ISP_INT_P_AFM_RGB_WIN10 = (1<<10),
187 ISP_INT_P_AFM_RGB_WIN11 = (1<<11),
188 ISP_INT_P_AFM_RGB_WIN12 = (1<<12),
189 ISP_INT_P_AFM_RGB_WIN13 = (1<<13),
190 ISP_INT_P_AFM_RGB_WIN14 = (1<<14),
191 ISP_INT_P_AFM_RGB_WIN15 = (1<<15),
192 ISP_INT_P_AFM_RGB_WIN16 = (1<<16),
193 ISP_INT_P_AFM_RGB_WIN17 = (1<<17),
194 ISP_INT_P_AFM_RGB_WIN18 = (1<<18),
195 ISP_INT_P_AFM_RGB_WIN19 = (1<<19),
196 ISP_INT_P_AFM_RGB_WIN20 = (1<<20),
197 ISP_INT_P_AFM_RGB_WIN21 = (1<<21),
198 ISP_INT_P_AFM_RGB_WIN22 = (1<<22),
199 ISP_INT_P_AFM_RGB_WIN23 = (1<<23),
200 ISP_INT_P_AFM_RGB_WIN24 = (1<<24),
204 ISP_INT_P_YUV_DONE = (1<<0),
205 ISP_INT_P_YUV_POSTCDN = (1<<1),
206 ISP_INT_P_YUV_CDN_DONE = (1<<2),
207 ISP_INT_P_YUV_EE_DONE = (1<<3),
208 ISP_INT_P_YUV_NLM_DONE = (1<<4),
209 ISP_INT_P_YUV_PRF_UV_DONE = (1<<5),
210 ISP_INT_P_YUV_PRF_Y_DONE = (1<<6),
211 ISP_INT_P_YUV_START = (1<<7),
212 ISP_INT_P_FRGB_CCE_DONE = (1<<8),
213 ISP_INT_P_FRGB_CCE_START = (1<<9),
214 ISP_INT_P_FRGB_DONE = (1<<10),
215 ISP_INT_P_FRGB_START = (1<<11),
216 ISP_INT_P_FRGB_CF_AE_DONE = (1<<12),
217 ISP_INT_P_FRGB_CF_AE_START = (1<<13),
218 ISP_INT_P_RRGB_DONE = (1<<14),
219 ISP_INT_P_RRGB_BDN_DONE = (1<<15),
220 ISP_INT_P_RRGB_PWD_DONE = (1<<16),
221 ISP_INT_P_RRGB_BPC_DONE = (1<<17),
222 ISP_INT_P_RRGB_LENS_DONE = (1<<18),
223 ISP_INT_P_RRGB_NLM_DONE = (1<<19),
224 ISP_INT_P_RRGB_START = (1<<20),
227 /*********tshark2***********/
229 ISP_INT_ISP_ALL_DONE = (1<<0),
230 ISP_INT_SHADOW_DONE = (1<<1),
231 ISP_INT_STORE_DONE = (1<<2),
232 ISP_INT_ISP_STRAT = (1<<3),
233 ISP_INT_FETCH_BUFFER_FULL = (1<<4),
234 ISP_INT_STORE_BUFFER_FULL = (1<<5),
235 ISP_INT_ISP2DCAM_AFIFO_FULL = (1<<6),
236 ISP_INT_LSC_LOAD_DONE = (1<<7),
237 ISP_INT_AEM_START = (1<<8),
238 ISP_INT_AEM_DONE = (1<<9),
239 ISP_INT_AEM2_START = (1<<10),
240 ISP_INT_AEM2_DONE = (1<<11),
241 ISP_INT_AFM_Y_START = (1<<12),
242 ISP_INT_AFM_Y_DONE = (1<<13),
243 ISP_INT_AFM_RGB_START = (1<<14),
244 ISP_INT_AFM_RGB_DONE = (1<<15),
245 ISP_INT_AWBM_START = (1<<16),
246 ISP_INT_AWBM_DONE = (1<<17),
247 ISP_INT_BINNING_DONE = (1<<18),
248 ISP_INT_BINNING_START = (1<<19),
249 ISP_INT_AFL_START = (1<<20),
250 ISP_INT_AFL_DONE = (1<<21),
251 ISP_INT_DCAMERA_SOF = (1<<22),
252 ISP_INT_DCAMERA_EOF = (1<<23),
253 ISP_INT_HIST_START = (1<<24),
254 ISP_INT_HIST_DONE = (1<<25),
255 ISP_INT_HIST2_START = (1<<26),
256 ISP_INT_HIST2_DONE = (1<<27),
257 ISP_INT_HIST2_WIN0_DONE = (1<<28),
258 ISP_INT_HIST2_WIN1_DONE = (1<<29),
259 ISP_INT_HIST2_WIN2_DONE = (1<<30),
260 ISP_INT_HIST2_WIN3_DONE = (1<<31),
264 ISP_INT_AFM_Y_WIN0 = (1<<0),
265 ISP_INT_AFM_Y_WIN1 = (1<<1),
266 ISP_INT_AFM_Y_WIN2 = (1<<2),
267 ISP_INT_AFM_Y_WIN3 = (1<<3),
268 ISP_INT_AFM_Y_WIN4 = (1<<4),
269 ISP_INT_AFM_Y_WIN5 = (1<<5),
270 ISP_INT_AFM_Y_WIN6 = (1<<6),
271 ISP_INT_AFM_Y_WIN7 = (1<<7),
272 ISP_INT_AFM_Y_WIN8 = (1<<8),
273 ISP_INT_AFM_Y_WIN9 = (1<<9),
274 ISP_INT_AFM_Y_WIN10 = (1<<10),
275 ISP_INT_AFM_Y_WIN11 = (1<<11),
276 ISP_INT_AFM_Y_WIN12 = (1<<12),
277 ISP_INT_AFM_Y_WIN13 = (1<<13),
278 ISP_INT_AFM_Y_WIN14 = (1<<14),
279 ISP_INT_AFM_Y_WIN15 = (1<<15),
280 ISP_INT_AFM_Y_WIN16 = (1<<16),
281 ISP_INT_AFM_Y_WIN17 = (1<<17),
282 ISP_INT_AFM_Y_WIN18 = (1<<18),
283 ISP_INT_AFM_Y_WIN19 = (1<<19),
284 ISP_INT_AFM_Y_WIN20 = (1<<20),
285 ISP_INT_AFM_Y_WIN21 = (1<<21),
286 ISP_INT_AFM_Y_WIN22 = (1<<22),
287 ISP_INT_AFM_Y_WIN23 = (1<<23),
288 ISP_INT_AFM_Y_WIN24 = (1<<24),
289 ISP_INT_DISPATCH_BUF_FULL = (1<<25),
290 ISP_INT_AWBM_ERR = (1<<26),
291 ISP_INT_BINNING_ERR1 = (1<<27),
292 ISP_INT_BINNING_ERR0 = (1<<28),
293 ISP_INT_BPC_ERR2 = (1<<29),
294 ISP_INT_BPC_ERR1 = (1<<30),
295 ISP_INT_BPC_ERR0 = (1<<31),
299 ISP_INT_AFM_RGB_WIN0 = (1<<0),
300 ISP_INT_AFM_RGB_WIN1 = (1<<1),
301 ISP_INT_AFM_RGB_WIN2 = (1<<2),
302 ISP_INT_AFM_RGB_WIN3 = (1<<3),
303 ISP_INT_AFM_RGB_WIN4 = (1<<4),
304 ISP_INT_AFM_RGB_WIN5 = (1<<5),
305 ISP_INT_AFM_RGB_WIN6 = (1<<6),
306 ISP_INT_AFM_RGB_WIN7 = (1<<7),
307 ISP_INT_AFM_RGB_WIN8 = (1<<8),
308 ISP_INT_AFM_RGB_WIN9 = (1<<9),
309 ISP_INT_AFM_RGB_WIN10 = (1<<10),
310 ISP_INT_AFM_RGB_WIN11 = (1<<11),
311 ISP_INT_AFM_RGB_WIN12 = (1<<12),
312 ISP_INT_AFM_RGB_WIN13 = (1<<13),
313 ISP_INT_AFM_RGB_WIN14 = (1<<14),
314 ISP_INT_AFM_RGB_WIN15 = (1<<15),
315 ISP_INT_AFM_RGB_WIN16 = (1<<16),
316 ISP_INT_AFM_RGB_WIN17 = (1<<17),
317 ISP_INT_AFM_RGB_WIN18 = (1<<18),
318 ISP_INT_AFM_RGB_WIN19 = (1<<19),
319 ISP_INT_AFM_RGB_WIN20 = (1<<20),
320 ISP_INT_AFM_RGB_WIN21 = (1<<21),
321 ISP_INT_AFM_RGB_WIN22 = (1<<22),
322 ISP_INT_AFM_RGB_WIN23 = (1<<23),
323 ISP_INT_AFM_RGB_WIN24 = (1<<24),
327 ISP_INT_EVT_STOP = (1<<31),
331 ISP_INT_EVT_HIST_STORE = (1<<0),
332 /*ISP_INT_EVT_STORE = (1<<1),*/
333 /*ISP_INT_EVT_LSC_LOAD = (1<<2),*/
334 ISP_INT_EVT_HIST_CAL = (1<<3),
335 ISP_INT_EVT_HIST_RST = (1<<4),
336 /*ISP_INT_EVT_FETCH_BUF_FULL = (1<<5),*/
337 /*ISP_INT_EVT_STORE_BUF_FULL = (1<<6),*/
338 ISP_INT_EVT_STORE_ERR = (1<<7),
339 /*ISP_INT_EVT_SHADOW = (1<<8),*/
340 ISP_INT_EVT_PREVIEW_STOP = (1<<9),
341 /*ISP_INT_EVT_AWB = (1<<10),*/
342 /*ISP_INT_EVT_AF = (1<<11),*/
343 ISP_INT_EVT_SLICE_CNT = (1<<12),
344 /*ISP_INT_EVT_AE = (1<<13),*/
345 /*ISP_INT_EVT_ANTI_FLICKER = (1<<14),*/
346 /*ISP_INT_EVT_AWBM_START = (1<<15),*/
347 /*ISP_INT_EVT_AFM_START = (1<<16),*/
348 /*ISP_INT_EVT_AE_START = (1<<17),*/
349 /*ISP_INT_EVT_DCAM_SOF = (1<<18),*/
350 /*ISP_INT_EVT_DCAM_EOF = (1<<19),*/
351 /*ISP_INT_EVT_AFM_WIN8 = (1<<20),*/
352 /*ISP_INT_EVT_AFM_WIN7 = (1<<21),*/
353 /*ISP_INT_EVT_AFM_WIN6 = (1<<22),*/
354 /*ISP_INT_EVT_AFM_WIN5 = (1<<23),*/
355 /*ISP_INT_EVT_AFM_WIN4 = (1<<24),*/
356 /*ISP_INT_EVT_AFM_WIN3 = (1<<25),*/
357 /*ISP_INT_EVT_AFM_WIN2 = (1<<26),*/
358 /*ISP_INT_EVT_AFM_WIN1 = (1<<27),*/
359 /*ISP_INT_EVT_AFM_WIN0 = (1<<28),*/
362 /*******tshark2*******/
364 ISP_INT_EVT_ISP_ALL_DONE = (1<<0),
365 ISP_INT_EVT_SHADOW_DONE = (1<<1),
366 ISP_INT_EVT_STORE_DONE = (1<<2),
367 ISP_INT_EVT_ISP_STRAT = (1<<3),
368 ISP_INT_EVT_FETCH_BUF_FULL = (1<<4),
369 ISP_INT_EVT_STORE_BUF_FULL = (1<<5),
370 ISP_INT_EVT_ISP2DCAM_AFIFO_FULL = (1<<6),
371 ISP_INT_EVT_LSC_LOAD = (1<<7),
372 ISP_INT_EVT_AEM_START = (1<<8),
373 ISP_INT_EVT_AEM_DONE = (1<<9),
374 ISP_INT_EVT_AEM2_START = (1<<10),
375 ISP_INT_EVT_AEM2_DONE = (1<<11),
376 ISP_INT_EVT_AFM_Y_START = (1<<12),
377 ISP_INT_EVT_AFM_Y_DONE = (1<<13),
378 ISP_INT_EVT_AFM_RGB_START = (1<<14),
379 ISP_INT_EVT_AFM_RGB_DONE = (1<<15),
380 ISP_INT_EVT_AWBM_START = (1<<16),
381 ISP_INT_EVT_AWBM_DONE = (1<<17),
382 ISP_INT_EVT_BINNING_DONE = (1<<18),
383 ISP_INT_EVT_BINNING_START = (1<<19),
384 ISP_INT_EVT_AFL_START = (1<<20),
385 ISP_INT_EVT_AFL_DONE = (1<<21),
386 ISP_INT_EVT_DCAM_SOF = (1<<22),
387 ISP_INT_EVT_DCAM_EOF = (1<<23),
388 ISP_INT_EVT_HIST_START = (1<<24),
389 ISP_INT_EVT_HIST_DONE = (1<<25),
390 ISP_INT_EVT_HIST2_START = (1<<26),
391 ISP_INT_EVT_HIST2_DONE = (1<<27),
392 ISP_INT_EVT_HIST2_WIN0_DONE = (1<<28),
393 ISP_INT_EVT_HIST2_WIN1_DONE = (1<<29),
394 ISP_INT_EVT_HIST2_WIN2_DONE = (1<<30),
395 ISP_INT_EVT_HIST2_WIN3_DONE = (1<<31),
399 ISP_INT_EVT_AFM_Y_WIN0 = (1<<0),
400 ISP_INT_EVT_AFM_Y_WIN1 = (1<<1),
401 ISP_INT_EVT_AFM_Y_WIN2 = (1<<2),
402 ISP_INT_EVT_AFM_Y_WIN3 = (1<<3),
403 ISP_INT_EVT_AFM_Y_WIN4 = (1<<4),
404 ISP_INT_EVT_AFM_Y_WIN5 = (1<<5),
405 ISP_INT_EVT_AFM_Y_WIN6 = (1<<6),
406 ISP_INT_EVT_AFM_Y_WIN7 = (1<<7),
407 ISP_INT_EVT_AFM_Y_WIN8 = (1<<8),
408 ISP_INT_EVT_AFM_Y_WIN9 = (1<<9),
409 ISP_INT_EVT_AFM_Y_WIN10 = (1<<10),
410 ISP_INT_EVT_AFM_Y_WIN11 = (1<<11),
411 ISP_INT_EVT_AFM_Y_WIN12 = (1<<12),
412 ISP_INT_EVT_AFM_Y_WIN13 = (1<<13),
413 ISP_INT_EVT_AFM_Y_WIN14 = (1<<14),
414 ISP_INT_EVT_AFM_Y_WIN15 = (1<<15),
415 ISP_INT_EVT_AFM_Y_WIN16 = (1<<16),
416 ISP_INT_EVT_AFM_Y_WIN17 = (1<<17),
417 ISP_INT_EVT_AFM_Y_WIN18 = (1<<18),
418 ISP_INT_EVT_AFM_Y_WIN19 = (1<<19),
419 ISP_INT_EVT_AFM_Y_WIN20 = (1<<20),
420 ISP_INT_EVT_AFM_Y_WIN21 = (1<<21),
421 ISP_INT_EVT_AFM_Y_WIN22 = (1<<22),
422 ISP_INT_EVT_AFM_Y_WIN23 = (1<<23),
423 ISP_INT_EVT_AFM_Y_WIN24 = (1<<24),
424 ISP_INT_EVT_DISPATCH_BUF_FULL = (1<<25),
425 ISP_INT_EVT_AWBM_ERR = (1<<26),
426 ISP_INT_EVT_BINNING_ERR1 = (1<<27),
427 ISP_INT_EVT_BINNING_ERR0 = (1<<28),
428 ISP_INT_EVT_BPC_ERR2 = (1<<29),
429 ISP_INT_EVT_BPC_ERR1 = (1<<30),
430 ISP_INT_EVT_BPC_ERR0 = (1<<31),
434 ISP_INT_EVT_AFM_RGB_WIN0 = (1<<0),
435 ISP_INT_EVT_AFM_RGB_WIN1 = (1<<1),
436 ISP_INT_EVT_AFM_RGB_WIN2 = (1<<2),
437 ISP_INT_EVT_AFM_RGB_WIN3 = (1<<3),
438 ISP_INT_EVT_AFM_RGB_WIN4 = (1<<4),
439 ISP_INT_EVT_AFM_RGB_WIN5 = (1<<5),
440 ISP_INT_EVT_AFM_RGB_WIN6 = (1<<6),
441 ISP_INT_EVT_AFM_RGB_WIN7 = (1<<7),
442 ISP_INT_EVT_AFM_RGB_WIN8 = (1<<8),
443 ISP_INT_EVT_AFM_RGB_WIN9 = (1<<9),
444 ISP_INT_EVT_AFM_RGB_WIN10 = (1<<10),
445 ISP_INT_EVT_AFM_RGB_WIN11 = (1<<11),
446 ISP_INT_EVT_AFM_RGB_WIN12 = (1<<12),
447 ISP_INT_EVT_AFM_RGB_WIN13 = (1<<13),
448 ISP_INT_EVT_AFM_RGB_WIN14 = (1<<14),
449 ISP_INT_EVT_AFM_RGB_WIN15 = (1<<15),
450 ISP_INT_EVT_AFM_RGB_WIN16 = (1<<16),
451 ISP_INT_EVT_AFM_RGB_WIN17 = (1<<17),
452 ISP_INT_EVT_AFM_RGB_WIN18 = (1<<18),
453 ISP_INT_EVT_AFM_RGB_WIN19 = (1<<19),
454 ISP_INT_EVT_AFM_RGB_WIN20 = (1<<20),
455 ISP_INT_EVT_AFM_RGB_WIN21 = (1<<21),
456 ISP_INT_EVT_AFM_RGB_WIN22 = (1<<22),
457 ISP_INT_EVT_AFM_RGB_WIN23 = (1<<23),
458 ISP_INT_EVT_AFM_RGB_WIN24 = (1<<24),
473 ISP_BLOCK_PRE_FILTER,
474 ISP_BLOCK_BRIGHTNESS,
490 ISP_BLOCK_PRE_WAVELET,
491 ISP_BLOCK_BINNING4AWB,
492 ISP_BLOCK_PRE_GLB_GAIN,
499 /***************Tshark2**************************************/
512 ISP_BLOCK_PRE_CDN_RGB,
516 ISP_BLOCK_ANTI_FLICKER,
518 ISP_BLOCK_YUV_PRECDN,
519 ISP_BLOCK_PRE_FILTER_V1,
528 ISP_BLOCK_ARBITER_V1,
531 /***************pike**************************************/
534 ISP_BLOCK_UV_PREFILTER,
539 enum isp_fetch_property {
541 ISP_PRO_FETCH_SLICE_SIZE,
542 ISP_PRO_FETCH_START_ISP,
545 enum isp_blc_property {
547 ISP_PRO_BLC_SLICE_SIZE,
548 ISP_PRO_BLC_SLICE_INFO,
551 enum isp_2d_lsc_property {
552 ISP_PRO_2D_LSC_BLOCK,
553 ISP_PRO_2D_LSC_BYPASS,
554 ISP_PRO_2D_LSC_PARAM_UPDATE,
556 ISP_PRO_2D_LSC_GRID_SIZE,
557 ISP_PRO_2D_LSC_LOAD_BUF_SEL,
558 ISP_PRO_2D_LSC_SLICE_SIZE,
559 ISP_PRO_2D_LSC_TRANSADDR,
563 enum isp_1d_lsc_property {
564 ISP_PRO_1D_LSC_BLOCK,
565 ISP_PRO_1D_LSC_SLICE_SIZE,
569 enum isp_awb_property {
571 ISP_PRO_AWBM_STATISTICS,
574 ISP_PRO_AWBM_SKIP_NUM,
575 ISP_PRO_AWBM_SKIP_NUM_CLR,
576 ISP_PRO_AWBM_BLOCK_OFFSET,
577 ISP_PRO_AWBM_BLOCK_SIZE,
579 ISP_PRO_AWBM_THR_BYPASS,
582 ISP_PRO_AWBM_CLCTOR_POS,
583 ISP_PRO_AWBM_CLCTOR_PIXEL_NUM,
584 ISP_PRO_AWBM_THR_VALUE,
585 ISP_PRO_AWBM_MEM_ADDR,
589 ISP_PRO_AWBC_GAIN_OFFSET,
592 enum isp_bpc_property {
596 ISP_PRO_BPC_PARAM_COMMON,
598 ISP_PRO_BPC_MAP_ADDR,
599 ISP_PRO_BPC_PIXEL_NUM,
600 ISP_PRO_BPC_DIFF_THRD,
603 enum isp_wavelet_denoise_property {
606 ISP_PRO_BDN_SLICE_SIZE,
611 enum isp_grgb_property {
617 enum isp_cfa_property {
620 ISP_PRO_CFA_SLICE_SIZE,
621 ISP_PRO_CFA_SLICE_INFO,
624 enum isp_cmc_property {
630 enum isp_gamma_property {
632 ISP_PRO_GAMMA_BYPASS,
636 enum isp_cce_property {
637 ISP_PRO_CCE_BLOCK_MATRIX,
638 ISP_PRO_CCE_BLOCK_UV,
639 ISP_PRO_CCE_UVDIVISION_BYPASS,
643 ISP_PRO_CCE_UVD_THRD,
644 ISP_PRO_CCE_UVC_PARAM,
647 enum isp_prefilter_property {
650 ISP_PRO_PREF_WRITEBACK,
652 ISP_PRO_PREF_SLICE_SIZE,
653 ISP_PRO_PREF_SLICE_INFO,
656 enum isp_brightness_property {
657 ISP_PRO_BRIGHT_BLOCK,
658 ISP_PRO_BRIGHT_SLICE_SIZE,
659 ISP_PRO_BRIGHT_SLICE_INFO,
662 enum isp_contrast_property {
663 ISP_PRO_CONTRAST_BLOCK,
666 enum isp_hist_property {
669 ISP_PRO_HIST_AUTO_RST_DISABLE,
673 ISP_PRO_HIST_CLEAR_EB,
674 ISP_PRO_HIST_STATISTIC,
675 ISP_PRO_HIST_STATISTIC_NUM,
676 ISP_PRO_HIST_SLICE_SIZE,
679 enum isp_autocont_property {
687 enum isp_afm_property {
692 ISP_PRO_AFM_SKIP_NUM,
693 ISP_PRO_AFM_SKIP_NUM_CLR,
695 ISP_PRO_AFM_STATISTIC,
699 enum isp_edge_property {
705 enum isp_emboss_property {
706 ISP_PRO_EMBOSS_BLOCK,
707 ISP_PRO_EMBOSS_BYPASS,
708 ISP_PRO_EMBOSS_PARAM,
711 enum isp_fcs_property {
717 enum isp_css_property {
721 ISP_PRO_CSS_SLICE_SIZE,
725 enum isp_csa_property {
731 enum isp_store_property {
733 ISP_PRO_STORE_SLICE_SIZE,
736 enum isp_feeder_property {
737 ISP_PRO_FEEDER_BLOCK,
738 ISP_PRO_FEEDER_DATA_TYPE,
739 ISP_PRO_FEEDER_SLICE_SIZE,
742 enum isp_hdr_property {
750 enum isp_nlc_property {
759 enum isp_nawbm_property {
761 ISP_PRO_NAWBM_BYPASS,
764 enum isp_pre_wavelet_property {
765 ISP_PRO_PRE_WAVELET_BLOCK,
766 ISP_PRO_PRE_WAVELET_BYPASS,
769 enum isp_binging4awb_property {
770 ISP_PRO_BINNING4AWB_BLOCK,
771 ISP_PRO_BINNING4AWB_BYPASS,
772 ISP_PRO_BINNING4AWB_SCALING_RATIO,
773 ISP_PRO_BINNING4AWB_MEM_ADDR,
774 ISP_PRO_BINNING4AWB_STATISTICS_BUF,
775 ISP_PRO_BINNING4AWB_TRANSADDR,
778 enum isp_pre_glb_gain_property {
779 ISP_PRO_PRE_GLB_GAIN_BLOCK,
782 enum isp_common_property {
783 ISP_PRO_COMMON_START,
784 ISP_PRO_COMMON_IN_MODE,
785 ISP_PRO_COMMON_OUT_MODE,
786 ISP_PRO_COMMON_FETCH_ENDIAN,
787 ISP_PRO_COMMON_BPC_ENDIAN,
788 ISP_PRO_COMMON_STORE_ENDIAN,
789 ISP_PRO_COMMON_FETCH_DATA_FORMAT,
790 ISP_PRO_COMMON_STORE_FORMAT,
791 ISP_PRO_COMMON_BURST_SIZE,
792 ISP_PRO_COMMON_MEM_SWITCH,
793 ISP_PRO_COMMON_SHADOW,
794 ISP_PRO_COMMON_SHADOW_ALL,
795 ISP_PRO_COMMON_BAYER_MODE,
796 ISP_PRO_COMMON_INT_REGISTER,
797 ISP_PRO_COMMON_INT_CLEAR,
798 ISP_PRO_COMMON_GET_INT_RAW,
799 ISP_PRO_COMMON_PMU_RAW_MASK,
800 ISP_PRO_COMMON_HW_MASK,
801 ISP_PRO_COMMON_HW_ENABLE,
802 ISP_PRO_COMMON_PMU_SEL,
803 ISP_PRO_COMMON_SW_ENABLE,
804 ISP_PRO_COMMON_PREVIEW_STOP,
805 ISP_PRO_COMMON_SET_SHADOW_CONTROL,
806 ISP_PRO_COMMON_SHADOW_CONTROL_CLEAR,
807 ISP_PRO_COMMON_AXI_STOP,
808 ISP_PRO_COMMON_SLICE_CNT_ENABLE,
809 ISP_PRO_COMMON_PREFORM_CNT_ENABLE,
810 ISP_PRO_COMMON_SET_SLICE_NUM,
811 ISP_PRO_COMMON_GET_SLICE_NUM,
812 ISP_PRO_COMMON_PERFORM_CNT_RSTATUS,
813 ISP_PRO_COMMON_PERFORM_CNT_STATUS,
816 enum isp_glb_gain_property {
817 ISP_PRO_GLB_GAIN_BLOCK,
818 ISP_PRO_GLB_GAIN_BYPASS,
819 ISP_PRO_GLB_GAIN_SET,
820 ISP_PRO_GLB_GAIN_SLICE_SIZE,
823 enum isp_rgb_gain_property {
824 ISP_PRO_RGB_GAIN_BLOCK,
827 enum isp_yiq_property {
828 ISP_RPO_YIQ_BLOCK_YGAMMA,
829 ISP_RPO_YIQ_BLOCK_AE,
830 ISP_RPO_YIQ_BLOCK_FLICKER,
831 ISP_PRO_YIQ_YGAMMA_BYPASS,
832 ISP_PRO_YIQ_YGAMMA_XNODE,
833 ISP_PRO_YIQ_YGAMMA_YNODE,
834 ISP_PRO_YIQ_YGAMMA_INDEX,
835 ISP_PRO_YIQ_AE_BYPASS,
836 ISP_PRO_YIQ_AE_SOURCE_SEL,
838 ISP_PRO_YIQ_AE_SKIP_NUM,
839 ISP_PRO_YIQ_FLICKER_BYPASS,
840 ISP_PRO_YIQ_FLICKER_MODE,
841 ISP_PRO_YIQ_FLICKER_VHEIGHT,
842 ISP_PRO_YIQ_FLICKER_LINE_CONTER,
843 ISP_PRO_YIQ_FLICKER_LINE_STEP,
844 ISP_PRO_YIQ_FLICKER_LINE_START,
847 enum isp_hue_property {
853 enum isp_nbpc_property {
858 /****************Tshark2****************************/
859 enum isp_raw_aem_property {
860 ISP_PRO_RAW_AEM_BLOCK,
861 ISP_PRO_RAW_AEM_BYPASS,
862 ISP_PRO_RAW_AEM_STATISTICS,
863 ISP_PRO_RAW_AEM_SKIP_NUM,
864 ISP_PRO_RAW_AEM_SHIFT,
865 ISP_PRO_RAW_AEM_OFFSET,
866 ISP_PRO_RAW_AEM_BLK_SIZE,
867 ISP_PRO_RAW_AEM_SLICE_SIZE,
870 enum isp_ct_property {
874 enum isp_csc_property {
876 ISP_PRO_CSC_PIC_SIZE,
879 enum isp_posterize_property {
880 ISP_PRO_POSTERIZE_BLOCK,
883 enum isp_yuv_precdn_property {
884 ISP_PRO_YUV_PRECDN_BLOCK,
887 enum isp_cdn_property {
888 ISP_PRO_YUV_CDN_BLOCK,
893 ISP_PRO_CDN_FILTER_BYPASS,
894 ISP_PRO_CDN_MEDIAN_WRITEBACK_EN,
895 ISP_PRO_CDN_MEDIAN_MODE,
896 ISP_PRO_CDN_GAUSSIAN_MODE,
897 ISP_PRO_CDN_MEDIAN_THR,
898 ISP_PRO_CDN_MEDIAN_THRUV,
903 enum isp_rgbg2_property {
904 ISP_PRO_RGB_GAIN2_BLOCK,
926 struct isp_aem_statistics {
927 uint32_t val[ISP_AEM_ITEM];
930 struct isp_raw_aem_statistics {
931 uint32_t r[ISP_RAW_AEM_ITEM];
932 uint32_t g[ISP_RAW_AEM_ITEM];
933 uint32_t b[ISP_RAW_AEM_ITEM];
936 struct isp_awbm_statistics {
937 uint32_t r[ISP_AWBM_ITEM];
938 uint32_t g[ISP_AWBM_ITEM];
939 uint32_t b[ISP_AWBM_ITEM];
942 struct isp_raw_awbm_statistics {
954 struct isp_awbc_rgb {
960 struct isp_bpc_common {
961 uint32_t pattern_type;
962 uint32_t detect_thrd;
963 uint32_t super_bad_thrd;
966 struct isp_bpc_thrd {
972 struct isp_grgb_thrd {
977 struct isp_cfa_thrd {
982 struct isp_cmc_matrix_tab {
983 uint16_t val[ISP_CMC_MATRIX_TAB_MAX];
987 struct isp_gamma_node {
988 uint32_t val[ISP_GAMMA_NODE_MAX];
991 struct isp_cce_matrix_tab {
992 uint16_t matrix[ISP_CCE_MATRIX_TAB_MAX];
996 struct isp_cce_shift {
1002 struct isp_cce_uvd {
1003 uint8_t uvd[ISP_CCE_UVD_NUM];
1007 struct isp_cce_uvc {
1008 uint8_t uvc0[ISP_CCE_UVC0_NUM];
1011 uint8_t uvc1[ISP_CCE_UVC1_NUM];
1015 struct isp_prefilter_thrd {
1021 struct isp_hist_ratio {
1023 uint32_t high_ratio;
1026 struct isp_hist_maxmin {
1033 struct isp_aca_maxmin {
1040 struct isp_aca_adjust {
1046 struct isp_img_coord {
1053 struct isp_afm_statistic {
1057 struct isp_edge_thrd {
1063 struct isp_css_thrd {
1064 uint8_t lower_thrd[ISP_CSS_LOWER_NUM];
1066 uint8_t lower_sum_thrd[ISP_CSS_LOWER_SUM_NUM];
1067 uint8_t chroma_thrd;
1070 struct isp_css_ratio {
1071 uint8_t ratio[ISP_CSS_RATIO_NUM];
1081 struct isp_scaling_ratio {
1086 struct isp_b4awb_phys {
1091 struct isp_hdr_rgb_index {
1097 struct isp_hdr_tab {
1098 uint8_t com[ISP_HDR_COMP_ITEM * 4];
1099 uint8_t p2e[ISP_HDR_P2E_ITEM * 4];
1100 uint8_t e2p[ISP_HDR_E2P_ITEM * 4];
1103 struct isp_nlc_r_node {
1104 uint16_t r_node[ISP_NLC_R_NODE_NUM];
1108 struct isp_nlc_g_node {
1109 uint16_t g_node[ISP_NLC_G_NODE_NUM];
1113 struct isp_nlc_b_node {
1114 uint16_t b_node[ISP_NLC_B_NODE_NUM];
1118 struct isp_nlc_l_node {
1119 uint16_t l_node[ISP_NLC_L_NODE_NUM];
1123 struct isp_bayer_mode {
1125 uint32_t awbc_bayer;
1126 uint32_t wave_bayer;
1128 uint32_t gain_bayer;
1131 struct isp_fetch_endian {
1133 uint32_t bit_recorder;
1136 struct isp_rgb_gain {
1142 struct isp_rgb_gain_offset {
1148 struct isp_ygamma_xnode {
1149 uint8_t x_node[ISP_YIQ_YGAMMA_XNODE_NUM];
1152 struct isp_ygamma_ynode {
1153 uint8_t y_node[ISP_YIQ_YGAMMA_YNODE_NUM];
1158 struct isp_ygamma_node_index {
1159 uint8_t node_index[ISP_YIQ_YGAMMA_NODE_INDEX_NUM];
1165 struct isp_dev_fetch_info {
1168 struct isp_addr addr;
1169 struct isp_pitch pitch;
1170 uint32_t mipi_word_num;
1171 uint32_t mipi_byte_rel_pos;
1174 struct isp_dev_blc_info {
1183 struct isp_dev_lsc_info {
1185 uint32_t grid_pitch;
1188 uint32_t buf_addr[2]; //compatible with 64bit cpu
1192 struct isp_dev_awb_info {
1194 uint32_t awbm_bypass;
1203 uint32_t awbc_bypass;
1215 struct isp_dev_bpc_info {
1220 uint32_t texture_thrd;
1224 struct isp_dev_wavelet_denoise_info {
1226 uint32_t diswei_level;
1227 uint32_t ranwei_level;
1230 struct isp_dev_grgb_info {
1236 struct isp_dev_cfa_info {
1241 struct isp_dev_cmc_info {
1243 uint16_t matrix[ISP_CMC_MATRIX_TAB_MAX];
1247 struct isp_dev_gamma_info {
1249 uint32_t node[ISP_GAMMA_NODE_MAX];
1252 struct isp_dev_cce_matrix_info {
1254 uint16_t matrix[ISP_CCE_MATRIX_TAB_MAX];
1261 struct isp_dev_cce_uv_info {
1264 uint8_t uvd[ISP_CCE_UVD_NUM];
1266 uint8_t uvc0[ISP_CCE_UVC0_NUM];
1269 uint8_t uvc1[ISP_CCE_UVC1_NUM];
1273 struct isp_dev_prefilter_info {
1281 struct isp_dev_hist_info {
1283 uint32_t auto_rst_disable;
1285 uint32_t low_sum_ratio;
1286 uint32_t high_sum_ratio;
1294 struct isp_dev_aca_info {
1302 uint32_t small_thrd;
1306 struct isp_dev_afm_info {
1311 uint32_t skip_num_clr;
1312 struct isp_img_coord win[ISP_AFM_WIN_NUM];
1315 struct isp_dev_edge_info {
1317 uint32_t detail_thrd;
1318 uint32_t smooth_thrd;
1322 struct isp_dev_emboss_info {
1327 struct isp_dev_fcs_info {
1332 struct isp_dev_css_info {
1334 uint8_t lower_thrd[ISP_CSS_LOWER_NUM];
1336 uint8_t lower_sum_thrd[ISP_CSS_LOWER_SUM_NUM];
1337 uint8_t chroma_thrd;
1338 uint8_t ratio[ISP_CSS_RATIO_NUM];
1341 struct isp_dev_csa_info {
1346 struct isp_dev_store_info {
1349 struct isp_addr addr;
1350 struct isp_pitch pitch;
1353 struct isp_dev_feeder_info {
1357 struct isp_dev_hdr_info {
1363 uint8_t com[ISP_HDR_COMP_ITEM * 4];
1364 uint8_t p2e[ISP_HDR_P2E_ITEM * 4];
1365 uint8_t e2p[ISP_HDR_E2P_ITEM * 4];
1368 struct isp_dev_nlc_info {
1370 uint16_t r_node[ISP_NLC_R_NODE_NUM];
1372 uint16_t g_node[ISP_NLC_G_NODE_NUM];
1374 uint16_t b_node[ISP_NLC_B_NODE_NUM];
1376 uint16_t l_node[ISP_NLC_L_NODE_NUM];
1380 struct isp_dev_nawbm_info {
1384 struct isp_dev_pre_wavelet_info {
1388 struct isp_dev_binning4awb_info {
1392 struct isp_dev_glb_gain_info {
1397 struct isp_dev_rgb_gain_info {
1407 struct isp_dev_yiq_ygamma_info {
1409 uint8_t x_node[ISP_YIQ_YGAMMA_XNODE_NUM];
1410 uint8_t y_node[ISP_YIQ_YGAMMA_YNODE_NUM];
1413 uint8_t node_index[ISP_YIQ_YGAMMA_NODE_INDEX_NUM];
1419 struct isp_dev_yiq_ae_info {
1426 struct isp_dev_yiq_flicker_info {
1430 uint32_t line_counter;
1432 uint32_t line_start;
1435 struct isp_dev_hue_info {
1440 struct isp_dev_nbpc_info {
1445 /*********************Tshark2**********************/
1446 #define ISP_PINGPANG_CTM_NUM 729
1447 #define ISP_CTM_PARAM_NUM (729 * 4)
1448 #define ISP_PINGPANG_HSV_NUM 361
1449 #define ISP_HSV_PARAM_NUM (361 * 2)
1450 #define ISP_PINGPANG_FRGB_GAMC_NUM 129
1451 #define ISP_PINGPANG_YUV_YGAMMA_NUM 129
1452 #define ISP_VST_IVST_NUM 1024
1453 #define ISP_AFM_WIN_NUM_V1 25
1455 enum isp_dev_capability {
1456 ISP_CAPABILITY_CHIP_ID,
1457 ISP_CAPABILITY_SINGLE_SIZE,
1458 ISP_CAPABILITY_CONTINE_SIZE,
1459 ISP_CAPABILITY_AWB_WIN,
1460 ISP_CAPABILITY_AWB_DEFAULT_GAIN,
1461 ISP_CAPABILITY_AF_MAX_WIN_NUM,
1464 enum isp_int_property {
1482 ISP_PRO_INT_ALL_DONE_CTRL,
1485 enum isp_dispatch_property {
1486 ISP_PRO_DISPATCH_BLOCK,
1487 ISP_PRO_DISPATCH_CH0_BAYER,
1488 ISP_PRO_DISPATCH_CH1_BAYER,
1489 ISP_PRO_DISPATCH_CH0_SIZE,
1490 ISP_PRO_DISPATCH_CH1_SIZE,
1493 enum isp_arbiter_property {
1494 ISP_PRO_ARBITER_BLOCK,
1495 ISP_PRO_ARBITER_WR_STATUS,
1496 ISP_PRO_ARBITER_RD_STATUS,
1497 ISP_PRO_ARBITER_PARAM,
1498 ISP_PRO_ARBITER_ENDIAN_CH0,
1499 ISP_PRO_ARBITER_ENDIAN_CH1,
1500 ISP_PRO_ARBITER_CTRL,
1503 enum isp_axi_property {
1505 ISP_PRO_AXI_WR_MASTER_STATUS,
1506 ISP_PRO_AXI_RD_MASTER_STATUS,
1507 ISP_PRO_AXI_ITI2AXIM_CTRL,
1508 ISP_PRO_AXI_CONVERT_WR_CTRL,
1511 enum isp_raw_sizer_property {
1512 ISP_PRO_RAW_SIZER_BLOCK,
1513 ISP_PRO_RAW_SIZER_BYPASS,
1514 ISP_PRO_RAW_SIZER_BPC_BYPASS,
1515 ISP_PRO_RAW_SIZER_CROP_BYPASS,
1516 ISP_PRO_RAW_SIZER_CROP_SRC,
1517 ISP_PRO_RAW_SIZER_CROP_DST,
1518 ISP_PRO_RAW_SIZER_CROP_START,
1519 ISP_PRO_RAW_SIZER_DST,
1520 ISP_PRO_RAW_SIZER_BPC_SHIFT,
1521 ISP_PRO_RAW_SIZER_BPC_MULTI,
1522 ISP_PRO_RAW_SIZER_BPC_MIN_DIFF,
1523 ISP_PRO_RAW_SIZER_HCOEFF,
1524 ISP_PRO_RAW_SIZER_VCOEFF,
1525 ISP_PRO_RAW_SIZER_H_INIT_PARA,
1526 ISP_PRO_RAW_SIZER_V_INIT_PARA,
1529 enum isp_common_property_v1 {
1530 ISP_PRO_COMMON_BLOCK,
1531 ISP_PRO_COMMON_VERSION,
1532 ISP_PRO_COMMON_STATUS0,
1533 ISP_PRO_COMMON_STATUS1,
1534 ISP_PRO_COMMON_CH0_FETCH_SEL,
1535 ISP_PRO_COMMON_CH0_SIZER_SEL,
1536 ISP_PRO_COMMON_CH0_STORE_SEL,
1537 ISP_PRO_COMMON_CH1_FETCH_SEL,
1538 ISP_PRO_COMMON_CH1_SIZER_SEL,
1539 ISP_PRO_COMMON_CH1_STORE_SEL,
1540 ISP_PRO_COMMON_FETCH_COLOR_SPACE_SEL,
1541 ISP_PRO_COMMON_STORE_COLOR_SPACE_SEL,
1542 ISP_PRO_COMMON_AWBM_POS_SEL,
1543 ISP_PRO_COMMON_CH0_AEM2_POS,
1544 ISP_PRO_COMMON_CH0_Y_AFM_POS,
1545 ISP_PRO_COMMON_CH1_AEM2_POS,
1546 ISP_PRO_COMMON_CH1_Y_AFM_POS,
1547 ISP_PRO_COMMON_LBUF_OFFSET,
1548 ISP_PRO_COMMON_SHADOW_ALL_CTRL,
1549 ISP_PRO_COMMON_AWBM_SHADOW,
1550 ISP_PRO_COMMON_AE_SHADOW,
1551 ISP_PRO_COMMON_AF_SHADOW,
1552 ISP_PRO_COMMON_AFL_SHADOW,
1553 ISP_PRO_COMMON_COMM_SHADOW,
1554 ISP_PRO_COMMON_3A_SINGLE_FRAME_CTRL,
1557 enum isp_pwd_property {
1559 ISP_PRO_PWD_SLICE_SIZE,
1562 enum isp_awbm_property {
1566 enum isp_awbc_property {
1570 enum isp_grgb_property_v1 {
1571 ISP_PRO_GRGB_BLOCK_v1,
1574 enum isp_nlm_property {
1580 enum isp_wdr_property {
1584 enum isp_cmc8_property {
1588 enum isp_hsv_property {
1592 enum isp_pre_cdn_rgb_property {
1593 ISP_PRO_PRE_CDN_RGB_BLOCK,
1596 enum isp_rgb_afm_property {
1597 ISP_PRO_RGB_AFM_BLOCK,
1598 ISP_PRO_RGB_AFM_FRAME_SIZE,
1599 ISP_PRO_RGB_AFM_TYPE1_STATISTIC,
1600 ISP_PRO_RGB_AFM_TYPE2_STATISTIC,
1601 ISP_PRO_RGB_AFM_BYPASS,
1602 ISP_PRO_RGB_AFM_MODE,
1603 ISP_PRO_RGB_AFM_SKIP_NUM,
1604 ISP_PRO_RGB_AFM_SKIP_NUM_CLR,
1605 ISP_PRO_RGB_AFM_SPSMD_RTGBOT_ENABLE,
1606 ISP_PRO_RGB_AFM_SPSMD_DIAGONAL_ENABLE,
1607 ISP_PRO_RGB_AFM_SPSMD_CAL_MOD,
1608 ISP_PRO_RGB_AFM_SEL_FILTER1,
1609 ISP_PRO_RGB_AFM_SEL_FILTER2,
1610 ISP_PRO_RGB_AFM_SOBEL_TYPE,
1611 ISP_PRO_RGB_AFM_SPSMD_TYPE,
1612 ISP_PRO_RGB_AFM_SOBEL_THRESHOLD,
1613 ISP_PRO_RGB_AFM_SPSMD_THRESHOLD,
1614 ISP_PRO_RGB_AFM_FRAME_RANGE,
1615 ISP_PRO_RGB_AFM_WIN,
1616 ISP_PRO_RGB_AFM_WIN_NUM,
1619 enum isp_rgb2y_property {
1620 ISP_PRO_RGB2Y_BLOCK,
1623 enum isp_yiq_aem_property {
1624 ISP_PRO_YIQ_AEM_BLOCK,
1625 ISP_PRO_YIQ_AEM_SLICE_SIZE,
1628 enum isp_anti_flicker_property {
1629 ISP_PRO_ANTI_FLICKER_BLOCK,
1630 ISP_PRO_ANTI_FLICKER_STATISTIC,
1631 ISP_PRO_ANTI_FLICKER_BYPASS,
1634 enum isp_yiq_afm_property {
1635 ISP_PRO_YIQ_AFM_BLOCK,
1636 ISP_PRO_YIQ_AFM_SLICE_SIZE,
1637 ISP_PRO_YIQ_AFM_WIN,
1638 ISP_PRO_YIQ_AFM_WIN_NUM,
1639 ISP_PRO_YIQ_AFM_STATISTIC,
1642 enum isp_prefilter_property_v1 {
1643 ISP_PRO_PREF_BLOCK_V1,
1646 enum isp_uv_prefilter_property {
1647 ISP_PRO_UV_PREFILTER_BLOCK,
1650 enum isp_hist2_property {
1651 ISP_PRO_HIST2_BLOCK,
1654 enum isp_iircnr_property {
1655 ISP_PRO_IIRCNR_BLOCK,
1656 ISP_PRO_YRANDOM_BLOCK,
1659 enum isp_post_cdn_property {
1660 ISP_PRO_POST_CDN_BLOCK,
1663 enum isp_ygamma_property {
1664 ISP_PRO_YGAMMA_BLOCK,
1667 enum isp_ydelay_property {
1668 ISP_PRO_YDELAY_BLOCK,
1671 enum isp_yuv_nlm_property {
1672 ISP_PRO_YUV_NLM_BLOCK,
1673 ISP_PRO_YUV_NLM_SLICE_SIZE,
1676 enum isp_pingpang_property {
1677 ISP_PRO_PINGPANG_CTM_BLOCK,
1678 ISP_PRO_PINGPANG_HSV_BLOCK,
1679 ISP_PRO_PINGPANG_FRGB_GAMC_BLOCK,
1687 struct isp_reg_bits {
1688 unsigned long reg_addr;
1689 unsigned long reg_value;
1692 struct isp_reg_param {
1693 unsigned long reg_param;
1706 struct isp_interrupt {
1711 struct isp_capability {
1714 void * property_param;
1717 struct isp_io_param {
1721 void * property_param;
1724 struct isp_img_offset {
1729 struct isp_img_size {
1739 struct isp_lsc_addr {
1747 uint16_t r_node[29];
1749 uint16_t g_node[29];
1751 uint16_t b_node[29];
1753 uint16_t l_node[27];
1758 struct awbm_rect_pos {
1759 uint32_t start_x[5];
1760 uint32_t start_y[5];
1765 struct awbm_circle_pos {
1771 struct awbm_pixel_num {
1772 uint32_t pixel_num[5];
1818 //*cmc8 and cmc10*//
1824 struct coordinate_xy {
1829 struct csa_factor_v1 {
1834 struct isp_raw_afm_statistic {
1835 uint32_t val[ISP_RAW_AFM_ITEM];
1838 struct isp_yiq_afm_statistic {
1839 uint32_t val[ISP_YIQ_AFM_ITEM];
1842 struct arbiter_endian_v1 {
1843 uint32_t bpc_endian;
1844 uint32_t lens_endian;
1845 uint32_t store_endian;
1846 uint32_t fetch_bit_reorder;
1847 uint32_t fetch_endian;
1850 struct arbiter_param_v1 {
1851 uint32_t pause_cycle;
1856 struct isp_dev_pre_glb_gain_info {
1861 struct isp_dev_rgb_gain_info_v1 {
1863 uint32_t global_gain;
1869 struct isp_dev_pre_wavelet_info_v1 {
1871 uint32_t radial_bypass;
1872 uint32_t gain_thrs0;
1873 uint32_t gain_thrs1;
1879 uint32_t center_pos_x;
1880 uint32_t center_pos_y;
1887 uint32_t gain_max_thr;
1890 uint32_t lum_shink_level;
1893 struct isp_dev_nlc_info_v1 {
1895 struct nlc_node node;
1898 struct isp_dev_2d_lsc_info {
1901 uint32_t grid_address;
1904 uint32_t loader_enable;
1905 uint32_t grid_pitch;
1906 uint32_t grid_width;
1907 uint32_t grid_x_num;
1908 uint32_t grid_y_num;
1909 uint32_t grid_num_t;
1910 uint32_t load_buf_sel;
1911 uint32_t load_chn_sel;
1913 struct isp_img_size slice_size;
1914 uint32_t relative_x;
1915 uint32_t relative_y;
1916 uint32_t q_value[2][5];
1917 uint32_t buf_addr[2]; //compatible with 64bit cpu
1921 struct isp_dev_1d_lsc_info {
1923 uint32_t gain_max_thr;
1924 uint32_t center_r0c0_row_y;
1925 uint32_t center_r0c0_col_x;
1926 uint32_t center_r0c1_row_y;
1927 uint32_t center_r0c1_col_x;
1928 uint32_t center_r1c0_row_y;
1929 uint32_t center_r1c0_col_x;
1930 uint32_t center_r1c1_row_y;
1931 uint32_t center_r1c1_col_x;
1932 uint32_t delta_square_r0c0_x;
1933 uint32_t delta_square_r0c0_y;
1934 uint32_t delta_square_r0c1_x;
1935 uint32_t delta_square_r0c1_y;
1936 uint32_t delta_square_r1c0_x;
1937 uint32_t delta_square_r1c0_y;
1938 uint32_t delta_square_r1c1_x;
1939 uint32_t delta_square_r1c1_y;
1940 uint32_t coef_r0c0_p1;
1941 uint32_t coef_r0c0_p2;
1942 uint32_t coef_r0c1_p1;
1943 uint32_t coef_r0c1_p2;
1944 uint32_t coef_r1c0_p1;
1945 uint32_t coef_r1c0_p2;
1946 uint32_t coef_r1c1_p1;
1947 uint32_t coef_r1c1_p2;
1948 struct img_offset start_pos;
1951 struct isp_dev_binning4awb_info_v1 {
1954 uint32_t burst_mode;
1956 uint32_t mem_fifo_clr;
1962 struct isp_dev_awbm_info_v1 {
1966 struct img_offset block_offset;
1967 struct isp_img_size block_size;
1969 uint32_t thr_bypass;
1970 struct awbm_rect_pos rect_pos;
1971 struct awbm_circle_pos circle_pos;
1972 struct awbm_rect_pos clctor_pos;
1973 struct awbm_pixel_num pix_num;
1974 struct awbm_thr thr;
1975 struct isp_img_size slice_size;
1976 uint32_t skip_num_clear;
1980 struct isp_dev_awbc_info_v1 {
1982 uint32_t alpha_bypass;
1983 uint32_t alpha_value;
1985 struct awbc_param gain;
1986 struct awbc_rgb thrd;
1987 struct awbc_param gain_offset;
1988 struct awbc_param gain_buff;
1989 struct awbc_param gain_offset_buff;
1992 struct isp_dev_awb_info_v1 {
1994 uint32_t awbm_bypass;
1997 struct img_offset block_offset;
1998 struct isp_img_size block_size;
2000 uint32_t thr_bypass;
2001 struct awbm_rect_pos rect_pos;
2002 struct awbm_circle_pos circle_pos;
2003 struct awbm_rect_pos clctor_pos;
2004 struct awbm_pixel_num pix_num;
2005 struct awbm_thr thr;
2006 struct isp_img_size slice_size;
2007 uint32_t skip_num_clear;
2010 uint32_t awbc_bypass;
2011 uint32_t alpha_bypass;
2012 uint32_t alpha_value;
2014 struct awbc_param gain;
2015 struct awbc_rgb thrd;
2016 struct awbc_param gain_offset;
2017 struct awbc_param gain_buff;
2018 struct awbc_param gain_offset_buff;
2021 struct isp_dev_awb_info_v2 {
2023 uint32_t awbm_bypass;
2026 struct img_offset block_offset;
2027 struct isp_img_size block_size;
2029 uint32_t thr_bypass;
2030 struct awbm_rect_pos rect_pos;
2031 struct awbm_circle_pos circle_pos;
2032 struct awbm_rect_pos clctor_pos;
2033 struct awbm_pixel_num pix_num;
2034 struct awbm_thr thr;
2035 struct isp_img_size slice_size;
2036 uint32_t skip_num_clear;
2037 uint32_t position_sel;
2040 uint32_t awbc_bypass;
2041 uint32_t alpha_bypass;
2042 uint32_t alpha_value;
2044 struct awbc_param gain;
2045 struct awbc_rgb thrd;
2046 struct awbc_param gain_offset;
2047 struct awbc_param gain_buff;
2048 struct awbc_param gain_offset_buff;
2052 struct isp_dev_raw_aem_info {
2058 struct isp_dev_bpc_info_v1 {
2060 uint32_t pvd_bypass;
2065 uint32_t cntr_threshold;
2066 uint32_t bad_map_hw_fifo_clr_en;
2068 uint32_t bpc_map_fifo_clr;
2070 uint32_t bad_pixel_num;
2071 uint32_t flat_factor;
2072 uint32_t safe_factor;
2073 uint32_t spike_coeff;
2074 uint32_t dead_coeff;
2075 uint16_t intercept_b[8];
2076 uint16_t slope_k[8];
2077 uint16_t lut_level[8];
2078 uint32_t new_old_sel;
2079 uint32_t map_done_sel;
2080 uint32_t bpc_map_addr_new;
2084 struct isp_dev_bdn_info_v1 {
2086 uint32_t radial_bypass;
2088 uint32_t dis[10][2];
2089 uint32_t ran[10][8];
2096 uint32_t start_pos_x;
2097 uint32_t start_pos_y;
2103 struct isp_dev_grgb_info_v1 {
2110 struct isp_dev_rgb_gain2_info {
2120 struct isp_dev_vst_info_v1 {
2125 struct isp_dev_nlm_info_v1 {
2127 uint32_t imp_opt_bypass;
2128 uint32_t flat_opt_bypass;
2129 uint32_t flat_thr_bypass;
2130 uint32_t direction_mode_bypass;
2132 uint8_t strength[5];
2136 uint32_t texture_dec;
2144 uint32_t tdist_min_th;
2148 uint32_t vst_addr[2]; //compatible with 64bit cpu
2151 uint32_t ivst_addr[2]; //compatible with 64bit cpu
2154 uint32_t nlm_addr[2]; //compatible with 64bit cpu
2156 uint32_t strength_level;
2159 struct isp_dev_nlm_info_v2 {
2161 uint32_t imp_opt_bypass;
2162 uint32_t flat_opt_bypass;
2163 // uint32_t flat_thr_bypass;
2164 // uint32_t direction_mode_bypass;
2166 uint8_t strength[5];
2170 uint32_t texture_dec;
2173 // uint32_t opt_mode;
2174 // uint32_t dist_mode;
2175 // uint32_t w_shift[3];
2177 // uint32_t tdist_min_th;
2178 // uint32_t diff_th;
2180 uint32_t vst_addr[2]; //compatible with 64bit cpu
2182 uint32_t ivst_addr[2]; //compatible with 64bit cpu
2184 uint32_t nlm_addr[2]; //compatible with 64bit cpu
2186 uint32_t strength_level;
2191 struct isp_dev_ivst_info_v1 {
2196 struct isp_dev_cfa_info_v1 {
2200 uint32_t gbuf_addr_max;
2203 uint32_t cfa_uni_dir_intplt_tr ;
2204 uint32_t cfai_ee_uni_dir_tr;
2205 uint32_t cfai_ee_edge_tr;
2206 uint32_t cfai_ee_diagonal_tr;
2207 uint32_t cfai_ee_grid_tr;
2208 uint32_t cfai_doee_clip_tr;
2209 uint32_t cfai_ee_saturation_level;
2210 uint32_t plt_diff_tr;
2211 uint32_t grid_min_tr ;
2212 uint32_t strength_tr_neg;
2213 uint32_t strength_tr_pos;
2214 uint32_t ee_strength_neg;
2215 uint32_t ee_strength_pos;
2216 uint32_t inter_chl_gain;
2219 struct isp_dev_cmc10_info {
2223 uint32_t alpha_bypass;
2224 struct cmc_matrix matrix;
2225 struct cmc_matrix matrix_buf;
2228 struct isp_dev_gamma_info_v1 {
2230 struct coordinate_xy nodes[ISP_PINGPANG_FRGB_GAMC_NUM];
2233 struct isp_dev_cmc8_info_v1 {
2237 uint32_t alpha_bypass;
2238 struct cmc_matrix matrix;
2239 struct cmc_matrix matrix_buf;
2242 struct isp_dev_ct_info {
2245 uint32_t data_ptr[2]; //compatible with 64bit cpu
2249 struct isp_dev_cce_info_v1 {
2259 struct isp_dev_cce_uvd_info {
2260 uint32_t uvdiv_bypass;
2261 uint32_t lum_th_h_len;
2263 uint32_t lum_th_l_len;
2265 uint32_t chroma_min_h;
2266 uint32_t chroma_min_l;
2267 uint32_t chroma_max_h;
2268 uint32_t chroma_max_l;
2278 uint8_t reserved[3];
2283 struct isp_dev_hsv_info_v1 {
2287 uint32_t data_ptr[2]; //compatible with 64bit cpu
2291 struct isp_dev_csc_info {
2293 uint32_t red_centre_x;
2294 uint32_t red_centre_y;
2295 uint32_t blue_centre_x;
2296 uint32_t blue_centre_y;
2297 uint32_t red_x2_init;
2298 uint32_t red_y2_init;
2299 uint32_t blue_x2_init;
2300 uint32_t blue_y2_init;
2301 uint32_t red_threshold;
2302 uint32_t blue_threshold;
2303 uint32_t red_p1_param;
2304 uint32_t red_p2_param;
2305 uint32_t blue_p1_param;
2306 uint32_t blue_p2_param;
2307 uint32_t max_gain_thr;
2308 struct isp_img_size img_size;
2309 struct img_offset start_pos;
2312 struct isp_dev_pre_cdn_rgb_info {
2314 uint32_t median_mode;
2315 uint32_t median_thr;
2323 struct isp_dev_posterize_info {
2325 uint8_t posterize_level_bottom[8];
2326 uint8_t posterize_level_top[8];
2327 uint8_t posterize_level_out[8];
2330 struct isp_dev_rgb_afm_info_v1 {
2334 uint32_t skip_num_clear;
2335 uint32_t spsmd_rtgbot_enable;
2336 uint32_t spsmd_diagonal_enable;
2337 uint32_t spsmd_cal_mode;
2338 uint32_t af_sel_filter1;
2339 uint32_t af_sel_filter2;
2340 uint32_t sobel_type;
2341 uint32_t spsmd_type;
2342 uint32_t sobel_threshold_min;
2343 uint32_t sobel_threshold_max;
2344 uint32_t spsmd_threshold_min;
2345 uint32_t spsmd_threshold_max;
2346 uint32_t frame_width;
2347 uint32_t frame_height;
2348 struct isp_coord coord[ISP_AFM_WIN_NUM_V1];
2351 struct isp_dev_rgb2y_info {
2352 uint32_t signal_sel;
2355 struct isp_dev_yiq_aem_info_v1 {
2356 uint32_t ygamma_bypass;
2357 int16_t gamma_xnode[10];
2358 int16_t gamma_ynode[10];
2359 uint32_t gamma_node_idx[10];
2360 uint32_t aem_bypass;
2362 uint32_t aem_skip_num;
2369 struct isp_dev_yiq_aem_info_v2 {
2370 uint32_t ygamma_bypass;
2371 uint32_t gamma_xnode[10];
2372 uint32_t gamma_ynode[10];
2373 uint32_t gamma_node_idx[10];
2374 uint32_t aem_bypass;
2376 uint32_t aem_skip_num;
2385 struct isp_dev_anti_flicker_info_v1 {
2388 uint32_t skip_frame_num;
2397 struct isp_dev_yiq_afm_info_v1 {
2400 uint32_t source_pos;
2403 uint32_t skip_num_clear;
2405 uint32_t iir_bypass;
2406 struct isp_coord coord[25];
2411 struct isp_dev_yiq_afm_info_v2 {
2416 uint32_t skip_num_clear;
2417 uint32_t af_position;
2419 uint32_t iir_bypass;
2420 struct isp_coord coord[25];
2425 struct isp_dev_yuv_precdn_info {
2428 uint32_t median_writeback_en;
2429 uint32_t median_mode;
2432 uint8_t median_thr_u[2];
2433 uint8_t median_thr_v[2];
2434 uint32_t median_thr;
2437 uint8_t r_segu[2][7];
2438 uint8_t r_segv[2][7];
2439 uint8_t r_segy[2][7];
2440 uint8_t r_distw[25];
2445 struct isp_dev_prefilter_info_v1 {
2451 struct isp_dev_uv_prefilter_info {
2458 struct isp_dev_brightness_info {
2463 struct isp_dev_contrast_info {
2468 struct isp_dev_hist_info_v1 {
2471 uint32_t buf_rst_en;
2472 uint32_t pof_rst_en;//pike have no this bit
2474 uint32_t skip_num_clr;
2477 uint32_t high_ratio;
2483 struct isp_dev_hist2_info_v1 {
2485 uint32_t en;//pike has no this bit
2487 uint32_t skip_num_clr;
2489 int32_t hist_roi_x_s[4];
2490 int32_t hist_roi_y_s[4];
2491 uint32_t hist_roi_x_e[4];
2492 uint32_t hist_roi_y_e[4];
2495 struct isp_dev_autocont_info_v1 {
2504 struct isp_dev_yuv_cdn_info {
2506 uint32_t filter_bypass;
2507 uint32_t median_writeback_en;
2508 uint32_t median_mode;
2509 uint32_t gaussian_mode;
2510 uint32_t median_thr;
2511 uint32_t median_thru0;
2512 uint32_t median_thru1;
2513 uint32_t median_thrv0;
2514 uint32_t median_thrv1;
2515 uint32_t rangewu[31];
2516 uint32_t rangewv[31];
2520 struct isp_dev_edge_info_v1 {
2523 uint32_t ee_str_m_n;
2524 uint32_t ee_str_m_p;
2525 uint32_t ee_str_d_n;
2526 uint32_t ee_str_d_p;
2529 uint32_t ee_incr_d_n;
2530 uint32_t ee_incr_d_p;
2531 uint32_t ee_thr_d_n;
2532 uint32_t ee_thr_d_p;
2534 uint32_t ee_flat_thr_1;
2535 uint32_t ee_flat_thr_2;
2536 uint32_t ee_incr_m_n;
2537 uint32_t ee_incr_m_p;
2539 uint32_t ee_txt_thr_1;
2540 uint32_t ee_txt_thr_2;
2541 uint32_t ee_txt_thr_3;
2543 uint32_t ee_corner_sm_n;
2544 uint32_t ee_corner_sm_p;
2545 uint32_t ee_corner_gain_n;
2546 uint32_t ee_corner_gain_p;
2547 uint32_t ee_corner_th_n;
2548 uint32_t ee_corner_th_p;
2549 uint32_t ee_corner_cor;
2551 uint32_t ee_smooth_strength;
2552 uint32_t ee_smooth_thr;
2554 uint32_t ee_flat_smooth_mode;
2555 uint32_t ee_edge_smooth_mode;
2557 uint32_t ee_incr_b_n;
2558 uint32_t ee_incr_b_p;
2559 uint32_t ee_str_b_n;
2560 uint32_t ee_str_b_p;
2564 uint32_t ipd_flat_thr;
2565 uint32_t ipd_bypass;
2566 uint32_t ee_clip_after_smooth_en;
2568 //pike has no ADP_CFG0 ADP_CFG1 ADP_CFG2 registers
2575 uint32_t ee_cv_clip_n;
2576 uint32_t ee_cv_clip_p;
2585 struct isp_dev_css_info_v1 {
2587 uint32_t lh_chrom_th;
2588 uint8_t chrom_lower_th[7];
2590 uint8_t chrom_high_th[7];
2592 uint32_t lum_low_shift;
2593 uint32_t lum_hig_shift;
2594 uint8_t lh_ratio[8];
2596 uint32_t lum_low_th;
2598 uint32_t lum_hig_th;
2611 struct isp_dev_csa_info_v1 {
2615 struct csa_factor_v1 factor;
2618 struct isp_dev_hue_info_v1 {
2623 struct isp_dev_post_cdn_info {
2625 uint32_t downsample_bypass;
2627 uint32_t writeback_en;
2629 uint32_t median_mode;
2630 uint32_t adapt_med_thr;
2637 uint8_t r_segu[2][7];
2638 uint8_t r_segv[2][7];
2639 uint8_t r_distw[15][5];
2641 uint32_t start_row_mod4;
2645 struct isp_dev_emboss_info_v1 {
2652 struct isp_dev_ygamma_info {
2655 struct coordinate_xy nodes[ISP_PINGPANG_YUV_YGAMC_NUM];
2658 struct isp_dev_ydelay_info {
2662 struct isp_dev_yuv_nlm_info {
2663 uint32_t nlm_bypass;
2664 uint32_t nlm_radial_bypass;
2665 uint32_t nlm_adaptive_bypass;
2666 uint32_t nlm_vst_bypass;
2667 uint32_t edge_str_req[7];
2668 uint32_t edge_str_cmp[7];
2669 uint32_t edge_range_l;
2670 uint32_t edge_range_h;
2671 uint32_t edge_time_str;
2673 uint32_t den_strength;
2686 uint32_t lut_vs[64];
2689 struct isp_dev_iircnr_info_v1 {
2696 uint32_t uv_low_thr2;
2697 uint32_t uv_low_thr1;
2699 uint32_t alpha_low_u;
2700 uint32_t alpha_low_v;
2701 uint32_t uv_high_thr2;
2706 uint32_t iirnr_level;
2709 struct isp_dev_yrandom_info_v1 {
2716 uint32_t takeBit[8];
2719 struct isp_dev_fetch_info_v1 {
2722 uint32_t color_format;
2723 // struct isp_img_size slice_size;
2724 struct isp_addr addr;
2725 struct isp_pitch pitch;
2726 uint32_t mipi_word_num;
2727 uint32_t mipi_byte_rel_pos;
2730 struct isp_dev_store_info_v1 {
2733 uint32_t color_format;
2734 // struct isp_img_size size;
2735 struct isp_addr addr;
2736 struct isp_pitch pitch;
2739 struct isp_dev_dispatch_info_v1 {
2744 struct isp_dev_arbiter_info_v1 {
2745 struct arbiter_endian_v1 endian_ch0;
2746 struct arbiter_endian_v1 endian_ch1;
2747 struct arbiter_param_v1 para;
2750 struct isp_dev_axi_info_v1 {
2751 uint32_t iti2axim_ctrl;
2752 uint32_t convert_wr_ctrl;
2755 struct isp_raw_sizer_init_para {
2756 uint32_t half_dst_wd_remain;
2757 uint32_t residual_half_wd;
2758 uint32_t adv_b_init_residual;
2759 uint32_t adv_a_init_residual;
2760 uint32_t offset_incr_init_b;
2761 uint32_t offset_incr_init_a;
2762 uint32_t offset_base_incr;
2765 struct isp_common_lbuf_param_v1 {
2766 uint32_t cfae_lbuf_offset;
2767 uint32_t comm_lbuf_offset;
2768 uint32_t ydly_lbuf_offset;
2769 uint32_t awbm_lbuf_offset;
2772 struct isp_dev_common_info_v1 {
2773 uint32_t fetch_sel_0;
2774 uint32_t sizer_sel_0;
2775 uint32_t store_sel_0;
2776 uint32_t fetch_sel_1;
2777 uint32_t sizer_sel_1;
2778 uint32_t store_sel_1;
2779 uint32_t fetch_color_format;
2780 uint32_t store_color_format;
2782 uint32_t y_afm_pos_0;
2783 uint32_t y_aem_pos_0;
2784 uint32_t y_afm_pos_1;
2785 uint32_t y_aem_pos_1;
2786 struct isp_common_lbuf_param_v1 lbuf_off;
2789 struct isp_dev_common_info_v2 {
2790 uint32_t fetch_sel_0;
2791 uint32_t sizer_sel_0;
2792 uint32_t store_sel_0;
2793 uint32_t fetch_sel_1;
2794 uint32_t sizer_sel_1;
2795 uint32_t store_sel_1;
2796 uint32_t fetch_color_format;
2797 uint32_t store_color_format;
2799 uint32_t y_afm_pos_0;
2800 uint32_t y_aem_pos_0;
2801 uint32_t y_afm_pos_1;
2802 uint32_t y_aem_pos_1;
2807 struct isp_dev_pingpang_ctm_info_v1 {
2811 struct isp_dev_pingpang_hsv_info_v1 {
2816 struct isp_dev_pingpang_frgb_gamc_info_v1 {
2822 #define ISP_IO_MAGIC 'R'
2823 #define ISP_IO_CAPABILITY _IOR(ISP_IO_MAGIC, 0, struct isp_capability)
2824 #define ISP_IO_IRQ _IOR(ISP_IO_MAGIC, 1, struct isp_irq)
2825 #define ISP_IO_READ _IOR(ISP_IO_MAGIC, 2, struct isp_reg_param)
2826 #define ISP_IO_WRITE _IOW(ISP_IO_MAGIC, 3, struct isp_reg_param)
2827 #define ISP_IO_RST _IOW(ISP_IO_MAGIC, 4, uint32_t)
2828 #define ISP_IO_STOP _IOW(ISP_IO_MAGIC, 5, uint32_t)
2829 #define ISP_IO_INT _IOW(ISP_IO_MAGIC, 6, uint32_t)
2830 #define ISP_IO_CFG_PARAM _IOWR(ISP_IO_MAGIC, 7, struct isp_io_param)
2831 #define ISP_REG_READ _IOR(ISP_IO_MAGIC, 8, struct isp_reg_bits)