1 /* SPDX-License-Identifier: GPL-2.0 */
3 * (C) Copyright 2019 Xilinx, Inc,
4 * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
12 #define VERSAL_PM_LOAD_PDI 0x701
13 #define VERSAL_PM_PDI_TYPE 0xF
15 extern struct xilinx_fpga_op versal_op;
17 #define XILINX_VERSAL_DESC \
18 { xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
20 #endif /* _VERSALPL_H_ */