1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
8 * Santosh Yaraganavi <santosh.sy@samsung.com>
9 * Vinayak Holikatti <h.vinayak@samsung.com>
15 #include <linux/bitfield.h>
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
18 #include <linux/devfreq.h>
19 #include <linux/msi.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/dma-direction.h>
22 #include <scsi/scsi_device.h>
23 #include <ufs/unipro.h>
25 #include <ufs/ufs_quirks.h>
26 #include <ufs/ufshci.h>
28 #define UFSHCD "ufshcd"
33 DEV_CMD_TYPE_NOP = 0x0,
34 DEV_CMD_TYPE_QUERY = 0x1,
35 DEV_CMD_TYPE_RPMB = 0x2,
39 /* uic specific errors */
47 UFS_EVT_AUTO_HIBERN8_ERR,
49 UFS_EVT_LINK_STARTUP_FAIL,
64 * struct uic_command - UIC command structure
65 * @command: UIC command
66 * @argument1: UIC command argument 1
67 * @argument2: UIC command argument 2
68 * @argument3: UIC command argument 3
69 * @cmd_active: Indicate if UIC command is outstanding
70 * @done: UIC command completion
78 struct completion done;
81 /* Used to differentiate the power management options */
88 /* Host <-> Device UniPro Link state */
90 UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
91 UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
92 UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
93 UIC_LINK_BROKEN_STATE = 3, /* Link is in broken state */
96 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
97 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
98 UIC_LINK_ACTIVE_STATE)
99 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
100 UIC_LINK_HIBERN8_STATE)
101 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
102 UIC_LINK_BROKEN_STATE)
103 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
104 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
105 UIC_LINK_ACTIVE_STATE)
106 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
107 UIC_LINK_HIBERN8_STATE)
108 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
109 UIC_LINK_BROKEN_STATE)
111 #define ufshcd_set_ufs_dev_active(h) \
112 ((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
113 #define ufshcd_set_ufs_dev_sleep(h) \
114 ((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
115 #define ufshcd_set_ufs_dev_poweroff(h) \
116 ((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
117 #define ufshcd_set_ufs_dev_deepsleep(h) \
118 ((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
119 #define ufshcd_is_ufs_dev_active(h) \
120 ((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
121 #define ufshcd_is_ufs_dev_sleep(h) \
122 ((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
123 #define ufshcd_is_ufs_dev_poweroff(h) \
124 ((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
125 #define ufshcd_is_ufs_dev_deepsleep(h) \
126 ((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
129 * UFS Power management levels.
130 * Each level is in increasing order of power savings, except DeepSleep
131 * which is lower than PowerDown with power on but not PowerDown with
145 struct ufs_pm_lvl_states {
146 enum ufs_dev_pwr_mode dev_state;
147 enum uic_link_state link_state;
151 * struct ufshcd_lrb - local reference block
152 * @utr_descriptor_ptr: UTRD address of the command
153 * @ucd_req_ptr: UCD address of the command
154 * @ucd_rsp_ptr: Response UPIU address for this command
155 * @ucd_prdt_ptr: PRDT address of the command
156 * @utrd_dma_addr: UTRD dma address for debug
157 * @ucd_prdt_dma_addr: PRDT dma address for debug
158 * @ucd_rsp_dma_addr: UPIU response dma address for debug
159 * @ucd_req_dma_addr: UPIU request dma address for debug
160 * @cmd: pointer to SCSI command
161 * @scsi_status: SCSI status of the command
162 * @command_type: SCSI, UFS, Query.
163 * @task_tag: Task tag of the command
164 * @lun: LUN of the command
165 * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
166 * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
167 * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
168 * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
169 * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
170 * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
171 * @data_unit_num: the data unit number for the first block for inline crypto
172 * @req_abort_skip: skip request abort task flag
175 struct utp_transfer_req_desc *utr_descriptor_ptr;
176 struct utp_upiu_req *ucd_req_ptr;
177 struct utp_upiu_rsp *ucd_rsp_ptr;
178 struct ufshcd_sg_entry *ucd_prdt_ptr;
180 dma_addr_t utrd_dma_addr;
181 dma_addr_t ucd_req_dma_addr;
182 dma_addr_t ucd_rsp_dma_addr;
183 dma_addr_t ucd_prdt_dma_addr;
185 struct scsi_cmnd *cmd;
190 u8 lun; /* UPIU LUN id field is only 8-bit wide */
192 ktime_t issue_time_stamp;
193 u64 issue_time_stamp_local_clock;
194 ktime_t compl_time_stamp;
195 u64 compl_time_stamp_local_clock;
196 #ifdef CONFIG_SCSI_UFS_CRYPTO
205 * struct ufs_query - holds relevant data structures for query request
206 * @request: request upiu and function
207 * @descriptor: buffer for sending/receiving descriptor
208 * @response: response upiu and response
211 struct ufs_query_req request;
213 struct ufs_query_res response;
217 * struct ufs_dev_cmd - all assosiated fields with device management commands
218 * @type: device management command type - Query, NOP OUT
219 * @lock: lock to allow one command at a time
220 * @complete: internal commands completion
221 * @query: Device management query information
224 enum dev_cmd_type type;
226 struct completion *complete;
227 struct ufs_query query;
231 * struct ufs_clk_info - UFS clock related info
232 * @list: list headed by hba->clk_list_head
235 * @max_freq: maximum frequency supported by the clock
236 * @min_freq: min frequency that can be used for clock scaling
237 * @curr_freq: indicates the current frequency that it is set to
238 * @keep_link_active: indicates that the clk should not be disabled if
240 * @enabled: variable to check against multiple enable/disable
242 struct ufs_clk_info {
243 struct list_head list;
249 bool keep_link_active;
253 enum ufs_notify_change_status {
258 struct ufs_pa_layer_attr {
268 struct ufs_pwr_mode_info {
270 struct ufs_pa_layer_attr info;
274 * struct ufs_hba_variant_ops - variant specific callbacks
275 * @name: variant name
276 * @init: called when the driver is initialized
277 * @exit: called to cleanup everything done in init
278 * @get_ufs_hci_version: called to get UFS HCI version
279 * @clk_scale_notify: notifies that clks are scaled up/down
280 * @setup_clocks: called before touching any of the controller registers
281 * @hce_enable_notify: called before and after HCE enable bit is set to allow
282 * variant specific Uni-Pro initialization.
283 * @link_startup_notify: called before and after Link startup is carried out
284 * to allow variant specific Uni-Pro initialization.
285 * @pwr_change_notify: called before and after a power mode change
286 * is carried out to allow vendor spesific capabilities
288 * @setup_xfer_req: called before any transfer request is issued
290 * @setup_task_mgmt: called before any task management request is issued
292 * @hibern8_notify: called around hibern8 enter/exit
293 * @apply_dev_quirks: called to apply device specific quirks
294 * @fixup_dev_quirks: called to modify device specific quirks
295 * @suspend: called during host controller PM callback
296 * @resume: called during host controller PM callback
297 * @dbg_register_dump: used to dump controller debug information
298 * @phy_initialization: used to initialize phys
299 * @device_reset: called to issue a reset pulse on the UFS device
300 * @config_scaling_param: called to configure clock scaling parameters
301 * @program_key: program or evict an inline encryption key
302 * @event_notify: called to notify important events
303 * @reinit_notify: called to notify reinit of UFSHCD during max gear switch
304 * @mcq_config_resource: called to configure MCQ platform resources
305 * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode
306 * @op_runtime_config: called to config Operation and runtime regs Pointers
307 * @get_outstanding_cqs: called to get outstanding completion queues
308 * @config_esi: called to config Event Specific Interrupt
310 struct ufs_hba_variant_ops {
312 int (*init)(struct ufs_hba *);
313 void (*exit)(struct ufs_hba *);
314 u32 (*get_ufs_hci_version)(struct ufs_hba *);
315 int (*clk_scale_notify)(struct ufs_hba *, bool,
316 enum ufs_notify_change_status);
317 int (*setup_clocks)(struct ufs_hba *, bool,
318 enum ufs_notify_change_status);
319 int (*hce_enable_notify)(struct ufs_hba *,
320 enum ufs_notify_change_status);
321 int (*link_startup_notify)(struct ufs_hba *,
322 enum ufs_notify_change_status);
323 int (*pwr_change_notify)(struct ufs_hba *,
324 enum ufs_notify_change_status status,
325 struct ufs_pa_layer_attr *,
326 struct ufs_pa_layer_attr *);
327 void (*setup_xfer_req)(struct ufs_hba *hba, int tag,
329 void (*setup_task_mgmt)(struct ufs_hba *, int, u8);
330 void (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
331 enum ufs_notify_change_status);
332 int (*apply_dev_quirks)(struct ufs_hba *hba);
333 void (*fixup_dev_quirks)(struct ufs_hba *hba);
334 int (*suspend)(struct ufs_hba *, enum ufs_pm_op,
335 enum ufs_notify_change_status);
336 int (*resume)(struct ufs_hba *, enum ufs_pm_op);
337 void (*dbg_register_dump)(struct ufs_hba *hba);
338 int (*phy_initialization)(struct ufs_hba *);
339 int (*device_reset)(struct ufs_hba *hba);
340 void (*config_scaling_param)(struct ufs_hba *hba,
341 struct devfreq_dev_profile *profile,
342 struct devfreq_simple_ondemand_data *data);
343 int (*program_key)(struct ufs_hba *hba,
344 const union ufs_crypto_cfg_entry *cfg, int slot);
345 void (*event_notify)(struct ufs_hba *hba,
346 enum ufs_event_type evt, void *data);
347 void (*reinit_notify)(struct ufs_hba *);
348 int (*mcq_config_resource)(struct ufs_hba *hba);
349 int (*get_hba_mac)(struct ufs_hba *hba);
350 int (*op_runtime_config)(struct ufs_hba *hba);
351 int (*get_outstanding_cqs)(struct ufs_hba *hba,
352 unsigned long *ocqs);
353 int (*config_esi)(struct ufs_hba *hba);
356 /* clock gating state */
357 enum clk_gating_state {
365 * struct ufs_clk_gating - UFS clock gating related info
366 * @gate_work: worker to turn off clocks after some delay as specified in
368 * @ungate_work: worker to turn on clocks that will be used in case of
370 * @state: the current clocks state
371 * @delay_ms: gating delay in ms
372 * @is_suspended: clk gating is suspended when set to 1 which can be used
373 * during suspend/resume
374 * @delay_attr: sysfs attribute to control delay_attr
375 * @enable_attr: sysfs attribute to enable/disable clock gating
376 * @is_enabled: Indicates the current status of clock gating
377 * @is_initialized: Indicates whether clock gating is initialized or not
378 * @active_reqs: number of requests that are pending and should be waited for
379 * completion before gating clocks.
380 * @clk_gating_workq: workqueue for clock gating work.
382 struct ufs_clk_gating {
383 struct delayed_work gate_work;
384 struct work_struct ungate_work;
385 enum clk_gating_state state;
386 unsigned long delay_ms;
388 struct device_attribute delay_attr;
389 struct device_attribute enable_attr;
393 struct workqueue_struct *clk_gating_workq;
397 * struct ufs_clk_scaling - UFS clock scaling related data
398 * @active_reqs: number of requests that are pending. If this is zero when
399 * devfreq ->target() function is called then schedule "suspend_work" to
401 * @tot_busy_t: Total busy time in current polling window
402 * @window_start_t: Start time (in jiffies) of the current polling window
403 * @busy_start_t: Start time of current busy period
404 * @enable_attr: sysfs attribute to enable/disable clock scaling
405 * @saved_pwr_info: UFS power mode may also be changed during scaling and this
406 * one keeps track of previous power mode.
407 * @workq: workqueue to schedule devfreq suspend/resume work
408 * @suspend_work: worker to suspend devfreq
409 * @resume_work: worker to resume devfreq
410 * @min_gear: lowest HS gear to scale down to
411 * @is_enabled: tracks if scaling is currently enabled or not, controlled by
412 * clkscale_enable sysfs node
413 * @is_allowed: tracks if scaling is currently allowed or not, used to block
414 * clock scaling which is not invoked from devfreq governor
415 * @is_initialized: Indicates whether clock scaling is initialized or not
416 * @is_busy_started: tracks if busy period has started or not
417 * @is_suspended: tracks if devfreq is suspended or not
419 struct ufs_clk_scaling {
421 unsigned long tot_busy_t;
422 ktime_t window_start_t;
423 ktime_t busy_start_t;
424 struct device_attribute enable_attr;
425 struct ufs_pa_layer_attr saved_pwr_info;
426 struct workqueue_struct *workq;
427 struct work_struct suspend_work;
428 struct work_struct resume_work;
433 bool is_busy_started;
437 #define UFS_EVENT_HIST_LENGTH 8
439 * struct ufs_event_hist - keeps history of errors
440 * @pos: index to indicate cyclic buffer position
441 * @val: cyclic buffer for registers value
442 * @tstamp: cyclic buffer for time stamp
443 * @cnt: error counter
445 struct ufs_event_hist {
447 u32 val[UFS_EVENT_HIST_LENGTH];
448 u64 tstamp[UFS_EVENT_HIST_LENGTH];
449 unsigned long long cnt;
453 * struct ufs_stats - keeps usage/err statistics
454 * @last_intr_status: record the last interrupt status.
455 * @last_intr_ts: record the last interrupt timestamp.
456 * @hibern8_exit_cnt: Counter to keep track of number of exits,
457 * reset this after link-startup.
458 * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
459 * Clear after the first successful command completion.
460 * @event: array with event history.
463 u32 last_intr_status;
466 u32 hibern8_exit_cnt;
467 u64 last_hibern8_exit_tstamp;
468 struct ufs_event_hist event[UFS_EVT_CNT];
472 * enum ufshcd_state - UFS host controller state
473 * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command
475 * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process
477 * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.
478 * SCSI commands may be submitted to the controller.
479 * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail
480 * newly submitted SCSI commands with error code DID_BAD_TARGET.
481 * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery
482 * failed. Fail all SCSI commands with error code DID_ERROR.
486 UFSHCD_STATE_OPERATIONAL,
487 UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
488 UFSHCD_STATE_EH_SCHEDULED_FATAL,
493 /* Interrupt aggregation support is broken */
494 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
497 * delay before each dme command is required as the unipro
498 * layer has shown instabilities
500 UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS = 1 << 1,
503 * If UFS host controller is having issue in processing LCC (Line
504 * Control Command) coming from device then enable this quirk.
505 * When this quirk is enabled, host controller driver should disable
506 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
507 * attribute of device to 0).
509 UFSHCD_QUIRK_BROKEN_LCC = 1 << 2,
512 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
513 * inbound Link supports unterminated line in HS mode. Setting this
514 * attribute to 1 fixes moving to HS gear.
516 UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP = 1 << 3,
519 * This quirk needs to be enabled if the host controller only allows
520 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
523 UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE = 1 << 4,
526 * This quirk needs to be enabled if the host controller doesn't
527 * advertise the correct version in UFS_VER register. If this quirk
528 * is enabled, standard UFS host driver will call the vendor specific
529 * ops (get_ufs_hci_version) to get the correct version.
531 UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION = 1 << 5,
534 * Clear handling for transfer/task request list is just opposite.
536 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
539 * This quirk needs to be enabled if host controller doesn't allow
540 * that the interrupt aggregation timer and counter are reset by s/w.
542 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
545 * This quirks needs to be enabled if host controller cannot be
546 * enabled via HCE register.
548 UFSHCI_QUIRK_BROKEN_HCE = 1 << 8,
551 * This quirk needs to be enabled if the host controller regards
552 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
554 UFSHCD_QUIRK_PRDT_BYTE_GRAN = 1 << 9,
557 * This quirk needs to be enabled if the host controller reports
558 * OCS FATAL ERROR with device error through sense data
560 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR = 1 << 10,
563 * This quirk needs to be enabled if the host controller has
564 * auto-hibernate capability but it doesn't work.
566 UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8 = 1 << 11,
569 * This quirk needs to disable manual flush for write booster
571 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL = 1 << 12,
574 * This quirk needs to disable unipro timeout values
575 * before power mode change
577 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
580 * Align DMA SG entries on a 4 KiB boundary.
582 UFSHCD_QUIRK_4KB_DMA_ALIGNMENT = 1 << 14,
585 * This quirk needs to be enabled if the host controller does not
586 * support UIC command
588 UFSHCD_QUIRK_BROKEN_UIC_CMD = 1 << 15,
591 * This quirk needs to be enabled if the host controller cannot
592 * support physical host configuration.
594 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION = 1 << 16,
597 * This quirk needs to be enabled if the host controller has
598 * 64-bit addressing supported capability but it doesn't work.
600 UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS = 1 << 17,
603 * This quirk needs to be enabled if the host controller has
604 * auto-hibernate capability but it's FASTAUTO only.
606 UFSHCD_QUIRK_HIBERN_FASTAUTO = 1 << 18,
609 * This quirk needs to be enabled if the host controller needs
610 * to reinit the device after switching to maximum gear.
612 UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH = 1 << 19,
615 * Some host raises interrupt (per queue) in addition to
616 * CQES (traditional) when ESI is disabled.
617 * Enable this quirk will disable CQES and use per queue interrupt.
619 UFSHCD_QUIRK_MCQ_BROKEN_INTR = 1 << 20,
622 * Some host does not implement SQ Run Time Command (SQRTC) register
623 * thus need this quirk to skip related flow.
625 UFSHCD_QUIRK_MCQ_BROKEN_RTC = 1 << 21,
629 /* Allow dynamic clk gating */
630 UFSHCD_CAP_CLK_GATING = 1 << 0,
632 /* Allow hiberb8 with clk gating */
633 UFSHCD_CAP_HIBERN8_WITH_CLK_GATING = 1 << 1,
635 /* Allow dynamic clk scaling */
636 UFSHCD_CAP_CLK_SCALING = 1 << 2,
638 /* Allow auto bkops to enabled during runtime suspend */
639 UFSHCD_CAP_AUTO_BKOPS_SUSPEND = 1 << 3,
642 * This capability allows host controller driver to use the UFS HCI's
643 * interrupt aggregation capability.
644 * CAUTION: Enabling this might reduce overall UFS throughput.
646 UFSHCD_CAP_INTR_AGGR = 1 << 4,
649 * This capability allows the device auto-bkops to be always enabled
650 * except during suspend (both runtime and suspend).
651 * Enabling this capability means that device will always be allowed
652 * to do background operation when it's active but it might degrade
653 * the performance of ongoing read/write operations.
655 UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
658 * This capability allows host controller driver to automatically
659 * enable runtime power management by itself instead of waiting
660 * for userspace to control the power management.
662 UFSHCD_CAP_RPM_AUTOSUSPEND = 1 << 6,
665 * This capability allows the host controller driver to turn-on
666 * WriteBooster, if the underlying device supports it and is
667 * provisioned to be used. This would increase the write performance.
669 UFSHCD_CAP_WB_EN = 1 << 7,
672 * This capability allows the host controller driver to use the
673 * inline crypto engine, if it is present
675 UFSHCD_CAP_CRYPTO = 1 << 8,
678 * This capability allows the controller regulators to be put into
679 * lpm mode aggressively during clock gating.
680 * This would increase power savings.
682 UFSHCD_CAP_AGGR_POWER_COLLAPSE = 1 << 9,
685 * This capability allows the host controller driver to use DeepSleep,
686 * if it is supported by the UFS device. The host controller driver must
687 * support device hardware reset via the hba->device_reset() callback,
688 * in order to exit DeepSleep state.
690 UFSHCD_CAP_DEEPSLEEP = 1 << 10,
693 * This capability allows the host controller driver to use temperature
694 * notification if it is supported by the UFS device.
696 UFSHCD_CAP_TEMP_NOTIF = 1 << 11,
699 * Enable WriteBooster when scaling up the clock and disable
700 * WriteBooster when scaling the clock down.
702 UFSHCD_CAP_WB_WITH_CLK_SCALING = 1 << 12,
705 struct ufs_hba_variant_params {
706 struct devfreq_dev_profile devfreq_profile;
707 struct devfreq_simple_ondemand_data ondemand_data;
708 u16 hba_enable_delay_us;
709 u32 wb_flush_threshold;
712 #ifdef CONFIG_SCSI_UFS_HPB
714 * struct ufshpb_dev_info - UFSHPB device related info
715 * @num_lu: the number of user logical unit to check whether all lu finished
717 * @rgn_size: device reported HPB region size
718 * @srgn_size: device reported HPB sub-region size
719 * @slave_conf_cnt: counter to check all lu finished initialization
720 * @hpb_disabled: flag to check if HPB is disabled
721 * @max_hpb_single_cmd: device reported bMAX_DATA_SIZE_FOR_SINGLE_CMD value
722 * @is_legacy: flag to check HPB 1.0
723 * @control_mode: either host or device
725 struct ufshpb_dev_info {
729 atomic_t slave_conf_cnt;
731 u8 max_hpb_single_cmd;
737 struct ufs_hba_monitor {
738 unsigned long chunk_size;
740 unsigned long nr_sec_rw[2];
741 ktime_t total_busy[2];
743 unsigned long nr_req[2];
750 ktime_t busy_start_ts[2];
757 * struct ufshcd_res_info_t - MCQ related resource regions
759 * @name: resource name
760 * @resource: pointer to resource region
761 * @base: register base address
763 struct ufshcd_res_info {
765 struct resource *resource;
781 * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
783 * @offset: Doorbell Address Offset
784 * @stride: Steps proportional to queue [0...31]
785 * @base: base address
787 struct ufshcd_mcq_opr_info_t {
788 unsigned long offset;
789 unsigned long stride;
793 enum ufshcd_mcq_opr {
802 * struct ufs_hba - per adapter private structure
803 * @mmio_base: UFSHCI base register address
804 * @ucdl_base_addr: UFS Command Descriptor base address
805 * @utrdl_base_addr: UTP Transfer Request Descriptor base address
806 * @utmrdl_base_addr: UTP Task Management Descriptor base address
807 * @ucdl_dma_addr: UFS Command Descriptor DMA address
808 * @utrdl_dma_addr: UTRDL DMA address
809 * @utmrdl_dma_addr: UTMRDL DMA address
810 * @host: Scsi_Host instance of the driver
811 * @dev: device handle
812 * @ufs_device_wlun: WLUN that controls the entire UFS device.
813 * @hwmon_device: device instance registered with the hwmon core.
814 * @curr_dev_pwr_mode: active UFS device power mode.
815 * @uic_link_state: active state of the link to the UFS device.
816 * @rpm_lvl: desired UFS power management level during runtime PM.
817 * @spm_lvl: desired UFS power management level during system PM.
818 * @pm_op_in_progress: whether or not a PM operation is in progress.
819 * @ahit: value of Auto-Hibernate Idle Timer register.
820 * @lrb: local reference block
821 * @outstanding_tasks: Bits representing outstanding task requests
822 * @outstanding_lock: Protects @outstanding_reqs.
823 * @outstanding_reqs: Bits representing outstanding transfer requests
824 * @capabilities: UFS Controller Capabilities
825 * @mcq_capabilities: UFS Multi Circular Queue capabilities
826 * @nutrs: Transfer Request Queue depth supported by controller
827 * @nutmrs: Task Management Queue depth supported by controller
828 * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.
829 * @ufs_version: UFS Version to which controller complies
830 * @vops: pointer to variant specific operations
831 * @vps: pointer to variant specific parameters
832 * @priv: pointer to variant specific private data
833 * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
834 * @irq: Irq number of the controller
835 * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.
836 * @dev_ref_clk_freq: reference clock frequency
837 * @quirks: bitmask with information about deviations from the UFSHCI standard.
838 * @dev_quirks: bitmask with information about deviations from the UFS standard.
839 * @tmf_tag_set: TMF tag set.
840 * @tmf_queue: Used to allocate TMF tags.
841 * @tmf_rqs: array with pointers to TMF requests while these are in progress.
842 * @active_uic_cmd: handle of active UIC command
843 * @uic_cmd_mutex: mutex for UIC command
844 * @uic_async_done: completion used during UIC processing
845 * @ufshcd_state: UFSHCD state
846 * @eh_flags: Error handling flags
847 * @intr_mask: Interrupt Mask Bits
848 * @ee_ctrl_mask: Exception event control mask
849 * @ee_drv_mask: Exception event mask for driver
850 * @ee_usr_mask: Exception event mask for user (set via debugfs)
851 * @ee_ctrl_mutex: Used to serialize exception event information.
852 * @is_powered: flag to check if HBA is powered
853 * @shutting_down: flag to check if shutdown has been invoked
854 * @host_sem: semaphore used to serialize concurrent contexts
855 * @eh_wq: Workqueue that eh_work works on
856 * @eh_work: Worker to handle UFS errors that require s/w attention
857 * @eeh_work: Worker to handle exception events
858 * @errors: HBA errors
859 * @uic_error: UFS interconnect layer error status
860 * @saved_err: sticky error mask
861 * @saved_uic_err: sticky UIC error mask
862 * @ufs_stats: various error counters
863 * @force_reset: flag to force eh_work perform a full reset
864 * @force_pmc: flag to force a power mode change
865 * @silence_err_logs: flag to silence error logs
866 * @dev_cmd: ufs device management command information
867 * @last_dme_cmd_tstamp: time stamp of the last completed DME command
868 * @nop_out_timeout: NOP OUT timeout value
869 * @dev_info: information about the UFS device
870 * @auto_bkops_enabled: to track whether bkops is enabled in device
871 * @vreg_info: UFS device voltage regulator information
872 * @clk_list_head: UFS host controller clocks list node head
873 * @req_abort_count: number of times ufshcd_abort() has been called
874 * @lanes_per_direction: number of lanes per data direction between the UFS
875 * controller and the UFS device.
876 * @pwr_info: holds current power mode
877 * @max_pwr_info: keeps the device max valid pwm
878 * @clk_gating: information related to clock gating
879 * @caps: bitmask with information about UFS controller capabilities
880 * @devfreq: frequency scaling information owned by the devfreq core
881 * @clk_scaling: frequency scaling information owned by the UFS driver
882 * @system_suspending: system suspend has been started and system resume has
884 * @is_sys_suspended: UFS device has been suspended because of system suspend
885 * @urgent_bkops_lvl: keeps track of urgent bkops level for device
886 * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
887 * device is known or not.
888 * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
889 * @clk_scaling_lock: used to serialize device commands and clock scaling
890 * @desc_size: descriptor sizes reported by device
891 * @scsi_block_reqs_cnt: reference counting for scsi block requests
892 * @bsg_dev: struct device associated with the BSG queue
893 * @bsg_queue: BSG queue associated with the UFS controller
894 * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power
895 * management) after the UFS device has finished a WriteBooster buffer
896 * flush or auto BKOP.
897 * @ufshpb_dev: information related to HPB (Host Performance Booster).
898 * @monitor: statistics about UFS commands
899 * @crypto_capabilities: Content of crypto capabilities register (0x100)
900 * @crypto_cap_array: Array of crypto capabilities
901 * @crypto_cfg_register: Start of the crypto cfg array
902 * @crypto_profile: the crypto profile of this hba (if applicable)
903 * @debugfs_root: UFS controller debugfs root directory
904 * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay
905 * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore
907 * @luns_avail: number of regular and well known LUNs supported by the UFS
909 * @nr_hw_queues: number of hardware queues configured
910 * @nr_queues: number of Queues of different queue types
911 * @complete_put: whether or not to call ufshcd_rpm_put() from inside
912 * ufshcd_resume_complete()
913 * @ext_iid_sup: is EXT_IID is supported by UFSHC
914 * @mcq_sup: is mcq supported by UFSHC
915 * @mcq_enabled: is mcq ready to accept requests
916 * @res: array of resource info of MCQ registers
917 * @mcq_base: Multi circular queue registers base address
918 * @uhq: array of supported hardware queues
919 * @dev_cmd_queue: Queue for issuing device management commands
922 void __iomem *mmio_base;
924 /* Virtual memory reference */
925 struct utp_transfer_cmd_desc *ucdl_base_addr;
926 struct utp_transfer_req_desc *utrdl_base_addr;
927 struct utp_task_req_desc *utmrdl_base_addr;
929 /* DMA memory reference */
930 dma_addr_t ucdl_dma_addr;
931 dma_addr_t utrdl_dma_addr;
932 dma_addr_t utmrdl_dma_addr;
934 struct Scsi_Host *host;
936 struct scsi_device *ufs_device_wlun;
938 #ifdef CONFIG_SCSI_UFS_HWMON
939 struct device *hwmon_device;
942 enum ufs_dev_pwr_mode curr_dev_pwr_mode;
943 enum uic_link_state uic_link_state;
944 /* Desired UFS power management level during runtime PM */
945 enum ufs_pm_level rpm_lvl;
946 /* Desired UFS power management level during system PM */
947 enum ufs_pm_level spm_lvl;
948 int pm_op_in_progress;
950 /* Auto-Hibernate Idle Timer register value */
953 struct ufshcd_lrb *lrb;
955 unsigned long outstanding_tasks;
956 spinlock_t outstanding_lock;
957 unsigned long outstanding_reqs;
961 u32 mcq_capabilities;
965 const struct ufs_hba_variant_ops *vops;
966 struct ufs_hba_variant_params *vps;
968 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
969 size_t sg_entry_size;
973 enum ufs_ref_clk_freq dev_ref_clk_freq;
975 unsigned int quirks; /* Deviations from standard UFSHCI spec. */
977 /* Device deviations from standard UFS device spec. */
978 unsigned int dev_quirks;
980 struct blk_mq_tag_set tmf_tag_set;
981 struct request_queue *tmf_queue;
982 struct request **tmf_rqs;
984 struct uic_command *active_uic_cmd;
985 struct mutex uic_cmd_mutex;
986 struct completion *uic_async_done;
988 enum ufshcd_state ufshcd_state;
994 struct mutex ee_ctrl_mutex;
997 struct semaphore host_sem;
1000 struct workqueue_struct *eh_wq;
1001 struct work_struct eh_work;
1002 struct work_struct eeh_work;
1009 struct ufs_stats ufs_stats;
1012 bool silence_err_logs;
1014 /* Device management request data */
1015 struct ufs_dev_cmd dev_cmd;
1016 ktime_t last_dme_cmd_tstamp;
1017 int nop_out_timeout;
1019 /* Keeps information of the UFS device connected to this host */
1020 struct ufs_dev_info dev_info;
1021 bool auto_bkops_enabled;
1022 struct ufs_vreg_info vreg_info;
1023 struct list_head clk_list_head;
1025 /* Number of requests aborts */
1026 int req_abort_count;
1028 /* Number of lanes available (1 or 2) for Rx/Tx */
1029 u32 lanes_per_direction;
1030 struct ufs_pa_layer_attr pwr_info;
1031 struct ufs_pwr_mode_info max_pwr_info;
1033 struct ufs_clk_gating clk_gating;
1034 /* Control to enable/disable host capabilities */
1037 struct devfreq *devfreq;
1038 struct ufs_clk_scaling clk_scaling;
1039 bool system_suspending;
1040 bool is_sys_suspended;
1042 enum bkops_status urgent_bkops_lvl;
1043 bool is_urgent_bkops_lvl_checked;
1045 struct mutex wb_mutex;
1046 struct rw_semaphore clk_scaling_lock;
1047 atomic_t scsi_block_reqs_cnt;
1049 struct device bsg_dev;
1050 struct request_queue *bsg_queue;
1051 struct delayed_work rpm_dev_flush_recheck_work;
1053 #ifdef CONFIG_SCSI_UFS_HPB
1054 struct ufshpb_dev_info ufshpb_dev;
1057 struct ufs_hba_monitor monitor;
1059 #ifdef CONFIG_SCSI_UFS_CRYPTO
1060 union ufs_crypto_capabilities crypto_capabilities;
1061 union ufs_crypto_cap_entry *crypto_cap_array;
1062 u32 crypto_cfg_register;
1063 struct blk_crypto_profile crypto_profile;
1065 #ifdef CONFIG_DEBUG_FS
1066 struct dentry *debugfs_root;
1067 struct delayed_work debugfs_ee_work;
1068 u32 debugfs_ee_rate_limit_ms;
1071 unsigned int nr_hw_queues;
1072 unsigned int nr_queues[HCTX_MAX_TYPES];
1075 bool scsi_host_added;
1078 struct ufshcd_res_info res[RES_MAX];
1079 void __iomem *mcq_base;
1080 struct ufs_hw_queue *uhq;
1081 struct ufs_hw_queue *dev_cmd_queue;
1082 struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX];
1086 * struct ufs_hw_queue - per hardware queue structure
1087 * @mcq_sq_head: base address of submission queue head pointer
1088 * @mcq_sq_tail: base address of submission queue tail pointer
1089 * @mcq_cq_head: base address of completion queue head pointer
1090 * @mcq_cq_tail: base address of completion queue tail pointer
1091 * @sqe_base_addr: submission queue entry base address
1092 * @sqe_dma_addr: submission queue dma address
1093 * @cqe_base_addr: completion queue base address
1094 * @cqe_dma_addr: completion queue dma address
1095 * @max_entries: max number of slots in this hardware queue
1096 * @id: hardware queue ID
1097 * @sq_tp_slot: current slot to which SQ tail pointer is pointing
1098 * @sq_lock: serialize submission queue access
1099 * @cq_tail_slot: current slot to which CQ tail pointer is pointing
1100 * @cq_head_slot: current slot to which CQ head pointer is pointing
1101 * @cq_lock: Synchronize between multiple polling instances
1102 * @sq_mutex: prevent submission queue concurrent access
1104 struct ufs_hw_queue {
1105 void __iomem *mcq_sq_head;
1106 void __iomem *mcq_sq_tail;
1107 void __iomem *mcq_cq_head;
1108 void __iomem *mcq_cq_tail;
1110 struct utp_transfer_req_desc *sqe_base_addr;
1111 dma_addr_t sqe_dma_addr;
1112 struct cq_entry *cqe_base_addr;
1113 dma_addr_t cqe_dma_addr;
1121 /* prevent concurrent access to submission queue */
1122 struct mutex sq_mutex;
1125 static inline bool is_mcq_enabled(struct ufs_hba *hba)
1127 return hba->mcq_enabled;
1130 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
1131 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1133 return hba->sg_entry_size;
1136 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size)
1138 WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry));
1139 hba->sg_entry_size = sg_entry_size;
1142 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1144 return sizeof(struct ufshcd_sg_entry);
1147 #define ufshcd_set_sg_entry_size(hba, sg_entry_size) \
1148 ({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })
1151 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba)
1153 return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba);
1156 /* Returns true if clocks can be gated. Otherwise false */
1157 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
1159 return hba->caps & UFSHCD_CAP_CLK_GATING;
1161 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
1163 return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1165 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
1167 return hba->caps & UFSHCD_CAP_CLK_SCALING;
1169 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
1171 return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1173 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
1175 return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
1178 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
1180 return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&
1181 !(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);
1184 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
1186 return !!(ufshcd_is_link_hibern8(hba) &&
1187 (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
1190 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
1192 return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
1193 !(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
1196 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
1198 return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);
1201 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
1203 return hba->caps & UFSHCD_CAP_WB_EN;
1206 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
1208 return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
1211 #define ufsmcq_writel(hba, val, reg) \
1212 writel((val), (hba)->mcq_base + (reg))
1213 #define ufsmcq_readl(hba, reg) \
1214 readl((hba)->mcq_base + (reg))
1216 #define ufsmcq_writelx(hba, val, reg) \
1217 writel_relaxed((val), (hba)->mcq_base + (reg))
1218 #define ufsmcq_readlx(hba, reg) \
1219 readl_relaxed((hba)->mcq_base + (reg))
1221 #define ufshcd_writel(hba, val, reg) \
1222 writel((val), (hba)->mmio_base + (reg))
1223 #define ufshcd_readl(hba, reg) \
1224 readl((hba)->mmio_base + (reg))
1227 * ufshcd_rmwl - perform read/modify/write for a controller register
1228 * @hba: per adapter instance
1229 * @mask: mask to apply on read value
1230 * @val: actual value to write
1231 * @reg: register address
1233 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1237 tmp = ufshcd_readl(hba, reg);
1239 tmp |= (val & mask);
1240 ufshcd_writel(hba, tmp, reg);
1243 int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1244 void ufshcd_dealloc_host(struct ufs_hba *);
1245 int ufshcd_hba_enable(struct ufs_hba *hba);
1246 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
1247 int ufshcd_link_recovery(struct ufs_hba *hba);
1248 int ufshcd_make_hba_operational(struct ufs_hba *hba);
1249 void ufshcd_remove(struct ufs_hba *);
1250 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
1251 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1252 void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
1253 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
1254 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1255 void ufshcd_hba_stop(struct ufs_hba *hba);
1256 void ufshcd_schedule_eh_work(struct ufs_hba *hba);
1257 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);
1258 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
1259 struct ufs_hw_queue *hwq);
1260 void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
1261 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
1264 * ufshcd_set_variant - set variant specific data to the hba
1265 * @hba: per adapter instance
1266 * @variant: pointer to variant specific data
1268 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
1271 hba->priv = variant;
1275 * ufshcd_get_variant - get variant specific data from the hba
1276 * @hba: per adapter instance
1278 static inline void *ufshcd_get_variant(struct ufs_hba *hba)
1285 extern int ufshcd_runtime_suspend(struct device *dev);
1286 extern int ufshcd_runtime_resume(struct device *dev);
1288 #ifdef CONFIG_PM_SLEEP
1289 extern int ufshcd_system_suspend(struct device *dev);
1290 extern int ufshcd_system_resume(struct device *dev);
1291 extern int ufshcd_system_freeze(struct device *dev);
1292 extern int ufshcd_system_thaw(struct device *dev);
1293 extern int ufshcd_system_restore(struct device *dev);
1296 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
1299 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1300 u8 attr_set, u32 mib_val, u8 peer);
1301 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1302 u32 *mib_val, u8 peer);
1303 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
1304 struct ufs_pa_layer_attr *desired_pwr_mode);
1305 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);
1307 /* UIC command interfaces for DME primitives */
1310 #define ATTR_SET_NOR 0 /* NORMAL */
1311 #define ATTR_SET_ST 1 /* STATIC */
1313 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1316 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1317 mib_val, DME_LOCAL);
1320 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1323 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1324 mib_val, DME_LOCAL);
1327 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1330 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1334 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1337 return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1341 static inline int ufshcd_dme_get(struct ufs_hba *hba,
1342 u32 attr_sel, u32 *mib_val)
1344 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1347 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1348 u32 attr_sel, u32 *mib_val)
1350 return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1353 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)
1355 return (pwr_info->pwr_rx == FAST_MODE ||
1356 pwr_info->pwr_rx == FASTAUTO_MODE) &&
1357 (pwr_info->pwr_tx == FAST_MODE ||
1358 pwr_info->pwr_tx == FASTAUTO_MODE);
1361 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1363 return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1366 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba);
1367 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
1368 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
1369 const struct ufs_dev_quirk *fixups);
1370 #define SD_ASCII_STD true
1371 #define SD_RAW false
1372 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
1373 u8 **buf, bool ascii);
1375 void ufshcd_hold(struct ufs_hba *hba);
1376 void ufshcd_release(struct ufs_hba *hba);
1378 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value);
1380 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba);
1382 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg);
1384 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1386 int ufshcd_exec_raw_upiu_cmd(struct ufs_hba *hba,
1387 struct utp_upiu_req *req_upiu,
1388 struct utp_upiu_req *rsp_upiu,
1390 u8 *desc_buff, int *buff_len,
1391 enum query_opcode desc_op);
1392 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
1393 struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req,
1394 struct ufs_ehs *ehs_rsp, int sg_cnt,
1395 struct scatterlist *sg_list, enum dma_data_direction dir);
1396 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
1397 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable);
1398 int ufshcd_suspend_prepare(struct device *dev);
1399 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);
1400 void ufshcd_resume_complete(struct device *dev);
1402 /* Wrapper functions for safely calling variant operations */
1403 static inline int ufshcd_vops_init(struct ufs_hba *hba)
1405 if (hba->vops && hba->vops->init)
1406 return hba->vops->init(hba);
1411 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)
1413 if (hba->vops && hba->vops->phy_initialization)
1414 return hba->vops->phy_initialization(hba);
1419 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1421 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1422 const char *prefix);
1424 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask);
1425 int ufshcd_write_ee_control(struct ufs_hba *hba);
1426 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
1427 const u16 *other_mask, u16 set, u16 clr);
1429 #endif /* End of Header */