1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2022 HabanaLabs, Ltd.
11 #include <linux/types.h>
12 #include <linux/ioctl.h>
15 * Defines that are asic-specific but constitutes as ABI between kernel driver
18 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */
19 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */
22 * 128 SOBs reserved for collective wait
23 * 16 SOBs reserved for sync stream
25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144
28 * 64 monitors reserved for collective wait
29 * 8 monitors reserved for sync stream
31 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72
33 /* Max number of elements in timestamps registration buffers */
34 #define TS_MAX_ELEMENTS_NUM (1 << 20) /* 1MB */
37 * Goya queue Numbering
39 * The external queues (PCI DMA channels) MUST be before the internal queues
40 * and each group (PCI DMA channels and internal) must be contiguous inside
41 * itself but there can be a gap between the two groups (although not
46 GOYA_QUEUE_ID_DMA_0 = 0,
47 GOYA_QUEUE_ID_DMA_1 = 1,
48 GOYA_QUEUE_ID_DMA_2 = 2,
49 GOYA_QUEUE_ID_DMA_3 = 3,
50 GOYA_QUEUE_ID_DMA_4 = 4,
51 GOYA_QUEUE_ID_CPU_PQ = 5,
52 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */
53 GOYA_QUEUE_ID_TPC0 = 7,
54 GOYA_QUEUE_ID_TPC1 = 8,
55 GOYA_QUEUE_ID_TPC2 = 9,
56 GOYA_QUEUE_ID_TPC3 = 10,
57 GOYA_QUEUE_ID_TPC4 = 11,
58 GOYA_QUEUE_ID_TPC5 = 12,
59 GOYA_QUEUE_ID_TPC6 = 13,
60 GOYA_QUEUE_ID_TPC7 = 14,
65 * Gaudi queue Numbering
66 * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*.
67 * Except one CPU queue, all the rest are internal queues.
71 GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */
72 GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */
73 GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */
74 GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */
75 GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */
76 GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */
77 GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */
78 GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */
79 GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */
80 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */
81 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */
82 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */
83 GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */
84 GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */
85 GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */
86 GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */
87 GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */
88 GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */
89 GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */
90 GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */
91 GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */
92 GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */
93 GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */
94 GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */
95 GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */
96 GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */
97 GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */
98 GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */
99 GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */
100 GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */
101 GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */
102 GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */
103 GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */
104 GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */
105 GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */
106 GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */
107 GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */
108 GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */
109 GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */
110 GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */
111 GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */
112 GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */
113 GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */
114 GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */
115 GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */
116 GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */
117 GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */
118 GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */
119 GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */
120 GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */
121 GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */
122 GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */
123 GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */
124 GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */
125 GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */
126 GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */
127 GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */
128 GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */
129 GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */
130 GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */
131 GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */
132 GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */
133 GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */
134 GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */
135 GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */
136 GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */
137 GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */
138 GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */
139 GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */
140 GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */
141 GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */
142 GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */
143 GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */
144 GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */
145 GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */
146 GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */
147 GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */
148 GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */
149 GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */
150 GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */
151 GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */
152 GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */
153 GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */
154 GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */
155 GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */
156 GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */
157 GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */
158 GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */
159 GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */
160 GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */
161 GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */
162 GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */
163 GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */
164 GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */
165 GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */
166 GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */
167 GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */
168 GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */
169 GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */
170 GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */
171 GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */
172 GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */
173 GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */
174 GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */
175 GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */
176 GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */
177 GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */
178 GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */
179 GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */
180 GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */
181 GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */
182 GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */
183 GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */
188 * In GAUDI2 we have two modes of operation in regard to queues:
189 * 1. Legacy mode, where each QMAN exposes 4 streams to the user
190 * 2. F/W mode, where we use F/W to schedule the JOBS to the different queues.
192 * When in legacy mode, the user sends the queue id per JOB according to
193 * enum gaudi2_queue_id below.
195 * When in F/W mode, the user sends a stream id per Command Submission. The
196 * stream id is a running number from 0 up to (N-1), where N is the number
197 * of streams the F/W exposes and is passed to the user in
198 * struct hl_info_hw_ip_info
201 enum gaudi2_queue_id {
202 GAUDI2_QUEUE_ID_PDMA_0_0 = 0,
203 GAUDI2_QUEUE_ID_PDMA_0_1 = 1,
204 GAUDI2_QUEUE_ID_PDMA_0_2 = 2,
205 GAUDI2_QUEUE_ID_PDMA_0_3 = 3,
206 GAUDI2_QUEUE_ID_PDMA_1_0 = 4,
207 GAUDI2_QUEUE_ID_PDMA_1_1 = 5,
208 GAUDI2_QUEUE_ID_PDMA_1_2 = 6,
209 GAUDI2_QUEUE_ID_PDMA_1_3 = 7,
210 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0 = 8,
211 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1 = 9,
212 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2 = 10,
213 GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3 = 11,
214 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0 = 12,
215 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1 = 13,
216 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2 = 14,
217 GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3 = 15,
218 GAUDI2_QUEUE_ID_DCORE0_MME_0_0 = 16,
219 GAUDI2_QUEUE_ID_DCORE0_MME_0_1 = 17,
220 GAUDI2_QUEUE_ID_DCORE0_MME_0_2 = 18,
221 GAUDI2_QUEUE_ID_DCORE0_MME_0_3 = 19,
222 GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 = 20,
223 GAUDI2_QUEUE_ID_DCORE0_TPC_0_1 = 21,
224 GAUDI2_QUEUE_ID_DCORE0_TPC_0_2 = 22,
225 GAUDI2_QUEUE_ID_DCORE0_TPC_0_3 = 23,
226 GAUDI2_QUEUE_ID_DCORE0_TPC_1_0 = 24,
227 GAUDI2_QUEUE_ID_DCORE0_TPC_1_1 = 25,
228 GAUDI2_QUEUE_ID_DCORE0_TPC_1_2 = 26,
229 GAUDI2_QUEUE_ID_DCORE0_TPC_1_3 = 27,
230 GAUDI2_QUEUE_ID_DCORE0_TPC_2_0 = 28,
231 GAUDI2_QUEUE_ID_DCORE0_TPC_2_1 = 29,
232 GAUDI2_QUEUE_ID_DCORE0_TPC_2_2 = 30,
233 GAUDI2_QUEUE_ID_DCORE0_TPC_2_3 = 31,
234 GAUDI2_QUEUE_ID_DCORE0_TPC_3_0 = 32,
235 GAUDI2_QUEUE_ID_DCORE0_TPC_3_1 = 33,
236 GAUDI2_QUEUE_ID_DCORE0_TPC_3_2 = 34,
237 GAUDI2_QUEUE_ID_DCORE0_TPC_3_3 = 35,
238 GAUDI2_QUEUE_ID_DCORE0_TPC_4_0 = 36,
239 GAUDI2_QUEUE_ID_DCORE0_TPC_4_1 = 37,
240 GAUDI2_QUEUE_ID_DCORE0_TPC_4_2 = 38,
241 GAUDI2_QUEUE_ID_DCORE0_TPC_4_3 = 39,
242 GAUDI2_QUEUE_ID_DCORE0_TPC_5_0 = 40,
243 GAUDI2_QUEUE_ID_DCORE0_TPC_5_1 = 41,
244 GAUDI2_QUEUE_ID_DCORE0_TPC_5_2 = 42,
245 GAUDI2_QUEUE_ID_DCORE0_TPC_5_3 = 43,
246 GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 = 44,
247 GAUDI2_QUEUE_ID_DCORE0_TPC_6_1 = 45,
248 GAUDI2_QUEUE_ID_DCORE0_TPC_6_2 = 46,
249 GAUDI2_QUEUE_ID_DCORE0_TPC_6_3 = 47,
250 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0 = 48,
251 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1 = 49,
252 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2 = 50,
253 GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3 = 51,
254 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0 = 52,
255 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1 = 53,
256 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2 = 54,
257 GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3 = 55,
258 GAUDI2_QUEUE_ID_DCORE1_MME_0_0 = 56,
259 GAUDI2_QUEUE_ID_DCORE1_MME_0_1 = 57,
260 GAUDI2_QUEUE_ID_DCORE1_MME_0_2 = 58,
261 GAUDI2_QUEUE_ID_DCORE1_MME_0_3 = 59,
262 GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 = 60,
263 GAUDI2_QUEUE_ID_DCORE1_TPC_0_1 = 61,
264 GAUDI2_QUEUE_ID_DCORE1_TPC_0_2 = 62,
265 GAUDI2_QUEUE_ID_DCORE1_TPC_0_3 = 63,
266 GAUDI2_QUEUE_ID_DCORE1_TPC_1_0 = 64,
267 GAUDI2_QUEUE_ID_DCORE1_TPC_1_1 = 65,
268 GAUDI2_QUEUE_ID_DCORE1_TPC_1_2 = 66,
269 GAUDI2_QUEUE_ID_DCORE1_TPC_1_3 = 67,
270 GAUDI2_QUEUE_ID_DCORE1_TPC_2_0 = 68,
271 GAUDI2_QUEUE_ID_DCORE1_TPC_2_1 = 69,
272 GAUDI2_QUEUE_ID_DCORE1_TPC_2_2 = 70,
273 GAUDI2_QUEUE_ID_DCORE1_TPC_2_3 = 71,
274 GAUDI2_QUEUE_ID_DCORE1_TPC_3_0 = 72,
275 GAUDI2_QUEUE_ID_DCORE1_TPC_3_1 = 73,
276 GAUDI2_QUEUE_ID_DCORE1_TPC_3_2 = 74,
277 GAUDI2_QUEUE_ID_DCORE1_TPC_3_3 = 75,
278 GAUDI2_QUEUE_ID_DCORE1_TPC_4_0 = 76,
279 GAUDI2_QUEUE_ID_DCORE1_TPC_4_1 = 77,
280 GAUDI2_QUEUE_ID_DCORE1_TPC_4_2 = 78,
281 GAUDI2_QUEUE_ID_DCORE1_TPC_4_3 = 79,
282 GAUDI2_QUEUE_ID_DCORE1_TPC_5_0 = 80,
283 GAUDI2_QUEUE_ID_DCORE1_TPC_5_1 = 81,
284 GAUDI2_QUEUE_ID_DCORE1_TPC_5_2 = 82,
285 GAUDI2_QUEUE_ID_DCORE1_TPC_5_3 = 83,
286 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0 = 84,
287 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1 = 85,
288 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2 = 86,
289 GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3 = 87,
290 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0 = 88,
291 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1 = 89,
292 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2 = 90,
293 GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3 = 91,
294 GAUDI2_QUEUE_ID_DCORE2_MME_0_0 = 92,
295 GAUDI2_QUEUE_ID_DCORE2_MME_0_1 = 93,
296 GAUDI2_QUEUE_ID_DCORE2_MME_0_2 = 94,
297 GAUDI2_QUEUE_ID_DCORE2_MME_0_3 = 95,
298 GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 = 96,
299 GAUDI2_QUEUE_ID_DCORE2_TPC_0_1 = 97,
300 GAUDI2_QUEUE_ID_DCORE2_TPC_0_2 = 98,
301 GAUDI2_QUEUE_ID_DCORE2_TPC_0_3 = 99,
302 GAUDI2_QUEUE_ID_DCORE2_TPC_1_0 = 100,
303 GAUDI2_QUEUE_ID_DCORE2_TPC_1_1 = 101,
304 GAUDI2_QUEUE_ID_DCORE2_TPC_1_2 = 102,
305 GAUDI2_QUEUE_ID_DCORE2_TPC_1_3 = 103,
306 GAUDI2_QUEUE_ID_DCORE2_TPC_2_0 = 104,
307 GAUDI2_QUEUE_ID_DCORE2_TPC_2_1 = 105,
308 GAUDI2_QUEUE_ID_DCORE2_TPC_2_2 = 106,
309 GAUDI2_QUEUE_ID_DCORE2_TPC_2_3 = 107,
310 GAUDI2_QUEUE_ID_DCORE2_TPC_3_0 = 108,
311 GAUDI2_QUEUE_ID_DCORE2_TPC_3_1 = 109,
312 GAUDI2_QUEUE_ID_DCORE2_TPC_3_2 = 110,
313 GAUDI2_QUEUE_ID_DCORE2_TPC_3_3 = 111,
314 GAUDI2_QUEUE_ID_DCORE2_TPC_4_0 = 112,
315 GAUDI2_QUEUE_ID_DCORE2_TPC_4_1 = 113,
316 GAUDI2_QUEUE_ID_DCORE2_TPC_4_2 = 114,
317 GAUDI2_QUEUE_ID_DCORE2_TPC_4_3 = 115,
318 GAUDI2_QUEUE_ID_DCORE2_TPC_5_0 = 116,
319 GAUDI2_QUEUE_ID_DCORE2_TPC_5_1 = 117,
320 GAUDI2_QUEUE_ID_DCORE2_TPC_5_2 = 118,
321 GAUDI2_QUEUE_ID_DCORE2_TPC_5_3 = 119,
322 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0 = 120,
323 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1 = 121,
324 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2 = 122,
325 GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3 = 123,
326 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0 = 124,
327 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1 = 125,
328 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2 = 126,
329 GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3 = 127,
330 GAUDI2_QUEUE_ID_DCORE3_MME_0_0 = 128,
331 GAUDI2_QUEUE_ID_DCORE3_MME_0_1 = 129,
332 GAUDI2_QUEUE_ID_DCORE3_MME_0_2 = 130,
333 GAUDI2_QUEUE_ID_DCORE3_MME_0_3 = 131,
334 GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 = 132,
335 GAUDI2_QUEUE_ID_DCORE3_TPC_0_1 = 133,
336 GAUDI2_QUEUE_ID_DCORE3_TPC_0_2 = 134,
337 GAUDI2_QUEUE_ID_DCORE3_TPC_0_3 = 135,
338 GAUDI2_QUEUE_ID_DCORE3_TPC_1_0 = 136,
339 GAUDI2_QUEUE_ID_DCORE3_TPC_1_1 = 137,
340 GAUDI2_QUEUE_ID_DCORE3_TPC_1_2 = 138,
341 GAUDI2_QUEUE_ID_DCORE3_TPC_1_3 = 139,
342 GAUDI2_QUEUE_ID_DCORE3_TPC_2_0 = 140,
343 GAUDI2_QUEUE_ID_DCORE3_TPC_2_1 = 141,
344 GAUDI2_QUEUE_ID_DCORE3_TPC_2_2 = 142,
345 GAUDI2_QUEUE_ID_DCORE3_TPC_2_3 = 143,
346 GAUDI2_QUEUE_ID_DCORE3_TPC_3_0 = 144,
347 GAUDI2_QUEUE_ID_DCORE3_TPC_3_1 = 145,
348 GAUDI2_QUEUE_ID_DCORE3_TPC_3_2 = 146,
349 GAUDI2_QUEUE_ID_DCORE3_TPC_3_3 = 147,
350 GAUDI2_QUEUE_ID_DCORE3_TPC_4_0 = 148,
351 GAUDI2_QUEUE_ID_DCORE3_TPC_4_1 = 149,
352 GAUDI2_QUEUE_ID_DCORE3_TPC_4_2 = 150,
353 GAUDI2_QUEUE_ID_DCORE3_TPC_4_3 = 151,
354 GAUDI2_QUEUE_ID_DCORE3_TPC_5_0 = 152,
355 GAUDI2_QUEUE_ID_DCORE3_TPC_5_1 = 153,
356 GAUDI2_QUEUE_ID_DCORE3_TPC_5_2 = 154,
357 GAUDI2_QUEUE_ID_DCORE3_TPC_5_3 = 155,
358 GAUDI2_QUEUE_ID_NIC_0_0 = 156,
359 GAUDI2_QUEUE_ID_NIC_0_1 = 157,
360 GAUDI2_QUEUE_ID_NIC_0_2 = 158,
361 GAUDI2_QUEUE_ID_NIC_0_3 = 159,
362 GAUDI2_QUEUE_ID_NIC_1_0 = 160,
363 GAUDI2_QUEUE_ID_NIC_1_1 = 161,
364 GAUDI2_QUEUE_ID_NIC_1_2 = 162,
365 GAUDI2_QUEUE_ID_NIC_1_3 = 163,
366 GAUDI2_QUEUE_ID_NIC_2_0 = 164,
367 GAUDI2_QUEUE_ID_NIC_2_1 = 165,
368 GAUDI2_QUEUE_ID_NIC_2_2 = 166,
369 GAUDI2_QUEUE_ID_NIC_2_3 = 167,
370 GAUDI2_QUEUE_ID_NIC_3_0 = 168,
371 GAUDI2_QUEUE_ID_NIC_3_1 = 169,
372 GAUDI2_QUEUE_ID_NIC_3_2 = 170,
373 GAUDI2_QUEUE_ID_NIC_3_3 = 171,
374 GAUDI2_QUEUE_ID_NIC_4_0 = 172,
375 GAUDI2_QUEUE_ID_NIC_4_1 = 173,
376 GAUDI2_QUEUE_ID_NIC_4_2 = 174,
377 GAUDI2_QUEUE_ID_NIC_4_3 = 175,
378 GAUDI2_QUEUE_ID_NIC_5_0 = 176,
379 GAUDI2_QUEUE_ID_NIC_5_1 = 177,
380 GAUDI2_QUEUE_ID_NIC_5_2 = 178,
381 GAUDI2_QUEUE_ID_NIC_5_3 = 179,
382 GAUDI2_QUEUE_ID_NIC_6_0 = 180,
383 GAUDI2_QUEUE_ID_NIC_6_1 = 181,
384 GAUDI2_QUEUE_ID_NIC_6_2 = 182,
385 GAUDI2_QUEUE_ID_NIC_6_3 = 183,
386 GAUDI2_QUEUE_ID_NIC_7_0 = 184,
387 GAUDI2_QUEUE_ID_NIC_7_1 = 185,
388 GAUDI2_QUEUE_ID_NIC_7_2 = 186,
389 GAUDI2_QUEUE_ID_NIC_7_3 = 187,
390 GAUDI2_QUEUE_ID_NIC_8_0 = 188,
391 GAUDI2_QUEUE_ID_NIC_8_1 = 189,
392 GAUDI2_QUEUE_ID_NIC_8_2 = 190,
393 GAUDI2_QUEUE_ID_NIC_8_3 = 191,
394 GAUDI2_QUEUE_ID_NIC_9_0 = 192,
395 GAUDI2_QUEUE_ID_NIC_9_1 = 193,
396 GAUDI2_QUEUE_ID_NIC_9_2 = 194,
397 GAUDI2_QUEUE_ID_NIC_9_3 = 195,
398 GAUDI2_QUEUE_ID_NIC_10_0 = 196,
399 GAUDI2_QUEUE_ID_NIC_10_1 = 197,
400 GAUDI2_QUEUE_ID_NIC_10_2 = 198,
401 GAUDI2_QUEUE_ID_NIC_10_3 = 199,
402 GAUDI2_QUEUE_ID_NIC_11_0 = 200,
403 GAUDI2_QUEUE_ID_NIC_11_1 = 201,
404 GAUDI2_QUEUE_ID_NIC_11_2 = 202,
405 GAUDI2_QUEUE_ID_NIC_11_3 = 203,
406 GAUDI2_QUEUE_ID_NIC_12_0 = 204,
407 GAUDI2_QUEUE_ID_NIC_12_1 = 205,
408 GAUDI2_QUEUE_ID_NIC_12_2 = 206,
409 GAUDI2_QUEUE_ID_NIC_12_3 = 207,
410 GAUDI2_QUEUE_ID_NIC_13_0 = 208,
411 GAUDI2_QUEUE_ID_NIC_13_1 = 209,
412 GAUDI2_QUEUE_ID_NIC_13_2 = 210,
413 GAUDI2_QUEUE_ID_NIC_13_3 = 211,
414 GAUDI2_QUEUE_ID_NIC_14_0 = 212,
415 GAUDI2_QUEUE_ID_NIC_14_1 = 213,
416 GAUDI2_QUEUE_ID_NIC_14_2 = 214,
417 GAUDI2_QUEUE_ID_NIC_14_3 = 215,
418 GAUDI2_QUEUE_ID_NIC_15_0 = 216,
419 GAUDI2_QUEUE_ID_NIC_15_1 = 217,
420 GAUDI2_QUEUE_ID_NIC_15_2 = 218,
421 GAUDI2_QUEUE_ID_NIC_15_3 = 219,
422 GAUDI2_QUEUE_ID_NIC_16_0 = 220,
423 GAUDI2_QUEUE_ID_NIC_16_1 = 221,
424 GAUDI2_QUEUE_ID_NIC_16_2 = 222,
425 GAUDI2_QUEUE_ID_NIC_16_3 = 223,
426 GAUDI2_QUEUE_ID_NIC_17_0 = 224,
427 GAUDI2_QUEUE_ID_NIC_17_1 = 225,
428 GAUDI2_QUEUE_ID_NIC_17_2 = 226,
429 GAUDI2_QUEUE_ID_NIC_17_3 = 227,
430 GAUDI2_QUEUE_ID_NIC_18_0 = 228,
431 GAUDI2_QUEUE_ID_NIC_18_1 = 229,
432 GAUDI2_QUEUE_ID_NIC_18_2 = 230,
433 GAUDI2_QUEUE_ID_NIC_18_3 = 231,
434 GAUDI2_QUEUE_ID_NIC_19_0 = 232,
435 GAUDI2_QUEUE_ID_NIC_19_1 = 233,
436 GAUDI2_QUEUE_ID_NIC_19_2 = 234,
437 GAUDI2_QUEUE_ID_NIC_19_3 = 235,
438 GAUDI2_QUEUE_ID_NIC_20_0 = 236,
439 GAUDI2_QUEUE_ID_NIC_20_1 = 237,
440 GAUDI2_QUEUE_ID_NIC_20_2 = 238,
441 GAUDI2_QUEUE_ID_NIC_20_3 = 239,
442 GAUDI2_QUEUE_ID_NIC_21_0 = 240,
443 GAUDI2_QUEUE_ID_NIC_21_1 = 241,
444 GAUDI2_QUEUE_ID_NIC_21_2 = 242,
445 GAUDI2_QUEUE_ID_NIC_21_3 = 243,
446 GAUDI2_QUEUE_ID_NIC_22_0 = 244,
447 GAUDI2_QUEUE_ID_NIC_22_1 = 245,
448 GAUDI2_QUEUE_ID_NIC_22_2 = 246,
449 GAUDI2_QUEUE_ID_NIC_22_3 = 247,
450 GAUDI2_QUEUE_ID_NIC_23_0 = 248,
451 GAUDI2_QUEUE_ID_NIC_23_1 = 249,
452 GAUDI2_QUEUE_ID_NIC_23_2 = 250,
453 GAUDI2_QUEUE_ID_NIC_23_3 = 251,
454 GAUDI2_QUEUE_ID_ROT_0_0 = 252,
455 GAUDI2_QUEUE_ID_ROT_0_1 = 253,
456 GAUDI2_QUEUE_ID_ROT_0_2 = 254,
457 GAUDI2_QUEUE_ID_ROT_0_3 = 255,
458 GAUDI2_QUEUE_ID_ROT_1_0 = 256,
459 GAUDI2_QUEUE_ID_ROT_1_1 = 257,
460 GAUDI2_QUEUE_ID_ROT_1_2 = 258,
461 GAUDI2_QUEUE_ID_ROT_1_3 = 259,
462 GAUDI2_QUEUE_ID_CPU_PQ = 260,
469 * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle'
472 enum goya_engine_id {
473 GOYA_ENGINE_ID_DMA_0 = 0,
474 GOYA_ENGINE_ID_DMA_1,
475 GOYA_ENGINE_ID_DMA_2,
476 GOYA_ENGINE_ID_DMA_3,
477 GOYA_ENGINE_ID_DMA_4,
478 GOYA_ENGINE_ID_MME_0,
479 GOYA_ENGINE_ID_TPC_0,
480 GOYA_ENGINE_ID_TPC_1,
481 GOYA_ENGINE_ID_TPC_2,
482 GOYA_ENGINE_ID_TPC_3,
483 GOYA_ENGINE_ID_TPC_4,
484 GOYA_ENGINE_ID_TPC_5,
485 GOYA_ENGINE_ID_TPC_6,
486 GOYA_ENGINE_ID_TPC_7,
490 enum gaudi_engine_id {
491 GAUDI_ENGINE_ID_DMA_0 = 0,
492 GAUDI_ENGINE_ID_DMA_1,
493 GAUDI_ENGINE_ID_DMA_2,
494 GAUDI_ENGINE_ID_DMA_3,
495 GAUDI_ENGINE_ID_DMA_4,
496 GAUDI_ENGINE_ID_DMA_5,
497 GAUDI_ENGINE_ID_DMA_6,
498 GAUDI_ENGINE_ID_DMA_7,
499 GAUDI_ENGINE_ID_MME_0,
500 GAUDI_ENGINE_ID_MME_1,
501 GAUDI_ENGINE_ID_MME_2,
502 GAUDI_ENGINE_ID_MME_3,
503 GAUDI_ENGINE_ID_TPC_0,
504 GAUDI_ENGINE_ID_TPC_1,
505 GAUDI_ENGINE_ID_TPC_2,
506 GAUDI_ENGINE_ID_TPC_3,
507 GAUDI_ENGINE_ID_TPC_4,
508 GAUDI_ENGINE_ID_TPC_5,
509 GAUDI_ENGINE_ID_TPC_6,
510 GAUDI_ENGINE_ID_TPC_7,
511 GAUDI_ENGINE_ID_NIC_0,
512 GAUDI_ENGINE_ID_NIC_1,
513 GAUDI_ENGINE_ID_NIC_2,
514 GAUDI_ENGINE_ID_NIC_3,
515 GAUDI_ENGINE_ID_NIC_4,
516 GAUDI_ENGINE_ID_NIC_5,
517 GAUDI_ENGINE_ID_NIC_6,
518 GAUDI_ENGINE_ID_NIC_7,
519 GAUDI_ENGINE_ID_NIC_8,
520 GAUDI_ENGINE_ID_NIC_9,
524 enum gaudi2_engine_id {
525 GAUDI2_DCORE0_ENGINE_ID_EDMA_0 = 0,
526 GAUDI2_DCORE0_ENGINE_ID_EDMA_1,
527 GAUDI2_DCORE0_ENGINE_ID_MME,
528 GAUDI2_DCORE0_ENGINE_ID_TPC_0,
529 GAUDI2_DCORE0_ENGINE_ID_TPC_1,
530 GAUDI2_DCORE0_ENGINE_ID_TPC_2,
531 GAUDI2_DCORE0_ENGINE_ID_TPC_3,
532 GAUDI2_DCORE0_ENGINE_ID_TPC_4,
533 GAUDI2_DCORE0_ENGINE_ID_TPC_5,
534 GAUDI2_DCORE0_ENGINE_ID_DEC_0,
535 GAUDI2_DCORE0_ENGINE_ID_DEC_1,
536 GAUDI2_DCORE1_ENGINE_ID_EDMA_0,
537 GAUDI2_DCORE1_ENGINE_ID_EDMA_1,
538 GAUDI2_DCORE1_ENGINE_ID_MME,
539 GAUDI2_DCORE1_ENGINE_ID_TPC_0,
540 GAUDI2_DCORE1_ENGINE_ID_TPC_1,
541 GAUDI2_DCORE1_ENGINE_ID_TPC_2,
542 GAUDI2_DCORE1_ENGINE_ID_TPC_3,
543 GAUDI2_DCORE1_ENGINE_ID_TPC_4,
544 GAUDI2_DCORE1_ENGINE_ID_TPC_5,
545 GAUDI2_DCORE1_ENGINE_ID_DEC_0,
546 GAUDI2_DCORE1_ENGINE_ID_DEC_1,
547 GAUDI2_DCORE2_ENGINE_ID_EDMA_0,
548 GAUDI2_DCORE2_ENGINE_ID_EDMA_1,
549 GAUDI2_DCORE2_ENGINE_ID_MME,
550 GAUDI2_DCORE2_ENGINE_ID_TPC_0,
551 GAUDI2_DCORE2_ENGINE_ID_TPC_1,
552 GAUDI2_DCORE2_ENGINE_ID_TPC_2,
553 GAUDI2_DCORE2_ENGINE_ID_TPC_3,
554 GAUDI2_DCORE2_ENGINE_ID_TPC_4,
555 GAUDI2_DCORE2_ENGINE_ID_TPC_5,
556 GAUDI2_DCORE2_ENGINE_ID_DEC_0,
557 GAUDI2_DCORE2_ENGINE_ID_DEC_1,
558 GAUDI2_DCORE3_ENGINE_ID_EDMA_0,
559 GAUDI2_DCORE3_ENGINE_ID_EDMA_1,
560 GAUDI2_DCORE3_ENGINE_ID_MME,
561 GAUDI2_DCORE3_ENGINE_ID_TPC_0,
562 GAUDI2_DCORE3_ENGINE_ID_TPC_1,
563 GAUDI2_DCORE3_ENGINE_ID_TPC_2,
564 GAUDI2_DCORE3_ENGINE_ID_TPC_3,
565 GAUDI2_DCORE3_ENGINE_ID_TPC_4,
566 GAUDI2_DCORE3_ENGINE_ID_TPC_5,
567 GAUDI2_DCORE3_ENGINE_ID_DEC_0,
568 GAUDI2_DCORE3_ENGINE_ID_DEC_1,
569 GAUDI2_DCORE0_ENGINE_ID_TPC_6,
570 GAUDI2_ENGINE_ID_PDMA_0,
571 GAUDI2_ENGINE_ID_PDMA_1,
572 GAUDI2_ENGINE_ID_ROT_0,
573 GAUDI2_ENGINE_ID_ROT_1,
574 GAUDI2_PCIE_ENGINE_ID_DEC_0,
575 GAUDI2_PCIE_ENGINE_ID_DEC_1,
576 GAUDI2_ENGINE_ID_NIC0_0,
577 GAUDI2_ENGINE_ID_NIC0_1,
578 GAUDI2_ENGINE_ID_NIC1_0,
579 GAUDI2_ENGINE_ID_NIC1_1,
580 GAUDI2_ENGINE_ID_NIC2_0,
581 GAUDI2_ENGINE_ID_NIC2_1,
582 GAUDI2_ENGINE_ID_NIC3_0,
583 GAUDI2_ENGINE_ID_NIC3_1,
584 GAUDI2_ENGINE_ID_NIC4_0,
585 GAUDI2_ENGINE_ID_NIC4_1,
586 GAUDI2_ENGINE_ID_NIC5_0,
587 GAUDI2_ENGINE_ID_NIC5_1,
588 GAUDI2_ENGINE_ID_NIC6_0,
589 GAUDI2_ENGINE_ID_NIC6_1,
590 GAUDI2_ENGINE_ID_NIC7_0,
591 GAUDI2_ENGINE_ID_NIC7_1,
592 GAUDI2_ENGINE_ID_NIC8_0,
593 GAUDI2_ENGINE_ID_NIC8_1,
594 GAUDI2_ENGINE_ID_NIC9_0,
595 GAUDI2_ENGINE_ID_NIC9_1,
596 GAUDI2_ENGINE_ID_NIC10_0,
597 GAUDI2_ENGINE_ID_NIC10_1,
598 GAUDI2_ENGINE_ID_NIC11_0,
599 GAUDI2_ENGINE_ID_NIC11_1,
600 GAUDI2_ENGINE_ID_PCIE,
601 GAUDI2_ENGINE_ID_PSOC,
602 GAUDI2_ENGINE_ID_ARC_FARM,
603 GAUDI2_ENGINE_ID_KDMA,
604 GAUDI2_ENGINE_ID_SIZE
608 * ASIC specific PLL index
610 * Used to retrieve in frequency info of different IPs via
611 * HL_INFO_PLL_FREQUENCY under HL_IOCTL_INFO IOCTL. The enums need to be
612 * used as an index in struct hl_pll_frequency_info
615 enum hl_goya_pll_index {
626 enum hl_gaudi_pll_index {
627 HL_GAUDI_CPU_PLL = 0,
640 enum hl_gaudi2_pll_index {
641 HL_GAUDI2_CPU_PLL = 0,
657 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
658 * submitted to the GOYA's DMA QMAN. This attribute is not relevant
659 * to the H/W but the kernel driver use it to parse the packet's
660 * addresses and patch/validate them.
661 * @HL_DMA_HOST_TO_DRAM: DMA operation from Host memory to GOYA's DDR.
662 * @HL_DMA_HOST_TO_SRAM: DMA operation from Host memory to GOYA's SRAM.
663 * @HL_DMA_DRAM_TO_SRAM: DMA operation from GOYA's DDR to GOYA's SRAM.
664 * @HL_DMA_SRAM_TO_DRAM: DMA operation from GOYA's SRAM to GOYA's DDR.
665 * @HL_DMA_SRAM_TO_HOST: DMA operation from GOYA's SRAM to Host memory.
666 * @HL_DMA_DRAM_TO_HOST: DMA operation from GOYA's DDR to Host memory.
667 * @HL_DMA_DRAM_TO_DRAM: DMA operation from GOYA's DDR to GOYA's DDR.
668 * @HL_DMA_SRAM_TO_SRAM: DMA operation from GOYA's SRAM to GOYA's SRAM.
669 * @HL_DMA_ENUM_MAX: number of values in enum
671 enum hl_goya_dma_direction {
684 * enum hl_device_status - Device status information.
685 * @HL_DEVICE_STATUS_OPERATIONAL: Device is operational.
686 * @HL_DEVICE_STATUS_IN_RESET: Device is currently during reset.
687 * @HL_DEVICE_STATUS_MALFUNCTION: Device is unusable.
688 * @HL_DEVICE_STATUS_NEEDS_RESET: Device needs reset because auto reset was disabled.
689 * @HL_DEVICE_STATUS_IN_DEVICE_CREATION: Device is operational but its creation is still in
691 * @HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE: Device is currently during reset that was
692 * triggered because the user released the device
693 * @HL_DEVICE_STATUS_LAST: Last status.
695 enum hl_device_status {
696 HL_DEVICE_STATUS_OPERATIONAL,
697 HL_DEVICE_STATUS_IN_RESET,
698 HL_DEVICE_STATUS_MALFUNCTION,
699 HL_DEVICE_STATUS_NEEDS_RESET,
700 HL_DEVICE_STATUS_IN_DEVICE_CREATION,
701 HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE,
702 HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE
705 enum hl_server_type {
706 HL_SERVER_TYPE_UNKNOWN = 0,
707 HL_SERVER_GAUDI_HLS1 = 1,
708 HL_SERVER_GAUDI_HLS1H = 2,
709 HL_SERVER_GAUDI_TYPE1 = 3,
710 HL_SERVER_GAUDI_TYPE2 = 4,
711 HL_SERVER_GAUDI2_HLS2 = 5,
712 HL_SERVER_GAUDI2_TYPE1 = 7
716 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command
718 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
719 * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code
720 * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset
721 * HL_NOTIFIER_EVENT_CS_TIMEOUT - Indicates CS timeout error
722 * HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE - Indicates device is unavailable
723 * HL_NOTIFIER_EVENT_USER_ENGINE_ERR - Indicates device engine in error state
724 * HL_NOTIFIER_EVENT_GENERAL_HW_ERR - Indicates device HW error
725 * HL_NOTIFIER_EVENT_RAZWI - Indicates razwi happened
726 * HL_NOTIFIER_EVENT_PAGE_FAULT - Indicates page fault happened
727 * HL_NOTIFIER_EVENT_CRITICAL_HW_ERR - Indicates a HW error that requires SW abort and
729 * HL_NOTIFIER_EVENT_CRITICAL_FW_ERR - Indicates a FW error that requires SW abort and
732 #define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0)
733 #define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1)
734 #define HL_NOTIFIER_EVENT_DEVICE_RESET (1ULL << 2)
735 #define HL_NOTIFIER_EVENT_CS_TIMEOUT (1ULL << 3)
736 #define HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE (1ULL << 4)
737 #define HL_NOTIFIER_EVENT_USER_ENGINE_ERR (1ULL << 5)
738 #define HL_NOTIFIER_EVENT_GENERAL_HW_ERR (1ULL << 6)
739 #define HL_NOTIFIER_EVENT_RAZWI (1ULL << 7)
740 #define HL_NOTIFIER_EVENT_PAGE_FAULT (1ULL << 8)
741 #define HL_NOTIFIER_EVENT_CRITICL_HW_ERR (1ULL << 9)
742 #define HL_NOTIFIER_EVENT_CRITICL_FW_ERR (1ULL << 10)
744 /* Opcode for management ioctl
746 * HW_IP_INFO - Receive information about different IP blocks in the
748 * HL_INFO_HW_EVENTS - Receive an array describing how many times each event
749 * occurred since the last hard reset.
750 * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the
751 * specific context. This is relevant only for devices
752 * where the dram is managed by the kernel driver
753 * HL_INFO_HW_IDLE - Retrieve information about the idle status of each
755 * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't
756 * require an open context.
757 * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device
758 * over the last period specified by the user.
759 * The period can be between 100ms to 1s, in
760 * resolution of 100ms. The return value is a
761 * percentage of the utilization rate.
762 * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each
763 * event occurred since the driver was loaded.
764 * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate
765 * of the device in MHz. The maximum clock rate is
766 * configurable via sysfs parameter
767 * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset
768 * operations performed on the device since the last
769 * time the driver was loaded.
770 * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time
771 * for synchronization.
772 * HL_INFO_CS_COUNTERS - Retrieve command submission counters
773 * HL_INFO_PCI_COUNTERS - Retrieve PCI counters
774 * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason
775 * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore
776 * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption
777 * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency
778 * HL_INFO_POWER - Retrieve power information
779 * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls
780 * HL_INFO_DRAM_REPLACED_ROWS - Retrieve DRAM replaced rows info
781 * HL_INFO_DRAM_PENDING_ROWS - Retrieve DRAM pending rows num
782 * HL_INFO_LAST_ERR_OPEN_DEV_TIME - Retrieve timestamp of the last time the device was opened
783 * and CS timeout or razwi error occurred.
784 * HL_INFO_CS_TIMEOUT_EVENT - Retrieve CS timeout timestamp and its related CS sequence number.
785 * HL_INFO_RAZWI_EVENT - Retrieve parameters of razwi:
786 * Timestamp of razwi.
787 * The address which accessing it caused the razwi.
789 * Razwi cause, was it a page fault or MMU access error.
790 * May return 0 even though no new data is available, in that case
791 * timestamp will be 0.
792 * HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES - Retrieve valid page sizes for device memory allocation
793 * HL_INFO_SECURED_ATTESTATION - Retrieve attestation report of the boot.
794 * HL_INFO_REGISTER_EVENTFD - Register eventfd for event notifications.
795 * HL_INFO_UNREGISTER_EVENTFD - Unregister eventfd
796 * HL_INFO_GET_EVENTS - Retrieve the last occurred events
797 * HL_INFO_UNDEFINED_OPCODE_EVENT - Retrieve last undefined opcode error information.
798 * May return 0 even though no new data is available, in that case
799 * timestamp will be 0.
800 * HL_INFO_ENGINE_STATUS - Retrieve the status of all the h/w engines in the asic.
801 * HL_INFO_PAGE_FAULT_EVENT - Retrieve parameters of captured page fault.
802 * May return 0 even though no new data is available, in that case
803 * timestamp will be 0.
804 * HL_INFO_USER_MAPPINGS - Retrieve user mappings, captured after page fault event.
805 * HL_INFO_FW_GENERIC_REQ - Send generic request to FW.
806 * HL_INFO_HW_ERR_EVENT - Retrieve information on the reported HW error.
807 * May return 0 even though no new data is available, in that case
808 * timestamp will be 0.
809 * HL_INFO_FW_ERR_EVENT - Retrieve information on the reported FW error.
810 * May return 0 even though no new data is available, in that case
811 * timestamp will be 0.
813 #define HL_INFO_HW_IP_INFO 0
814 #define HL_INFO_HW_EVENTS 1
815 #define HL_INFO_DRAM_USAGE 2
816 #define HL_INFO_HW_IDLE 3
817 #define HL_INFO_DEVICE_STATUS 4
818 #define HL_INFO_DEVICE_UTILIZATION 6
819 #define HL_INFO_HW_EVENTS_AGGREGATE 7
820 #define HL_INFO_CLK_RATE 8
821 #define HL_INFO_RESET_COUNT 9
822 #define HL_INFO_TIME_SYNC 10
823 #define HL_INFO_CS_COUNTERS 11
824 #define HL_INFO_PCI_COUNTERS 12
825 #define HL_INFO_CLK_THROTTLE_REASON 13
826 #define HL_INFO_SYNC_MANAGER 14
827 #define HL_INFO_TOTAL_ENERGY 15
828 #define HL_INFO_PLL_FREQUENCY 16
829 #define HL_INFO_POWER 17
830 #define HL_INFO_OPEN_STATS 18
831 #define HL_INFO_DRAM_REPLACED_ROWS 21
832 #define HL_INFO_DRAM_PENDING_ROWS 22
833 #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23
834 #define HL_INFO_CS_TIMEOUT_EVENT 24
835 #define HL_INFO_RAZWI_EVENT 25
836 #define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26
837 #define HL_INFO_SECURED_ATTESTATION 27
838 #define HL_INFO_REGISTER_EVENTFD 28
839 #define HL_INFO_UNREGISTER_EVENTFD 29
840 #define HL_INFO_GET_EVENTS 30
841 #define HL_INFO_UNDEFINED_OPCODE_EVENT 31
842 #define HL_INFO_ENGINE_STATUS 32
843 #define HL_INFO_PAGE_FAULT_EVENT 33
844 #define HL_INFO_USER_MAPPINGS 34
845 #define HL_INFO_FW_GENERIC_REQ 35
846 #define HL_INFO_HW_ERR_EVENT 36
847 #define HL_INFO_FW_ERR_EVENT 37
849 #define HL_INFO_VERSION_MAX_LEN 128
850 #define HL_INFO_CARD_NAME_MAX_LEN 16
852 /* Maximum buffer size for retrieving engines status */
853 #define HL_ENGINES_DATA_MAX_SIZE SZ_1M
856 * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC
857 * @sram_base_address: The first SRAM physical base address that is free to be
859 * @dram_base_address: The first DRAM virtual or physical base address that is
860 * free to be used by the user.
861 * @dram_size: The DRAM size that is available to the user.
862 * @sram_size: The SRAM size that is available to the user.
863 * @num_of_events: The number of events that can be received from the f/w. This
864 * is needed so the user can what is the size of the h/w events
865 * array he needs to pass to the kernel when he wants to fetch
866 * the event counters.
867 * @device_id: PCI device ID of the ASIC.
868 * @module_id: Module ID of the ASIC for mezzanine cards in servers
870 * @decoder_enabled_mask: Bit-mask that represents which decoders are enabled.
871 * @first_available_interrupt_id: The first available interrupt ID for the user
872 * to be used when it works with user interrupts.
873 * Relevant for Gaudi2 and later.
874 * @server_type: Server type that the Gaudi ASIC is currently installed in.
875 * The value is according to enum hl_server_type
876 * @cpld_version: CPLD version on the board.
877 * @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs.
878 * @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs.
879 * @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs.
880 * @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler
882 * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant
883 * for Goya/Gaudi only.
884 * @dram_enabled: Whether the DRAM is enabled.
885 * @security_enabled: Whether security is enabled on device.
886 * @mme_master_slave_mode: Indicate whether the MME is working in master/slave
887 * configuration. Relevant for Greco and later.
888 * @cpucp_version: The CPUCP f/w version.
889 * @card_name: The card name as passed by the f/w.
890 * @tpc_enabled_mask_ext: Bit-mask that represents which TPCs are enabled.
891 * Relevant for Greco and later.
892 * @dram_page_size: The DRAM physical page size.
893 * @edma_enabled_mask: Bit-mask that represents which EDMAs are enabled.
894 * Relevant for Gaudi2 and later.
895 * @number_of_user_interrupts: The number of interrupts that are available to the userspace
896 * application to use. Relevant for Gaudi2 and later.
897 * @device_mem_alloc_default_page_size: default page size used in device memory allocation.
898 * @revision_id: PCI revision ID of the ASIC.
899 * @tpc_interrupt_id: interrupt id for TPC to use in order to raise events towards the host.
900 * @rotator_enabled_mask: Bit-mask that represents which rotators are enabled.
901 * Relevant for Gaudi3 and later.
902 * @engine_core_interrupt_reg_addr: interrupt register address for engine core to use
903 * in order to raise events toward FW.
904 * @reserved_dram_size: DRAM size reserved for driver and firmware.
906 struct hl_info_hw_ip_info {
907 __u64 sram_base_address;
908 __u64 dram_base_address;
914 __u32 decoder_enabled_mask;
915 __u16 first_available_interrupt_id;
918 __u32 psoc_pci_pll_nr;
919 __u32 psoc_pci_pll_nf;
920 __u32 psoc_pci_pll_od;
921 __u32 psoc_pci_pll_div_factor;
922 __u8 tpc_enabled_mask;
924 __u8 security_enabled;
925 __u8 mme_master_slave_mode;
926 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
927 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
928 __u64 tpc_enabled_mask_ext;
929 __u64 dram_page_size;
930 __u32 edma_enabled_mask;
931 __u16 number_of_user_interrupts;
935 __u64 device_mem_alloc_default_page_size;
941 __u16 tpc_interrupt_id;
942 __u32 rotator_enabled_mask;
944 __u64 engine_core_interrupt_reg_addr;
945 __u64 reserved_dram_size;
948 struct hl_info_dram_usage {
953 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 4
955 struct hl_info_hw_idle {
958 * Bitmask of busy engines.
959 * Bits definition is according to `enum <chip>_engine_id'.
961 __u32 busy_engines_mask;
964 * Extended Bitmask of busy engines.
965 * Bits definition is according to `enum <chip>_engine_id'.
967 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE];
970 struct hl_info_device_status {
975 struct hl_info_device_utilization {
980 struct hl_info_clk_rate {
981 __u32 cur_clk_rate_mhz;
982 __u32 max_clk_rate_mhz;
985 struct hl_info_reset_count {
986 __u32 hard_reset_cnt;
987 __u32 soft_reset_cnt;
990 struct hl_info_time_sync {
996 * struct hl_info_pci_counters - pci counters
997 * @rx_throughput: PCI rx throughput KBps
998 * @tx_throughput: PCI tx throughput KBps
999 * @replay_cnt: PCI replay counter
1001 struct hl_info_pci_counters {
1002 __u64 rx_throughput;
1003 __u64 tx_throughput;
1007 enum hl_clk_throttling_type {
1008 HL_CLK_THROTTLE_TYPE_POWER,
1009 HL_CLK_THROTTLE_TYPE_THERMAL,
1010 HL_CLK_THROTTLE_TYPE_MAX
1013 /* clk_throttling_reason masks */
1014 #define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER)
1015 #define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL)
1018 * struct hl_info_clk_throttle - clock throttling reason
1019 * @clk_throttling_reason: each bit represents a clk throttling reason
1020 * @clk_throttling_timestamp_us: represents CPU timestamp in microseconds of the start-event
1021 * @clk_throttling_duration_ns: the clock throttle time in nanosec
1023 struct hl_info_clk_throttle {
1024 __u32 clk_throttling_reason;
1026 __u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX];
1027 __u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX];
1031 * struct hl_info_energy - device energy information
1032 * @total_energy_consumption: total device energy consumption
1034 struct hl_info_energy {
1035 __u64 total_energy_consumption;
1038 #define HL_PLL_NUM_OUTPUTS 4
1040 struct hl_pll_frequency_info {
1041 __u16 output[HL_PLL_NUM_OUTPUTS];
1045 * struct hl_open_stats_info - device open statistics information
1046 * @open_counter: ever growing counter, increased on each successful dev open
1047 * @last_open_period_ms: duration (ms) device was open last time
1048 * @is_compute_ctx_active: Whether there is an active compute context executing
1049 * @compute_ctx_in_release: true if the current compute context is being released
1051 struct hl_open_stats_info {
1053 __u64 last_open_period_ms;
1054 __u8 is_compute_ctx_active;
1055 __u8 compute_ctx_in_release;
1060 * struct hl_power_info - power information
1061 * @power: power consumption
1063 struct hl_power_info {
1068 * struct hl_info_sync_manager - sync manager information
1069 * @first_available_sync_object: first available sob
1070 * @first_available_monitor: first available monitor
1071 * @first_available_cq: first available cq
1073 struct hl_info_sync_manager {
1074 __u32 first_available_sync_object;
1075 __u32 first_available_monitor;
1076 __u32 first_available_cq;
1081 * struct hl_info_cs_counters - command submission counters
1082 * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue
1083 * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue
1084 * @total_parsing_drop_cnt: total dropped due to error in packet parsing
1085 * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing
1086 * @total_queue_full_drop_cnt: total dropped due to queue full
1087 * @ctx_queue_full_drop_cnt: context dropped due to queue full
1088 * @total_device_in_reset_drop_cnt: total dropped due to device in reset
1089 * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset
1090 * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight
1091 * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight
1092 * @total_validation_drop_cnt: total dropped due to validation error
1093 * @ctx_validation_drop_cnt: context dropped due to validation error
1095 struct hl_info_cs_counters {
1096 __u64 total_out_of_mem_drop_cnt;
1097 __u64 ctx_out_of_mem_drop_cnt;
1098 __u64 total_parsing_drop_cnt;
1099 __u64 ctx_parsing_drop_cnt;
1100 __u64 total_queue_full_drop_cnt;
1101 __u64 ctx_queue_full_drop_cnt;
1102 __u64 total_device_in_reset_drop_cnt;
1103 __u64 ctx_device_in_reset_drop_cnt;
1104 __u64 total_max_cs_in_flight_drop_cnt;
1105 __u64 ctx_max_cs_in_flight_drop_cnt;
1106 __u64 total_validation_drop_cnt;
1107 __u64 ctx_validation_drop_cnt;
1111 * struct hl_info_last_err_open_dev_time - last error boot information.
1112 * @timestamp: timestamp of last time the device was opened and error occurred.
1114 struct hl_info_last_err_open_dev_time {
1119 * struct hl_info_cs_timeout_event - last CS timeout information.
1120 * @timestamp: timestamp when last CS timeout event occurred.
1121 * @seq: sequence number of last CS timeout event.
1123 struct hl_info_cs_timeout_event {
1128 #define HL_RAZWI_NA_ENG_ID U16_MAX
1129 #define HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR 128
1130 #define HL_RAZWI_READ BIT(0)
1131 #define HL_RAZWI_WRITE BIT(1)
1132 #define HL_RAZWI_LBW BIT(2)
1133 #define HL_RAZWI_HBW BIT(3)
1134 #define HL_RAZWI_RR BIT(4)
1135 #define HL_RAZWI_ADDR_DEC BIT(5)
1138 * struct hl_info_razwi_event - razwi information.
1139 * @timestamp: timestamp of razwi.
1140 * @addr: address which accessing it caused razwi.
1141 * @engine_id: engine id of the razwi initiator, if it was initiated by engine that does not
1142 * have engine id it will be set to HL_RAZWI_NA_ENG_ID. If there are several possible
1143 * engines which caused the razwi, it will hold all of them.
1144 * @num_of_possible_engines: contains number of possible engine ids. In some asics, razwi indication
1145 * might be common for several engines and there is no way to get the
1146 * exact engine. In this way, engine_id array will be filled with all
1147 * possible engines caused this razwi. Also, there might be possibility
1148 * in gaudi, where we don't indication on specific engine, in that case
1149 * the value of this parameter will be zero.
1150 * @flags: bitmask for additional data: HL_RAZWI_READ - razwi caused by read operation
1151 * HL_RAZWI_WRITE - razwi caused by write operation
1152 * HL_RAZWI_LBW - razwi caused by lbw fabric transaction
1153 * HL_RAZWI_HBW - razwi caused by hbw fabric transaction
1154 * HL_RAZWI_RR - razwi caused by range register
1155 * HL_RAZWI_ADDR_DEC - razwi caused by address decode error
1156 * Note: this data is not supported by all asics, in that case the relevant bits will not
1159 struct hl_info_razwi_event {
1162 __u16 engine_id[HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR];
1163 __u16 num_of_possible_engines;
1168 #define MAX_QMAN_STREAMS_INFO 4
1169 #define OPCODE_INFO_MAX_ADDR_SIZE 8
1171 * struct hl_info_undefined_opcode_event - info about last undefined opcode error
1172 * @timestamp: timestamp of the undefined opcode error
1173 * @cb_addr_streams: CB addresses (per stream) that are currently exists in the PQ
1174 * entries. In case all streams array entries are
1175 * filled with values, it means the execution was in Lower-CP.
1176 * @cq_addr: the address of the current handled command buffer
1177 * @cq_size: the size of the current handled command buffer
1178 * @cb_addr_streams_len: num of streams - actual len of cb_addr_streams array.
1179 * should be equal to 1 in case of undefined opcode
1180 * in Upper-CP (specific stream) and equal to 4 incase
1181 * of undefined opcode in Lower-CP.
1182 * @engine_id: engine-id that the error occurred on
1183 * @stream_id: the stream id the error occurred on. In case the stream equals to
1184 * MAX_QMAN_STREAMS_INFO it means the error occurred on a Lower-CP.
1186 struct hl_info_undefined_opcode_event {
1188 __u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE];
1191 __u32 cb_addr_streams_len;
1197 * struct hl_info_hw_err_event - info about HW error
1198 * @timestamp: timestamp of error occurrence
1199 * @event_id: The async event ID (specific to each device type).
1200 * @pad: size padding for u64 granularity.
1202 struct hl_info_hw_err_event {
1208 /* FW error definition for event_type in struct hl_info_fw_err_event */
1209 enum hl_info_fw_err_type {
1210 HL_INFO_FW_HEARTBEAT_ERR,
1211 HL_INFO_FW_REPORTED_ERR,
1215 * struct hl_info_fw_err_event - info about FW error
1216 * @timestamp: time-stamp of error occurrence
1217 * @err_type: The type of event as defined in hl_info_fw_err_type.
1218 * @event_id: The async event ID (specific to each device type, applicable only when event type is
1219 * HL_INFO_FW_REPORTED_ERR).
1220 * @pad: size padding for u64 granularity.
1222 struct hl_info_fw_err_event {
1230 * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information.
1231 * @page_order_bitmask: bitmap in which a set bit represents the order of the supported page size
1232 * (e.g. 0x2100000 means that 1MB and 32MB pages are supported).
1234 struct hl_info_dev_memalloc_page_sizes {
1235 __u64 page_order_bitmask;
1238 #define SEC_PCR_DATA_BUF_SZ 256
1239 #define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */
1240 #define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */
1241 #define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */
1242 #define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */
1245 * struct hl_info_sec_attest - attestation report of the boot
1246 * @nonce: number only used once. random number provided by host. this also passed to the quote
1247 * command as a qualifying data.
1248 * @pcr_quote_len: length of the attestation quote data (bytes)
1249 * @pub_data_len: length of the public data (bytes)
1250 * @certificate_len: length of the certificate (bytes)
1251 * @pcr_num_reg: number of PCR registers in the pcr_data array
1252 * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes)
1253 * @quote_sig_len: length of the attestation report signature (bytes)
1254 * @pcr_data: raw values of the PCR registers
1255 * @pcr_quote: attestation report data structure
1256 * @quote_sig: signature structure of the attestation report
1257 * @public_data: public key for the signed attestation
1258 * (outPublic + name + qualifiedName)
1259 * @certificate: certificate for the attestation signing key
1261 struct hl_info_sec_attest {
1263 __u16 pcr_quote_len;
1265 __u16 certificate_len;
1269 __u8 pcr_data[SEC_PCR_DATA_BUF_SZ];
1270 __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ];
1271 __u8 quote_sig[SEC_SIGNATURE_BUF_SZ];
1272 __u8 public_data[SEC_PUB_DATA_BUF_SZ];
1273 __u8 certificate[SEC_CERTIFICATE_BUF_SZ];
1278 * struct hl_page_fault_info - page fault information.
1279 * @timestamp: timestamp of page fault.
1280 * @addr: address which accessing it caused page fault.
1281 * @engine_id: engine id which caused the page fault, supported only in gaudi3.
1283 struct hl_page_fault_info {
1291 * struct hl_user_mapping - user mapping information.
1292 * @dev_va: device virtual address.
1293 * @size: virtual address mapping size.
1295 struct hl_user_mapping {
1308 * struct hl_info_args - Main structure to retrieve device related information.
1309 * @return_pointer: User space address of the relevant structure related to HL_INFO_* operation
1311 * @return_size: Size of the structure used in @return_pointer, just like "size" in "snprintf", it
1312 * limits how many bytes the kernel can write. For hw_events array, the size should be
1313 * hl_info_hw_ip_info.num_of_events * sizeof(__u32).
1314 * @op: Defines which type of information to be retrieved. Refer HL_INFO_* for details.
1315 * @dcore_id: DCORE id for which the information is relevant (for Gaudi refer to enum gaudi_dcores).
1316 * @ctx_id: Context ID of the user. Currently not in use.
1317 * @period_ms: Period value, in milliseconds, for utilization rate in range 100ms - 1000ms in 100 ms
1318 * resolution. Currently not in use.
1319 * @pll_index: Index as defined in hl_<asic type>_pll_index enumeration.
1320 * @eventfd: event file descriptor for event notifications.
1321 * @user_buffer_actual_size: Actual data size which was copied to user allocated buffer by the
1322 * driver. It is possible for the user to allocate buffer larger than
1323 * needed, hence updating this variable so user will know the exact amount
1324 * of bytes copied by the kernel to the buffer.
1325 * @sec_attest_nonce: Nonce number used for attestation report.
1326 * @array_size: Number of array members copied to user buffer.
1327 * Relevant for HL_INFO_USER_MAPPINGS info ioctl.
1328 * @fw_sub_opcode: generic requests sub opcodes.
1329 * @pad: Padding to 64 bit.
1331 struct hl_info_args {
1332 __u64 return_pointer;
1342 __u32 user_buffer_actual_size;
1343 __u32 sec_attest_nonce;
1345 __u32 fw_sub_opcode;
1351 /* Opcode to create a new command buffer */
1352 #define HL_CB_OP_CREATE 0
1353 /* Opcode to destroy previously created command buffer */
1354 #define HL_CB_OP_DESTROY 1
1355 /* Opcode to retrieve information about a command buffer */
1356 #define HL_CB_OP_INFO 2
1358 /* 2MB minus 32 bytes for 2xMSG_PROT */
1359 #define HL_MAX_CB_SIZE (0x200000 - 32)
1361 /* Indicates whether the command buffer should be mapped to the device's MMU */
1362 #define HL_CB_FLAGS_MAP 0x1
1364 /* Used with HL_CB_OP_INFO opcode to get the device va address for kernel mapped CB */
1365 #define HL_CB_FLAGS_GET_DEVICE_VA 0x2
1368 /* Handle of CB or 0 if we want to create one */
1373 /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that
1374 * will be allocated, regardless of this parameter's value, is PAGE_SIZE
1378 /* Context ID - Currently not in use */
1390 /* Information about CB */
1392 /* Usage count of CB */
1397 /* CB mapped address to device MMU */
1405 struct hl_cb_out out;
1408 /* HL_CS_CHUNK_FLAGS_ values
1410 * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB:
1411 * Indicates if the CB was allocated and mapped by userspace
1412 * (relevant to greco and above). User allocated CB is a command buffer,
1413 * allocated by the user, via malloc (or similar). After allocating the
1414 * CB, the user invokes - “memory ioctl” to map the user memory into a
1415 * device virtual address. The user provides this address via the
1416 * cb_handle field. The interface provides the ability to create a
1417 * large CBs, Which aren’t limited to “HL_MAX_CB_SIZE”. Therefore, it
1418 * increases the PCI-DMA queues throughput. This CB allocation method
1419 * also reduces the use of Linux DMA-able memory pool. Which are limited
1420 * and used by other Linux sub-systems.
1422 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1
1425 * This structure size must always be fixed to 64-bytes for backward
1428 struct hl_cs_chunk {
1431 * For external queue, this represents a Handle of CB on the
1433 * For internal queue in Goya, this represents an SRAM or
1434 * a DRAM address of the internal CB. In Gaudi, this might also
1435 * represent a mapped host address of the CB.
1438 * For H/W queue, this represents either a Handle of CB on the
1439 * Host, or an SRAM, a DRAM, or a mapped host address of the CB.
1441 * A mapped host address is in the device address space, after
1442 * a host address was mapped by the device MMU.
1446 /* Relevant only when HL_CS_FLAGS_WAIT or
1447 * HL_CS_FLAGS_COLLECTIVE_WAIT is set
1448 * This holds address of array of u64 values that contain
1449 * signal CS sequence numbers. The wait described by
1450 * this job will listen on all those signals
1451 * (wait event per signal)
1453 __u64 signal_seq_arr;
1456 * Relevant only when HL_CS_FLAGS_WAIT or
1457 * HL_CS_FLAGS_COLLECTIVE_WAIT is set
1458 * along with HL_CS_FLAGS_ENCAP_SIGNALS.
1459 * This is the CS sequence which has the encapsulated signals.
1461 __u64 encaps_signal_seq;
1464 /* Index of queue to put the CB on */
1469 * Size of command buffer with valid packets
1470 * Can be smaller then actual CB size
1474 /* Relevant only when HL_CS_FLAGS_WAIT or
1475 * HL_CS_FLAGS_COLLECTIVE_WAIT is set.
1476 * Number of entries in signal_seq_arr
1478 __u32 num_signal_seq_arr;
1480 /* Relevant only when HL_CS_FLAGS_WAIT or
1481 * HL_CS_FLAGS_COLLECTIVE_WAIT is set along
1482 * with HL_CS_FLAGS_ENCAP_SIGNALS
1483 * This set the signals range that the user want to wait for
1484 * out of the whole reserved signals range.
1485 * e.g if the signals range is 20, and user don't want
1486 * to wait for signal 8, so he set this offset to 7, then
1487 * he call the API again with 9 and so on till 20.
1489 __u32 encaps_signal_offset;
1492 /* HL_CS_CHUNK_FLAGS_* */
1493 __u32 cs_chunk_flags;
1495 /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set.
1496 * This holds the collective engine ID. The wait described by this job
1497 * will sync with this engine and with all NICs before completion.
1499 __u32 collective_engine_id;
1501 /* Align structure to 64 bytes */
1505 /* SIGNAL/WAIT/COLLECTIVE_WAIT flags are mutually exclusive */
1506 #define HL_CS_FLAGS_FORCE_RESTORE 0x1
1507 #define HL_CS_FLAGS_SIGNAL 0x2
1508 #define HL_CS_FLAGS_WAIT 0x4
1509 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8
1511 #define HL_CS_FLAGS_TIMESTAMP 0x20
1512 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40
1513 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80
1514 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100
1515 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200
1516 #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400
1519 * The encapsulated signals CS is merged into the existing CS ioctls.
1520 * In order to use this feature need to follow the below procedure:
1521 * 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY
1522 * the output of this API will be the SOB offset from CFG_BASE.
1523 * this address will be used to patch CB cmds to do the signaling for this
1524 * SOB by incrementing it's value.
1525 * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY
1526 * CS type, note that this might fail if out-of-sync happened to the SOB
1527 * value, in case other signaling request to the same SOB occurred between
1528 * reserve-unreserve calls.
1529 * 2. Use the staged CS to do the encapsulated signaling jobs.
1530 * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST
1531 * along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset
1532 * field. This offset allows app to wait on part of the reserved signals.
1533 * 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag
1534 * to wait for the encapsulated signals.
1536 #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800
1537 #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000
1538 #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000
1541 * The engine cores CS is merged into the existing CS ioctls.
1542 * Use it to control the engine cores mode.
1544 #define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0x4000
1547 * The flush HBW PCI writes is merged into the existing CS ioctls.
1548 * Used to flush all HBW PCI writes.
1549 * This is a blocking operation and for this reason the user shall not use
1550 * the return sequence number (which will be invalid anyway)
1552 #define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0x8000
1555 * The engines CS is merged into the existing CS ioctls.
1556 * Use it to control engines modes.
1558 #define HL_CS_FLAGS_ENGINES_COMMAND 0x10000
1560 #define HL_CS_STATUS_SUCCESS 0
1562 #define HL_MAX_JOBS_PER_CS 512
1565 * enum hl_engine_command - engine command
1567 * @HL_ENGINE_CORE_HALT: engine core halt
1568 * @HL_ENGINE_CORE_RUN: engine core run
1569 * @HL_ENGINE_STALL: user engine/s stall
1570 * @HL_ENGINE_RESUME: user engine/s resume
1572 enum hl_engine_command {
1573 HL_ENGINE_CORE_HALT = 1,
1574 HL_ENGINE_CORE_RUN = 2,
1575 HL_ENGINE_STALL = 3,
1576 HL_ENGINE_RESUME = 4,
1577 HL_ENGINE_COMMAND_MAX
1584 /* this holds address of array of hl_cs_chunk for restore phase */
1585 __u64 chunks_restore;
1587 /* holds address of array of hl_cs_chunk for execution phase */
1588 __u64 chunks_execute;
1591 /* Valid only when HL_CS_FLAGS_ENGINE_CORE_COMMAND is set */
1593 /* this holds address of array of uint32 for engine_cores */
1596 /* number of engine cores in engine_cores array */
1597 __u32 num_engine_cores;
1599 /* the core command to be sent towards engine cores */
1603 /* Valid only when HL_CS_FLAGS_ENGINES_COMMAND is set */
1605 /* this holds address of array of uint32 for engines */
1608 /* number of engines in engines array */
1611 /* the engine command to be sent towards engines */
1612 __u32 engine_command;
1618 * Sequence number of a staged submission CS
1619 * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and
1620 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset.
1625 * Encapsulated signals handle id
1626 * Valid for two flows:
1627 * 1. CS with encapsulated signals:
1628 * when HL_CS_FLAGS_STAGED_SUBMISSION and
1629 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST
1630 * and HL_CS_FLAGS_ENCAP_SIGNALS are set.
1631 * 2. unreserve signals:
1632 * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set.
1634 __u32 encaps_sig_handle_id;
1636 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */
1638 /* Encapsulated signals number */
1639 __u32 encaps_signals_count;
1641 /* Encapsulated signals queue index (stream) */
1642 __u32 encaps_signals_q_idx;
1646 /* Number of chunks in restore phase array. Maximum number is
1647 * HL_MAX_JOBS_PER_CS
1649 __u32 num_chunks_restore;
1651 /* Number of chunks in execution array. Maximum number is
1652 * HL_MAX_JOBS_PER_CS
1654 __u32 num_chunks_execute;
1656 /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT
1664 /* Context ID - Currently not in use */
1672 * seq holds the sequence number of the CS to pass to wait
1673 * ioctl. All values are valid except for 0 and ULLONG_MAX
1677 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */
1679 /* This is the reserved signal handle id */
1682 /* This is the signals count */
1691 * SOB base address offset
1692 * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY or HL_CS_FLAGS_SIGNAL is set
1694 __u32 sob_base_addr_offset;
1697 * Count of completed signals in SOB before current signal submission.
1698 * Valid only when (HL_CS_FLAGS_ENCAP_SIGNALS & HL_CS_FLAGS_STAGED_SUBMISSION)
1699 * or HL_CS_FLAGS_SIGNAL is set
1701 __u16 sob_count_before_submission;
1707 struct hl_cs_out out;
1710 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2
1711 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000
1712 #define HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT 0xFFF00000
1713 #define HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT 0xFFE00000
1714 #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4
1715 #define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10
1716 #define HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT 0x20
1718 #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32
1720 struct hl_wait_cs_in {
1724 * In case of wait_cs holds the CS sequence number.
1725 * In case of wait for multi CS hold a user pointer to
1726 * an array of CS sequence numbers
1729 /* Absolute timeout to wait for command submission
1737 /* User address for completion comparison.
1738 * upon interrupt, driver will compare the value pointed
1739 * by this address with the supplied target value.
1740 * in order not to perform any comparison, set address
1742 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set
1746 /* cq_counters_handle to a kernel mapped cb which contains
1748 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set
1750 __u64 cq_counters_handle;
1753 /* Target value for completion comparison */
1758 /* Context ID - Currently not in use */
1761 /* HL_WAIT_CS_FLAGS_*
1762 * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include
1763 * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK
1765 * in order to wait for any CQ interrupt, set interrupt value to
1766 * HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT.
1768 * in order to wait for any decoder interrupt, set interrupt value to
1769 * HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT.
1775 /* Multi CS API info- valid entries in multi-CS array */
1780 /* Absolute timeout to wait for an interrupt in microseconds.
1781 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set
1783 __u64 interrupt_timeout_us;
1787 * cq counter offset inside the counters cb pointed by cq_counters_handle above.
1788 * upon interrupt, driver will compare the value pointed
1789 * by this address (cq_counters_handle + cq_counters_offset)
1790 * with the supplied target value.
1791 * relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set
1793 __u64 cq_counters_offset;
1796 * Timestamp_handle timestamps buffer handle.
1797 * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set
1799 __u64 timestamp_handle;
1802 * Timestamp_offset is offset inside the timestamp buffer pointed by timestamp_handle above.
1803 * upon interrupt, if the cq reached the target value then driver will write
1804 * timestamp to this offset.
1805 * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set
1807 __u64 timestamp_offset;
1810 #define HL_WAIT_CS_STATUS_COMPLETED 0
1811 #define HL_WAIT_CS_STATUS_BUSY 1
1812 #define HL_WAIT_CS_STATUS_TIMEDOUT 2
1813 #define HL_WAIT_CS_STATUS_ABORTED 3
1815 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1
1816 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2
1818 struct hl_wait_cs_out {
1819 /* HL_WAIT_CS_STATUS_* */
1821 /* HL_WAIT_CS_STATUS_FLAG* */
1824 * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set
1825 * for wait_cs: timestamp of CS completion
1826 * for wait_multi_cs: timestamp of FIRST CS completion
1828 __s64 timestamp_nsec;
1829 /* multi CS completion bitmap */
1830 __u32 cs_completion_map;
1834 union hl_wait_cs_args {
1835 struct hl_wait_cs_in in;
1836 struct hl_wait_cs_out out;
1839 /* Opcode to allocate device memory */
1840 #define HL_MEM_OP_ALLOC 0
1842 /* Opcode to free previously allocated device memory */
1843 #define HL_MEM_OP_FREE 1
1845 /* Opcode to map host and device memory */
1846 #define HL_MEM_OP_MAP 2
1848 /* Opcode to unmap previously mapped host and device memory */
1849 #define HL_MEM_OP_UNMAP 3
1851 /* Opcode to map a hw block */
1852 #define HL_MEM_OP_MAP_BLOCK 4
1854 /* Opcode to create DMA-BUF object for an existing device memory allocation
1855 * and to export an FD of that DMA-BUF back to the caller
1857 #define HL_MEM_OP_EXPORT_DMABUF_FD 5
1859 /* Opcode to create timestamps pool for user interrupts registration support
1860 * The memory will be allocated by the kernel driver, A timestamp buffer which the user
1861 * will get handle to it for mmap, and another internal buffer used by the
1862 * driver for registration management
1863 * The memory will be freed when the user closes the file descriptor(ctx close)
1865 #define HL_MEM_OP_TS_ALLOC 6
1868 #define HL_MEM_CONTIGUOUS 0x1
1869 #define HL_MEM_SHARED 0x2
1870 #define HL_MEM_USERPTR 0x4
1871 #define HL_MEM_FORCE_HINT 0x8
1872 #define HL_MEM_PREFETCH 0x40
1875 * structure hl_mem_in - structure that handle input args for memory IOCTL
1876 * @union arg: union of structures to be used based on the input operation
1877 * @op: specify the requested memory operation (one of the HL_MEM_OP_* definitions).
1878 * @flags: flags for the memory operation (one of the HL_MEM_* definitions).
1879 * For the HL_MEM_OP_EXPORT_DMABUF_FD opcode, this field holds the DMA-BUF file/FD flags.
1880 * @ctx_id: context ID - currently not in use.
1881 * @num_of_elements: number of timestamp elements used only with HL_MEM_OP_TS_ALLOC opcode.
1886 * structure for device memory allocation (used with the HL_MEM_OP_ALLOC op)
1887 * @mem_size: memory size to allocate
1888 * @page_size: page size to use on allocation. when the value is 0 the default page
1889 * size will be taken.
1897 * structure for free-ing device memory (used with the HL_MEM_OP_FREE op)
1898 * @handle: handle returned from HL_MEM_OP_ALLOC
1905 * structure for mapping device memory (used with the HL_MEM_OP_MAP op)
1906 * @hint_addr: requested virtual address of mapped memory.
1907 * the driver will try to map the requested region to this hint
1908 * address, as long as the address is valid and not already mapped.
1909 * the user should check the returned address of the IOCTL to make
1910 * sure he got the hint address.
1911 * passing 0 here means that the driver will choose the address itself.
1912 * @handle: handle returned from HL_MEM_OP_ALLOC.
1920 * structure for mapping host memory (used with the HL_MEM_OP_MAP op)
1921 * @host_virt_addr: address of allocated host memory.
1922 * @hint_addr: requested virtual address of mapped memory.
1923 * the driver will try to map the requested region to this hint
1924 * address, as long as the address is valid and not already mapped.
1925 * the user should check the returned address of the IOCTL to make
1926 * sure he got the hint address.
1927 * passing 0 here means that the driver will choose the address itself.
1928 * @size: size of allocated host memory.
1931 __u64 host_virt_addr;
1937 * structure for mapping hw block (used with the HL_MEM_OP_MAP_BLOCK op)
1938 * @block_addr:HW block address to map, a handle and size will be returned
1939 * to the user and will be used to mmap the relevant block.
1940 * only addresses from configuration space are allowed.
1947 * structure for unmapping host memory (used with the HL_MEM_OP_UNMAP op)
1948 * @device_virt_addr: virtual address returned from HL_MEM_OP_MAP
1951 __u64 device_virt_addr;
1955 * structure for exporting DMABUF object (used with
1956 * the HL_MEM_OP_EXPORT_DMABUF_FD op)
1957 * @addr: for Gaudi1, the driver expects a physical address
1958 * inside the device's DRAM. this is because in Gaudi1
1959 * we don't have MMU that covers the device's DRAM.
1960 * for all other ASICs, the driver expects a device
1961 * virtual address that represents the start address of
1962 * a mapped DRAM memory area inside the device.
1963 * the address must be the same as was received from the
1964 * driver during a previous HL_MEM_OP_MAP operation.
1965 * @mem_size: size of memory to export.
1966 * @offset: for Gaudi1, this value must be 0. For all other ASICs,
1967 * the driver expects an offset inside of the memory area
1968 * describe by addr. the offset represents the start
1969 * address of that the exported dma-buf object describes.
1981 __u32 num_of_elements;
1987 * Used for HL_MEM_OP_MAP as the virtual address that was
1988 * assigned in the device VA space.
1989 * A value of 0 means the requested operation failed.
1991 __u64 device_virt_addr;
1994 * Used in HL_MEM_OP_ALLOC
1995 * This is the assigned handle for the allocated memory
2001 * Used in HL_MEM_OP_MAP_BLOCK.
2002 * This is the assigned handle for the mapped block
2007 * Used in HL_MEM_OP_MAP_BLOCK
2008 * This is the size of the mapped block
2015 /* Returned in HL_MEM_OP_EXPORT_DMABUF_FD. Represents the
2016 * DMA-BUF object that was created to describe a memory
2017 * allocation on the device's memory space. The FD should be
2018 * passed to the importer driver
2025 struct hl_mem_in in;
2026 struct hl_mem_out out;
2029 #define HL_DEBUG_MAX_AUX_VALUES 10
2031 struct hl_debug_params_etr {
2032 /* Address in memory to allocate buffer */
2033 __u64 buffer_address;
2035 /* Size of buffer to allocate */
2038 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */
2043 struct hl_debug_params_etf {
2044 /* Address in memory to allocate buffer */
2045 __u64 buffer_address;
2047 /* Size of buffer to allocate */
2050 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */
2055 struct hl_debug_params_stm {
2056 /* Two bit masks for HW event and Stimulus Port */
2060 /* Trace source ID */
2063 /* Frequency for the timestamp register */
2067 struct hl_debug_params_bmon {
2068 /* Two address ranges that the user can request to filter */
2075 /* Capture window configuration */
2079 /* Trace source ID */
2082 /* Control register */
2085 /* Two more address ranges that the user can request to filter */
2093 struct hl_debug_params_spmu {
2094 /* Event types selection */
2095 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES];
2097 /* Number of event types selection */
2098 __u32 event_types_num;
2100 /* TRC configuration register values */
2102 __u32 trc_ctrl_host_val;
2103 __u32 trc_en_host_val;
2106 /* Opcode for ETR component */
2107 #define HL_DEBUG_OP_ETR 0
2108 /* Opcode for ETF component */
2109 #define HL_DEBUG_OP_ETF 1
2110 /* Opcode for STM component */
2111 #define HL_DEBUG_OP_STM 2
2112 /* Opcode for FUNNEL component */
2113 #define HL_DEBUG_OP_FUNNEL 3
2114 /* Opcode for BMON component */
2115 #define HL_DEBUG_OP_BMON 4
2116 /* Opcode for SPMU component */
2117 #define HL_DEBUG_OP_SPMU 5
2118 /* Opcode for timestamp (deprecated) */
2119 #define HL_DEBUG_OP_TIMESTAMP 6
2120 /* Opcode for setting the device into or out of debug mode. The enable
2121 * variable should be 1 for enabling debug mode and 0 for disabling it
2123 #define HL_DEBUG_OP_SET_MODE 7
2125 struct hl_debug_args {
2127 * Pointer to user input structure.
2128 * This field is relevant to specific opcodes.
2131 /* Pointer to user output structure */
2133 /* Size of user input structure */
2135 /* Size of user output structure */
2140 * Register index in the component, taken from the debug_regs_index enum
2141 * in the various ASIC header files
2144 /* Enable/disable */
2146 /* Context ID - Currently not in use */
2151 * Various information operations such as:
2152 * - H/W IP information
2153 * - Current dram usage
2155 * The user calls this IOCTL with an opcode that describes the required
2156 * information. The user should supply a pointer to a user-allocated memory
2157 * chunk, which will be filled by the driver with the requested information.
2159 * The user supplies the maximum amount of size to copy into the user's memory,
2160 * in order to prevent data corruption in case of differences between the
2161 * definitions of structures in kernel and userspace, e.g. in case of old
2162 * userspace and new kernel driver
2164 #define HL_IOCTL_INFO \
2165 _IOWR('H', 0x01, struct hl_info_args)
2169 * - Request a Command Buffer
2170 * - Destroy a Command Buffer
2172 * The command buffers are memory blocks that reside in DMA-able address
2173 * space and are physically contiguous so they can be accessed by the device
2174 * directly. They are allocated using the coherent DMA API.
2176 * When creating a new CB, the IOCTL returns a handle of it, and the user-space
2177 * process needs to use that handle to mmap the buffer so it can access them.
2179 * In some instances, the device must access the command buffer through the
2180 * device's MMU, and thus its memory should be mapped. In these cases, user can
2181 * indicate the driver that such a mapping is required.
2182 * The resulting device virtual address will be used internally by the driver,
2183 * and won't be returned to user.
2186 #define HL_IOCTL_CB \
2187 _IOWR('H', 0x02, union hl_cb_args)
2190 * Command Submission
2192 * To submit work to the device, the user need to call this IOCTL with a set
2193 * of JOBS. That set of JOBS constitutes a CS object.
2194 * Each JOB will be enqueued on a specific queue, according to the user's input.
2195 * There can be more then one JOB per queue.
2197 * The CS IOCTL will receive two sets of JOBS. One set is for "restore" phase
2198 * and a second set is for "execution" phase.
2199 * The JOBS on the "restore" phase are enqueued only after context-switch
2200 * (or if its the first CS for this context). The user can also order the
2201 * driver to run the "restore" phase explicitly
2204 * There are two types of queues - external and internal. External queues
2205 * are DMA queues which transfer data from/to the Host. All other queues are
2206 * internal. The driver will get completion notifications from the device only
2207 * on JOBS which are enqueued in the external queues.
2210 * There is a single type of queue for all types of engines, either DMA engines
2211 * for transfers from/to the host or inside the device, or compute engines.
2212 * The driver will get completion notifications from the device for all queues.
2214 * For jobs on external queues, the user needs to create command buffers
2215 * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on
2216 * internal queues, the user needs to prepare a "command buffer" with packets
2217 * on either the device SRAM/DRAM or the host, and give the device address of
2218 * that buffer to the CS ioctl.
2219 * For jobs on H/W queues both options of command buffers are valid.
2221 * This IOCTL is asynchronous in regard to the actual execution of the CS. This
2222 * means it returns immediately after ALL the JOBS were enqueued on their
2223 * relevant queues. Therefore, the user mustn't assume the CS has been completed
2224 * or has even started to execute.
2226 * Upon successful enqueue, the IOCTL returns a sequence number which the user
2227 * can use with the "Wait for CS" IOCTL to check whether the handle's CS
2228 * non-internal JOBS have been completed. Note that if the CS has internal JOBS
2229 * which can execute AFTER the external JOBS have finished, the driver might
2230 * report that the CS has finished executing BEFORE the internal JOBS have
2231 * actually finished executing.
2233 * Even though the sequence number increments per CS, the user can NOT
2234 * automatically assume that if CS with sequence number N finished, then CS
2235 * with sequence number N-1 also finished. The user can make this assumption if
2236 * and only if CS N and CS N-1 are exactly the same (same CBs for the same
2239 #define HL_IOCTL_CS \
2240 _IOWR('H', 0x03, union hl_cs_args)
2243 * Wait for Command Submission
2245 * The user can call this IOCTL with a handle it received from the CS IOCTL
2246 * to wait until the handle's CS has finished executing. The user will wait
2247 * inside the kernel until the CS has finished or until the user-requested
2248 * timeout has expired.
2250 * If the timeout value is 0, the driver won't sleep at all. It will check
2251 * the status of the CS and return immediately
2253 * The return value of the IOCTL is a standard Linux error code. The possible
2256 * EINTR - Kernel waiting has been interrupted, e.g. due to OS signal
2257 * that the user process received
2258 * ETIMEDOUT - The CS has caused a timeout on the device
2259 * EIO - The CS was aborted (usually because the device was reset)
2260 * ENODEV - The device wants to do hard-reset (so user need to close FD)
2262 * The driver also returns a custom define in case the IOCTL call returned 0.
2263 * The define can be one of the following:
2265 * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully (0)
2266 * HL_WAIT_CS_STATUS_BUSY - The CS is still executing (0)
2267 * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device
2269 * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the
2270 * device was reset (EIO)
2273 #define HL_IOCTL_WAIT_CS \
2274 _IOWR('H', 0x04, union hl_wait_cs_args)
2278 * - Map host memory to device MMU
2279 * - Unmap host memory from device MMU
2281 * This IOCTL allows the user to map host memory to the device MMU
2283 * For host memory, the IOCTL doesn't allocate memory. The user is supposed
2284 * to allocate the memory in user-space (malloc/new). The driver pins the
2285 * physical pages (up to the allowed limit by the OS), assigns a virtual
2286 * address in the device VA space and initializes the device MMU.
2288 * There is an option for the user to specify the requested virtual address.
2291 #define HL_IOCTL_MEMORY \
2292 _IOWR('H', 0x05, union hl_mem_args)
2296 * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces
2298 * This IOCTL allows the user to get debug traces from the chip.
2300 * Before the user can send configuration requests of the various
2301 * debug/profile engines, it needs to set the device into debug mode.
2302 * This is because the debug/profile infrastructure is shared component in the
2303 * device and we can't allow multiple users to access it at the same time.
2305 * Once a user set the device into debug mode, the driver won't allow other
2306 * users to "work" with the device, i.e. open a FD. If there are multiple users
2307 * opened on the device, the driver won't allow any user to debug the device.
2309 * For each configuration request, the user needs to provide the register index
2310 * and essential data such as buffer address and size.
2312 * Once the user has finished using the debug/profile engines, he should
2313 * set the device into non-debug mode, i.e. disable debug mode.
2315 * The driver can decide to "kick out" the user if he abuses this interface.
2318 #define HL_IOCTL_DEBUG \
2319 _IOWR('H', 0x06, struct hl_debug_args)
2321 #define HL_COMMAND_START 0x01
2322 #define HL_COMMAND_END 0x07
2324 #endif /* HABANALABS_H_ */