armv8: fsl-lsch3: enable snoopable sata read and write
[platform/kernel/u-boot.git] / include / tsi148.h
1 /*
2  * (C) Copyright 2009 Reinhard Arlt, reinhard.arlt@esd-electronics.com
3  *
4  * base on universe.h by
5  *
6  * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 #ifndef _tsi148_h
12 #define _tsi148_h
13
14 #ifndef PCI_DEVICE_ID_TUNDRA_TSI148
15 #define PCI_DEVICE_ID_TUNDRA_TSI148 0x0148
16 #endif
17
18 typedef struct _TSI148 TSI148;
19 typedef struct _OUTBOUND OUTBOUND;
20 typedef struct _INBOUND  INBOUND;
21 typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
22
23 struct _OUTBOUND {
24         unsigned int otsau;                   /* 0x000 Outbound start       upper */
25         unsigned int otsal;                   /* 0x004 Outbouud start       lower */
26         unsigned int oteau;                   /* 0x008 Outbound end         upper */
27         unsigned int oteal;                   /* 0x00c Outbound end         lower */
28         unsigned int otofu;                   /* 0x010 Outbound translation upper */
29         unsigned int otofl;                   /* 0x014 Outbound translation lower */
30         unsigned int otbs;                    /* 0x018 Outbound translation 2eSST */
31         unsigned int otat;                    /* 0x01c Outbound translation attr  */
32 };
33
34 struct _INBOUND {
35         unsigned int itsau;                   /* 0x000 inbound  start       upper */
36         unsigned int itsal;                   /* 0x004 inbouud  start       lower */
37         unsigned int iteau;                   /* 0x008 inbound  end         upper */
38         unsigned int iteal;                   /* 0x00c inbound  end         lower */
39         unsigned int itofu;                   /* 0x010 inbound  translation upper */
40         unsigned int itofl;                   /* 0x014 inbound  translation lower */
41         unsigned int itat;                    /* 0x018 inbound  translation attr  */
42         unsigned int spare;                   /* 0x01c not used                   */
43 };
44
45 struct _TSI148 {
46         unsigned int pci_id;                  /* 0x000         */
47         unsigned int pci_csr;                 /* 0x004         */
48         unsigned int pci_class;               /* 0x008         */
49         unsigned int pci_misc0;               /* 0x00c         */
50         unsigned int pci_mbarl;               /* 0x010         */
51         unsigned int pci_mbarh;               /* 0x014         */
52         unsigned int spare0[(0x03c-0x018)/4]; /* 0x018         */
53         unsigned int pci_misc1;               /* 0x03c         */
54         unsigned int pci_pcixcap;             /* 0x040         */
55         unsigned int pci_pcixstat;            /* 0x044         */
56         unsigned int spare1[(0x100-0x048)/4]; /* 0x048         */
57         OUTBOUND     outbound[8];             /* 0x100         */
58         unsigned int viack[8];                /* 0x204         */
59         unsigned int rmwau;                   /* 0x220         */
60         unsigned int rmwal;                   /* 0x224         */
61         unsigned int rmwen;                   /* 0x228         */
62         unsigned int rmwc;                    /* 0x22c         */
63         unsigned int rmws;                    /* 0x230         */
64         unsigned int vmctrl;                  /* 0x234         */
65         unsigned int vctrl;                   /* 0x238         */
66         unsigned int vstat;                   /* 0x23c         */
67         unsigned int pcsr;                    /* 0x240         */
68         unsigned int spare2[3];               /* 0x244 - 0x24c */
69         unsigned int vmefl;                   /* 0x250         */
70         unsigned int spare3[3];               /* 0x254 - 0x25c */
71         unsigned int veau;                    /* 0x260         */
72         unsigned int veal;                    /* 0x264         */
73         unsigned int veat;                    /* 0x268         */
74         unsigned int spare4[1];               /* 0x26c         */
75         unsigned int edpau;                   /* 0x270         */
76         unsigned int edpal;                   /* 0x274         */
77         unsigned int edpxa;                   /* 0x278         */
78         unsigned int edpxs;                   /* 0x27c         */
79         unsigned int edpat;                   /* 0x280         */
80         unsigned int spare5[31];              /* 0x284 - 0x2fc */
81         INBOUND      inbound[8];              /* 0x100         */
82         unsigned int gbau;                    /* 0x400         */
83         unsigned int gbal;                    /* 0x404         */
84         unsigned int gcsrat;                  /* 0x408         */
85         unsigned int cbau;                    /* 0x40c         */
86         unsigned int cbal;                    /* 0x410         */
87         unsigned int crgat;                   /* 0x414         */
88         unsigned int crou;                    /* 0x418         */
89         unsigned int crol;                    /* 0x41c         */
90         unsigned int crat;                    /* 0x420         */
91         unsigned int lmbau;                   /* 0x424         */
92         unsigned int lmbal;                   /* 0x428         */
93         unsigned int lmat;                    /* 0x42c         */
94         unsigned int r64bcu;                  /* 0x430         */
95         unsigned int r64bcl;                  /* 0x434         */
96         unsigned int bpgtr;                   /* 0x438         */
97         unsigned int bpctr;                   /* 0x43c         */
98         unsigned int vicr;                    /* 0x440         */
99         unsigned int spare6[1];               /* 0x444         */
100         unsigned int inten;                   /* 0x448         */
101         unsigned int inteo;                   /* 0x44c         */
102         unsigned int ints;                    /* 0x450         */
103         unsigned int intc;                    /* 0x454         */
104         unsigned int intm1;                   /* 0x458         */
105         unsigned int intm2;                   /* 0x45c         */
106         unsigned int spare7[40];              /* 0x460 - 0x4fc */
107         unsigned int dctl0;                   /* 0x500         */
108         unsigned int dsta0;                   /* 0x504         */
109         unsigned int dcsau0;                  /* 0x508         */
110         unsigned int dcsal0;                  /* 0x50c         */
111         unsigned int dcdau0;                  /* 0x510         */
112         unsigned int dcdal0;                  /* 0x514         */
113         unsigned int dclau0;                  /* 0x518         */
114         unsigned int dclal0;                  /* 0x51c         */
115         unsigned int dsau0;                   /* 0x520         */
116         unsigned int dsal0;                   /* 0x524         */
117         unsigned int ddau0;                   /* 0x528         */
118         unsigned int ddal0;                   /* 0x52c         */
119         unsigned int dsat0;                   /* 0x530         */
120         unsigned int ddat0;                   /* 0x534         */
121         unsigned int dnlau0;                  /* 0x538         */
122         unsigned int dnlal0;                  /* 0x53c         */
123         unsigned int dcnt0;                   /* 0x540         */
124         unsigned int ddbs0;                   /* 0x544         */
125         unsigned int r20[14];                 /* 0x548 - 0x57c */
126         unsigned int dctl1;                   /* 0x580         */
127         unsigned int dsta1;                   /* 0x584         */
128         unsigned int dcsau1;                  /* 0x588         */
129         unsigned int dcsal1;                  /* 0x58c         */
130         unsigned int dcdau1;                  /* 0x590         */
131         unsigned int dcdal1;                  /* 0x594         */
132         unsigned int dclau1;                  /* 0x598         */
133         unsigned int dclal1;                  /* 0x59c         */
134         unsigned int dsau1;                   /* 0x5a0         */
135         unsigned int dsal1;                   /* 0x5a4         */
136         unsigned int ddau1;                   /* 0x5a8         */
137         unsigned int ddal1;                   /* 0x5ac         */
138         unsigned int dsat1;                   /* 0x5b0         */
139         unsigned int ddat1;                   /* 0x5b4         */
140         unsigned int dnlau1;                  /* 0x5b8         */
141         unsigned int dnlal1;                  /* 0x5bc         */
142         unsigned int dcnt1;                   /* 0x5c0         */
143         unsigned int ddbs1;                   /* 0x5c4         */
144         unsigned int r21[14];                 /* 0x5c8 - 0x5fc */
145         unsigned int devi_veni_2;             /* 0x600         */
146         unsigned int gctrl_ga_revid;          /* 0x604         */
147         unsigned int semaphore0_1_2_3;        /* 0x608         */
148         unsigned int semaphore4_5_6_7;        /* 0x60c         */
149         unsigned int mbox0;                   /* 0x610         */
150         unsigned int mbox1;                   /* 0x614         */
151         unsigned int mbox2;                   /* 0x618         */
152         unsigned int mbox3;                   /* 0x61c         */
153         unsigned int r22[629];                /* 0x620 - 0xff0 */
154         unsigned int csrbcr;                  /* 0xff4         */
155         unsigned int csrbsr;                  /* 0xff8         */
156         unsigned int cbar;                    /* 0xffc         */
157 };
158
159 #define IRQ_VOWN        0x0001
160 #define IRQ_VIRQ1       0x0002
161 #define IRQ_VIRQ2       0x0004
162 #define IRQ_VIRQ3       0x0008
163 #define IRQ_VIRQ4       0x0010
164 #define IRQ_VIRQ5       0x0020
165 #define IRQ_VIRQ6       0x0040
166 #define IRQ_VIRQ7       0x0080
167 #define IRQ_DMA         0x0100
168 #define IRQ_LERR        0x0200
169 #define IRQ_VERR        0x0400
170 #define IRQ_res         0x0800
171 #define IRQ_IACK        0x1000
172 #define IRQ_SWINT       0x2000
173 #define IRQ_SYSFAIL     0x4000
174 #define IRQ_ACFAIL      0x8000
175
176 struct _TDMA_CMD_PACKET {
177         unsigned int dctl;   /* DMA Control         */
178         unsigned int dtbc;   /* Transfer Byte Count */
179         unsigned int dlv;    /* PCI Address         */
180         unsigned int res1;   /* Reserved            */
181         unsigned int dva;    /* Vme Address         */
182         unsigned int res2;   /* Reserved            */
183         unsigned int dcpp;   /* Pointer to Numed Cmd Packet with rPN */
184         unsigned int res3;   /* Reserved                             */
185 };
186
187 #define VME_AM_A16              0x01
188 #define VME_AM_A24              0x02
189 #define VME_AM_A32              0x03
190 #define VME_AM_Axx              0x03
191 #define VME_AM_USR              0x04
192 #define VME_AM_SUP              0x08
193 #define VME_AM_DATA             0x10
194 #define VME_AM_PROG             0x20
195 #define VME_AM_Mxx              (VME_AM_DATA | VME_AM_PROG)
196
197 #define VME_FLAG_D8             0x01
198 #define VME_FLAG_D16            0x02
199 #define VME_FLAG_D32            0x03
200 #define VME_FLAG_Dxx            0x03
201
202 #endif