1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Defines APIs and structures that allow software to interact with a
6 * Copyright (c) 2020 Linaro
7 * Copyright (c) 2018 Bootlin
9 * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
11 * Author: Miquel Raynal <miquel.raynal@bootlin.com>
17 #include <tpm-common.h>
21 #define TPM2_DIGEST_LEN 32
23 #define TPM2_SHA1_DIGEST_SIZE 20
24 #define TPM2_SHA256_DIGEST_SIZE 32
25 #define TPM2_SHA384_DIGEST_SIZE 48
26 #define TPM2_SHA512_DIGEST_SIZE 64
27 #define TPM2_SM3_256_DIGEST_SIZE 32
29 #define TPM2_MAX_PCRS 32
30 #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
31 #define TPM2_MAX_CAP_BUFFER 1024
32 #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
33 sizeof(u32)) / sizeof(struct tpms_tagged_property))
36 * We deviate from this draft of the specification by increasing the value of
37 * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
38 * implementations that have enabled a larger than typical number of PCR
39 * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
40 * in a future revision of the specification.
42 #define TPM2_NUM_PCR_BANKS 16
44 /* Definition of (UINT32) TPM2_CAP Constants */
45 #define TPM2_CAP_PCRS 0x00000005U
46 #define TPM2_CAP_TPM_PROPERTIES 0x00000006U
48 /* Definition of (UINT32) TPM2_PT Constants */
49 #define TPM2_PT_GROUP (u32)(0x00000100)
50 #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
51 #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
52 #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
53 #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
54 #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
57 #define EV_POST_CODE ((u32)0x00000001)
58 #define EV_NO_ACTION ((u32)0x00000003)
59 #define EV_SEPARATOR ((u32)0x00000004)
60 #define EV_S_CRTM_CONTENTS ((u32)0x00000007)
61 #define EV_S_CRTM_VERSION ((u32)0x00000008)
62 #define EV_CPU_MICROCODE ((u32)0x00000009)
63 #define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
65 /* TPMS_TAGGED_PROPERTY Structure */
66 struct tpms_tagged_property {
71 /* TPMS_PCR_SELECTION Structure */
72 struct tpms_pcr_selection {
75 u8 pcr_select[TPM2_PCR_SELECT_MAX];
78 /* TPML_PCR_SELECTION Structure */
79 struct tpml_pcr_selection {
81 struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
84 /* TPML_TAGGED_TPM_PROPERTY Structure */
85 struct tpml_tagged_tpm_property {
87 struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
90 /* TPMU_CAPABILITIES Union */
91 union tpmu_capabilities {
93 * Non exhaustive. Only added the structs needed for our
96 struct tpml_pcr_selection assigned_pcr;
97 struct tpml_tagged_tpm_property tpm_properties;
100 /* TPMS_CAPABILITY_DATA Structure */
101 struct tpms_capability_data {
103 union tpmu_capabilities data;
107 * SHA1 Event Log Entry Format
109 * @pcr_index: PCRIndex event extended to
110 * @event_type: Type of event (see EFI specs)
111 * @digest: Value extended into PCR index
112 * @event_size: Size of event
115 struct tcg_pcr_event {
118 u8 digest[TPM2_SHA1_DIGEST_SIZE];
124 * Definition of TPMU_HA Union
127 u8 sha1[TPM2_SHA1_DIGEST_SIZE];
128 u8 sha256[TPM2_SHA256_DIGEST_SIZE];
129 u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
130 u8 sha384[TPM2_SHA384_DIGEST_SIZE];
131 u8 sha512[TPM2_SHA512_DIGEST_SIZE];
135 * Definition of TPMT_HA Structure
137 * @hash_alg: Hash algorithm defined in enum tpm2_algorithms
138 * @digest: Digest value for a given algorithm
142 union tmpu_ha digest;
146 * Definition of TPML_DIGEST_VALUES Structure
148 * @count: Number of algorithms supported by hardware
149 * @digests: struct for algorithm id and hash value
151 struct tpml_digest_values {
153 struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
157 * Crypto Agile Log Entry Format
159 * @pcr_index: PCRIndex event extended to
160 * @event_type: Type of event
161 * @digests: List of digestsextended to PCR index
162 * @event_size: Size of the event data
165 struct tcg_pcr_event2 {
168 struct tpml_digest_values digests;
174 * TPM2 Structure Tags for command/response buffers.
176 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
177 * @TPM2_ST_SESSIONS: the command needs an authentication.
179 enum tpm2_structures {
180 TPM2_ST_NO_SESSIONS = 0x8001,
181 TPM2_ST_SESSIONS = 0x8002,
185 * TPM2 type of boolean.
193 * TPM2 startup values.
195 * @TPM2_SU_CLEAR: reset the internal state.
196 * @TPM2_SU_STATE: restore saved state (if any).
198 enum tpm2_startup_types {
199 TPM2_SU_CLEAR = 0x0000,
200 TPM2_SU_STATE = 0x0001,
204 * TPM2 permanent handles.
206 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
207 * @TPM2_RS_PW: indicates a password.
208 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
209 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
210 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
213 TPM2_RH_OWNER = 0x40000001,
214 TPM2_RS_PW = 0x40000009,
215 TPM2_RH_LOCKOUT = 0x4000000A,
216 TPM2_RH_ENDORSEMENT = 0x4000000B,
217 TPM2_RH_PLATFORM = 0x4000000C,
221 * TPM2 command codes used at the beginning of a buffer, gives the command.
223 * @TPM2_CC_STARTUP: TPM2_Startup().
224 * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
225 * @TPM2_CC_CLEAR: TPM2_Clear().
226 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
227 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
228 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
229 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
230 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
231 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
232 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
233 * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
234 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
235 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
237 enum tpm2_command_codes {
238 TPM2_CC_STARTUP = 0x0144,
239 TPM2_CC_SELF_TEST = 0x0143,
240 TPM2_CC_CLEAR = 0x0126,
241 TPM2_CC_CLEARCONTROL = 0x0127,
242 TPM2_CC_HIERCHANGEAUTH = 0x0129,
243 TPM2_CC_NV_DEFINE_SPACE = 0x012a,
244 TPM2_CC_PCR_SETAUTHPOL = 0x012C,
245 TPM2_CC_NV_WRITE = 0x0137,
246 TPM2_CC_NV_WRITELOCK = 0x0138,
247 TPM2_CC_DAM_RESET = 0x0139,
248 TPM2_CC_DAM_PARAMETERS = 0x013A,
249 TPM2_CC_NV_READ = 0x014E,
250 TPM2_CC_GET_CAPABILITY = 0x017A,
251 TPM2_CC_GET_RANDOM = 0x017B,
252 TPM2_CC_PCR_READ = 0x017E,
253 TPM2_CC_PCR_EXTEND = 0x0182,
254 TPM2_CC_PCR_SETAUTHVAL = 0x0183,
260 enum tpm2_return_codes {
261 TPM2_RC_SUCCESS = 0x0000,
262 TPM2_RC_BAD_TAG = 0x001E,
263 TPM2_RC_FMT1 = 0x0080,
264 TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
265 TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
266 TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
267 TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
268 TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
269 TPM2_RC_VER1 = 0x0100,
270 TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
271 TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
272 TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
273 TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
274 TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
275 TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
276 TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
277 TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
278 TPM2_RC_WARN = 0x0900,
279 TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
280 TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
281 TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
287 enum tpm2_algorithms {
288 TPM2_ALG_SHA1 = 0x04,
290 TPM2_ALG_SHA256 = 0x0B,
291 TPM2_ALG_SHA384 = 0x0C,
292 TPM2_ALG_SHA512 = 0x0D,
293 TPM2_ALG_NULL = 0x10,
294 TPM2_ALG_SM3_256 = 0x12,
297 /* NV index attributes */
298 enum tpm_index_attrs {
299 TPMA_NV_PPWRITE = 1UL << 0,
300 TPMA_NV_OWNERWRITE = 1UL << 1,
301 TPMA_NV_AUTHWRITE = 1UL << 2,
302 TPMA_NV_POLICYWRITE = 1UL << 3,
303 TPMA_NV_COUNTER = 1UL << 4,
304 TPMA_NV_BITS = 1UL << 5,
305 TPMA_NV_EXTEND = 1UL << 6,
306 TPMA_NV_POLICY_DELETE = 1UL << 10,
307 TPMA_NV_WRITELOCKED = 1UL << 11,
308 TPMA_NV_WRITEALL = 1UL << 12,
309 TPMA_NV_WRITEDEFINE = 1UL << 13,
310 TPMA_NV_WRITE_STCLEAR = 1UL << 14,
311 TPMA_NV_GLOBALLOCK = 1UL << 15,
312 TPMA_NV_PPREAD = 1UL << 16,
313 TPMA_NV_OWNERREAD = 1UL << 17,
314 TPMA_NV_AUTHREAD = 1UL << 18,
315 TPMA_NV_POLICYREAD = 1UL << 19,
316 TPMA_NV_NO_DA = 1UL << 25,
317 TPMA_NV_ORDERLY = 1UL << 26,
318 TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
319 TPMA_NV_READLOCKED = 1UL << 28,
320 TPMA_NV_WRITTEN = 1UL << 29,
321 TPMA_NV_PLATFORMCREATE = 1UL << 30,
322 TPMA_NV_READ_STCLEAR = 1UL << 31,
324 TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
325 TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
326 TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
327 TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
331 TPM_ACCESS_VALID = 1 << 7,
332 TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
333 TPM_ACCESS_REQUEST_PENDING = 1 << 2,
334 TPM_ACCESS_REQUEST_USE = 1 << 1,
335 TPM_ACCESS_ESTABLISHMENT = 1 << 0,
339 TPM_STS_FAMILY_SHIFT = 26,
340 TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
341 TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
342 TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
343 TPM_STS_COMMAND_CANCEL = 1 << 24,
344 TPM_STS_BURST_COUNT_SHIFT = 8,
345 TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
346 TPM_STS_VALID = 1 << 7,
347 TPM_STS_COMMAND_READY = 1 << 6,
349 TPM_STS_DATA_AVAIL = 1 << 4,
350 TPM_STS_DATA_EXPECT = 1 << 3,
351 TPM_STS_SELF_TEST_DONE = 1 << 2,
352 TPM_STS_RESPONSE_RETRY = 1 << 1,
356 TPM_CMD_COUNT_OFFSET = 2,
357 TPM_CMD_ORDINAL_OFFSET = 6,
358 TPM_MAX_BUF_SIZE = 1260,
362 /* Secure storage for firmware settings */
366 TPM_HT_POLICY_SESSION,
369 HR_PCR = TPM_HT_PCR << HR_SHIFT,
370 HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
371 HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
372 HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
376 * Issue a TPM2_Startup command.
379 * @mode TPM startup mode
381 * @return code of the operation
383 u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
386 * Issue a TPM2_SelfTest command.
389 * @full_test Asking to perform all tests or only the untested ones
391 * @return code of the operation
393 u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
396 * Issue a TPM2_Clear command.
401 * @pw_sz Length of the password
403 * @return code of the operation
405 u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
406 const ssize_t pw_sz);
409 * Issue a TPM_NV_DefineSpace command
411 * This allows a space to be defined with given attributes and policy
414 * @space_index index of the area
415 * @space_size size of area in bytes
416 * @nv_attributes TPM_NV_ATTRIBUTES of the area
417 * @nv_policy policy to use
418 * @nv_policy_size size of the policy
419 * @return return code of the operation
421 u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
422 size_t space_size, u32 nv_attributes,
423 const u8 *nv_policy, size_t nv_policy_size);
426 * Issue a TPM2_PCR_Extend command.
429 * @index Index of the PCR
430 * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
431 * @digest Value representing the event to be recorded
432 * @digest_len len of the hash
434 * @return code of the operation
436 u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
437 const u8 *digest, u32 digest_len);
440 * Read data from the secure storage
443 * @index Index of data to read
444 * @data Place to put data
445 * @count Number of bytes of data
446 * @return code of the operation
448 u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
451 * Write data to the secure storage
454 * @index Index of data to write
455 * @data Data to write
456 * @count Number of bytes of data
457 * @return code of the operation
459 u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
463 * Issue a TPM2_PCR_Read command.
466 * @idx Index of the PCR
467 * @idx_min_sz Minimum size in bytes of the pcrSelect array
468 * @data Output buffer for contents of the named PCR
469 * @updates Optional out parameter: number of updates for this PCR
471 * @return code of the operation
473 u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
474 void *data, unsigned int *updates);
477 * Issue a TPM2_GetCapability command. This implementation is limited
478 * to query property index that is 4-byte wide.
481 * @capability Partition of capabilities
482 * @property Further definition of capability, limited to be 4 bytes wide
483 * @buf Output buffer for capability information
484 * @prop_count Size of output buffer
486 * @return code of the operation
488 u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
489 void *buf, size_t prop_count);
492 * Issue a TPM2_DictionaryAttackLockReset command.
496 * @pw_sz Length of the password
498 * @return code of the operation
500 u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
503 * Issue a TPM2_DictionaryAttackParameters command.
507 * @pw_sz Length of the password
508 * @max_tries Count of authorizations before lockout
509 * @recovery_time Time before decrementation of the failure count
510 * @lockout_recovery Time to wait after a lockout
512 * @return code of the operation
514 u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
515 const ssize_t pw_sz, unsigned int max_tries,
516 unsigned int recovery_time,
517 unsigned int lockout_recovery);
520 * Issue a TPM2_HierarchyChangeAuth command.
524 * @newpw New password
525 * @newpw_sz Length of the new password
526 * @oldpw Old password
527 * @oldpw_sz Length of the old password
529 * @return code of the operation
531 int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
532 const ssize_t newpw_sz, const char *oldpw,
533 const ssize_t oldpw_sz);
536 * Issue a TPM_PCR_SetAuthPolicy command.
539 * @pw Platform password
540 * @pw_sz Length of the password
541 * @index Index of the PCR
542 * @digest New key to access the PCR
544 * @return code of the operation
546 u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
547 const ssize_t pw_sz, u32 index, const char *key);
550 * Issue a TPM_PCR_SetAuthValue command.
553 * @pw Platform password
554 * @pw_sz Length of the password
555 * @index Index of the PCR
556 * @digest New key to access the PCR
557 * @key_sz Length of the new key
559 * @return code of the operation
561 u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
562 const ssize_t pw_sz, u32 index, const char *key,
563 const ssize_t key_sz);
566 * Issue a TPM2_GetRandom command.
569 * @param data output buffer for the random bytes
570 * @param count size of output buffer
572 * @return return code of the operation
574 u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
577 * Lock data in the TPM
579 * Once locked the data cannot be written until after a reboot
582 * @index Index of data to lock
583 * @return code of the operation
585 u32 tpm2_write_lock(struct udevice *dev, u32 index);
587 #endif /* __TPM_V2_H */