1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Defines APIs and structures that allow software to interact with a
6 * Copyright (c) 2020 Linaro
7 * Copyright (c) 2018 Bootlin
9 * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
11 * Author: Miquel Raynal <miquel.raynal@bootlin.com>
17 #include <tpm-common.h>
21 #define TPM2_DIGEST_LEN 32
23 #define TPM2_SHA1_DIGEST_SIZE 20
24 #define TPM2_SHA256_DIGEST_SIZE 32
25 #define TPM2_SHA384_DIGEST_SIZE 48
26 #define TPM2_SHA512_DIGEST_SIZE 64
27 #define TPM2_SM3_256_DIGEST_SIZE 32
29 #define TPM2_MAX_PCRS 32
30 #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
31 #define TPM2_MAX_CAP_BUFFER 1024
32 #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
33 sizeof(u32)) / sizeof(struct tpms_tagged_property))
35 #define TPM2_HDR_LEN 10
38 * We deviate from this draft of the specification by increasing the value of
39 * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
40 * implementations that have enabled a larger than typical number of PCR
41 * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
42 * in a future revision of the specification.
44 #define TPM2_NUM_PCR_BANKS 16
46 /* Definition of (UINT32) TPM2_CAP Constants */
47 #define TPM2_CAP_PCRS 0x00000005U
48 #define TPM2_CAP_TPM_PROPERTIES 0x00000006U
50 /* Definition of (UINT32) TPM2_PT Constants */
51 #define TPM2_PT_GROUP (u32)(0x00000100)
52 #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
53 #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
54 #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
55 #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
56 #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
60 * "TCG Server Management Domain Firmware Profile Specification",
61 * rev 1.00, 2020-05-01
63 #define EV_POST_CODE ((u32)0x00000001)
64 #define EV_NO_ACTION ((u32)0x00000003)
65 #define EV_SEPARATOR ((u32)0x00000004)
66 #define EV_ACTION ((u32)0x00000005)
67 #define EV_TAG ((u32)0x00000006)
68 #define EV_S_CRTM_CONTENTS ((u32)0x00000007)
69 #define EV_S_CRTM_VERSION ((u32)0x00000008)
70 #define EV_CPU_MICROCODE ((u32)0x00000009)
71 #define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
72 #define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
73 #define EV_COMPACT_HASH ((u32)0x0000000C)
77 * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
78 * rev 1.04, June 3, 2019
80 #define EV_EFI_EVENT_BASE ((u32)0x80000000)
81 #define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
82 #define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
83 #define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
84 #define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
85 #define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
86 #define EV_EFI_GPT_EVENT ((u32)0x80000006)
87 #define EV_EFI_ACTION ((u32)0x80000007)
88 #define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
89 #define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
90 #define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
91 #define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
93 /* TPMS_TAGGED_PROPERTY Structure */
94 struct tpms_tagged_property {
99 /* TPMS_PCR_SELECTION Structure */
100 struct tpms_pcr_selection {
103 u8 pcr_select[TPM2_PCR_SELECT_MAX];
106 /* TPML_PCR_SELECTION Structure */
107 struct tpml_pcr_selection {
109 struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
112 /* TPML_TAGGED_TPM_PROPERTY Structure */
113 struct tpml_tagged_tpm_property {
115 struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
118 /* TPMU_CAPABILITIES Union */
119 union tpmu_capabilities {
121 * Non exhaustive. Only added the structs needed for our
124 struct tpml_pcr_selection assigned_pcr;
125 struct tpml_tagged_tpm_property tpm_properties;
128 /* TPMS_CAPABILITY_DATA Structure */
129 struct tpms_capability_data {
131 union tpmu_capabilities data;
135 * SHA1 Event Log Entry Format
137 * @pcr_index: PCRIndex event extended to
138 * @event_type: Type of event (see EFI specs)
139 * @digest: Value extended into PCR index
140 * @event_size: Size of event
143 struct tcg_pcr_event {
146 u8 digest[TPM2_SHA1_DIGEST_SIZE];
152 * Definition of TPMU_HA Union
155 u8 sha1[TPM2_SHA1_DIGEST_SIZE];
156 u8 sha256[TPM2_SHA256_DIGEST_SIZE];
157 u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
158 u8 sha384[TPM2_SHA384_DIGEST_SIZE];
159 u8 sha512[TPM2_SHA512_DIGEST_SIZE];
163 * Definition of TPMT_HA Structure
165 * @hash_alg: Hash algorithm defined in enum tpm2_algorithms
166 * @digest: Digest value for a given algorithm
170 union tmpu_ha digest;
174 * Definition of TPML_DIGEST_VALUES Structure
176 * @count: Number of algorithms supported by hardware
177 * @digests: struct for algorithm id and hash value
179 struct tpml_digest_values {
181 struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
185 * Crypto Agile Log Entry Format
187 * @pcr_index: PCRIndex event extended to
188 * @event_type: Type of event
189 * @digests: List of digestsextended to PCR index
190 * @event_size: Size of the event data
193 struct tcg_pcr_event2 {
196 struct tpml_digest_values digests;
202 * TPM2 Structure Tags for command/response buffers.
204 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
205 * @TPM2_ST_SESSIONS: the command needs an authentication.
207 enum tpm2_structures {
208 TPM2_ST_NO_SESSIONS = 0x8001,
209 TPM2_ST_SESSIONS = 0x8002,
213 * TPM2 type of boolean.
221 * TPM2 startup values.
223 * @TPM2_SU_CLEAR: reset the internal state.
224 * @TPM2_SU_STATE: restore saved state (if any).
226 enum tpm2_startup_types {
227 TPM2_SU_CLEAR = 0x0000,
228 TPM2_SU_STATE = 0x0001,
232 * TPM2 permanent handles.
234 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
235 * @TPM2_RS_PW: indicates a password.
236 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
237 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
238 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
241 TPM2_RH_OWNER = 0x40000001,
242 TPM2_RS_PW = 0x40000009,
243 TPM2_RH_LOCKOUT = 0x4000000A,
244 TPM2_RH_ENDORSEMENT = 0x4000000B,
245 TPM2_RH_PLATFORM = 0x4000000C,
249 * TPM2 command codes used at the beginning of a buffer, gives the command.
251 * @TPM2_CC_STARTUP: TPM2_Startup().
252 * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
253 * @TPM2_CC_CLEAR: TPM2_Clear().
254 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
255 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
256 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
257 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
258 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
259 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
260 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
261 * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
262 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
263 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
265 enum tpm2_command_codes {
266 TPM2_CC_STARTUP = 0x0144,
267 TPM2_CC_SELF_TEST = 0x0143,
268 TPM2_CC_HIER_CONTROL = 0x0121,
269 TPM2_CC_CLEAR = 0x0126,
270 TPM2_CC_CLEARCONTROL = 0x0127,
271 TPM2_CC_HIERCHANGEAUTH = 0x0129,
272 TPM2_CC_NV_DEFINE_SPACE = 0x012a,
273 TPM2_CC_PCR_SETAUTHPOL = 0x012C,
274 TPM2_CC_NV_WRITE = 0x0137,
275 TPM2_CC_NV_WRITELOCK = 0x0138,
276 TPM2_CC_DAM_RESET = 0x0139,
277 TPM2_CC_DAM_PARAMETERS = 0x013A,
278 TPM2_CC_NV_READ = 0x014E,
279 TPM2_CC_GET_CAPABILITY = 0x017A,
280 TPM2_CC_GET_RANDOM = 0x017B,
281 TPM2_CC_PCR_READ = 0x017E,
282 TPM2_CC_PCR_EXTEND = 0x0182,
283 TPM2_CC_PCR_SETAUTHVAL = 0x0183,
289 enum tpm2_return_codes {
290 TPM2_RC_SUCCESS = 0x0000,
291 TPM2_RC_BAD_TAG = 0x001E,
292 TPM2_RC_FMT1 = 0x0080,
293 TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
294 TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
295 TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
296 TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
297 TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
298 TPM2_RC_VER1 = 0x0100,
299 TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
300 TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
301 TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
302 TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
303 TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
304 TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
305 TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
306 TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c,
307 TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
308 TPM2_RC_WARN = 0x0900,
309 TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
310 TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
311 TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
317 enum tpm2_algorithms {
318 TPM2_ALG_SHA1 = 0x04,
320 TPM2_ALG_SHA256 = 0x0B,
321 TPM2_ALG_SHA384 = 0x0C,
322 TPM2_ALG_SHA512 = 0x0D,
323 TPM2_ALG_NULL = 0x10,
324 TPM2_ALG_SM3_256 = 0x12,
327 /* NV index attributes */
328 enum tpm_index_attrs {
329 TPMA_NV_PPWRITE = 1UL << 0,
330 TPMA_NV_OWNERWRITE = 1UL << 1,
331 TPMA_NV_AUTHWRITE = 1UL << 2,
332 TPMA_NV_POLICYWRITE = 1UL << 3,
333 TPMA_NV_COUNTER = 1UL << 4,
334 TPMA_NV_BITS = 1UL << 5,
335 TPMA_NV_EXTEND = 1UL << 6,
336 TPMA_NV_POLICY_DELETE = 1UL << 10,
337 TPMA_NV_WRITELOCKED = 1UL << 11,
338 TPMA_NV_WRITEALL = 1UL << 12,
339 TPMA_NV_WRITEDEFINE = 1UL << 13,
340 TPMA_NV_WRITE_STCLEAR = 1UL << 14,
341 TPMA_NV_GLOBALLOCK = 1UL << 15,
342 TPMA_NV_PPREAD = 1UL << 16,
343 TPMA_NV_OWNERREAD = 1UL << 17,
344 TPMA_NV_AUTHREAD = 1UL << 18,
345 TPMA_NV_POLICYREAD = 1UL << 19,
346 TPMA_NV_NO_DA = 1UL << 25,
347 TPMA_NV_ORDERLY = 1UL << 26,
348 TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
349 TPMA_NV_READLOCKED = 1UL << 28,
350 TPMA_NV_WRITTEN = 1UL << 29,
351 TPMA_NV_PLATFORMCREATE = 1UL << 30,
352 TPMA_NV_READ_STCLEAR = 1UL << 31,
354 TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
355 TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
356 TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
357 TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
361 TPM_ACCESS_VALID = 1 << 7,
362 TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
363 TPM_ACCESS_REQUEST_PENDING = 1 << 2,
364 TPM_ACCESS_REQUEST_USE = 1 << 1,
365 TPM_ACCESS_ESTABLISHMENT = 1 << 0,
369 TPM_STS_FAMILY_SHIFT = 26,
370 TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
371 TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
372 TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
373 TPM_STS_COMMAND_CANCEL = 1 << 24,
374 TPM_STS_BURST_COUNT_SHIFT = 8,
375 TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
376 TPM_STS_VALID = 1 << 7,
377 TPM_STS_COMMAND_READY = 1 << 6,
379 TPM_STS_DATA_AVAIL = 1 << 4,
380 TPM_STS_DATA_EXPECT = 1 << 3,
381 TPM_STS_SELF_TEST_DONE = 1 << 2,
382 TPM_STS_RESPONSE_RETRY = 1 << 1,
386 TPM_CMD_COUNT_OFFSET = 2,
387 TPM_CMD_ORDINAL_OFFSET = 6,
388 TPM_MAX_BUF_SIZE = 1260,
392 /* Secure storage for firmware settings */
396 TPM_HT_POLICY_SESSION,
399 HR_PCR = TPM_HT_PCR << HR_SHIFT,
400 HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
401 HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
402 HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
406 * Issue a TPM2_Startup command.
409 * @mode TPM startup mode
411 * @return code of the operation
413 u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
416 * Issue a TPM2_SelfTest command.
419 * @full_test Asking to perform all tests or only the untested ones
421 * @return code of the operation
423 u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
426 * Issue a TPM2_Clear command.
431 * @pw_sz Length of the password
433 * @return code of the operation
435 u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
436 const ssize_t pw_sz);
439 * Issue a TPM_NV_DefineSpace command
441 * This allows a space to be defined with given attributes and policy
444 * @space_index index of the area
445 * @space_size size of area in bytes
446 * @nv_attributes TPM_NV_ATTRIBUTES of the area
447 * @nv_policy policy to use
448 * @nv_policy_size size of the policy
449 * @return return code of the operation
451 u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
452 size_t space_size, u32 nv_attributes,
453 const u8 *nv_policy, size_t nv_policy_size);
456 * Issue a TPM2_PCR_Extend command.
459 * @index Index of the PCR
460 * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
461 * @digest Value representing the event to be recorded
462 * @digest_len len of the hash
464 * @return code of the operation
466 u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
467 const u8 *digest, u32 digest_len);
470 * Read data from the secure storage
473 * @index Index of data to read
474 * @data Place to put data
475 * @count Number of bytes of data
476 * @return code of the operation
478 u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
481 * Write data to the secure storage
484 * @index Index of data to write
485 * @data Data to write
486 * @count Number of bytes of data
487 * @return code of the operation
489 u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
493 * Issue a TPM2_PCR_Read command.
496 * @idx Index of the PCR
497 * @idx_min_sz Minimum size in bytes of the pcrSelect array
498 * @data Output buffer for contents of the named PCR
499 * @updates Optional out parameter: number of updates for this PCR
501 * @return code of the operation
503 u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
504 void *data, unsigned int *updates);
507 * Issue a TPM2_GetCapability command. This implementation is limited
508 * to query property index that is 4-byte wide.
511 * @capability Partition of capabilities
512 * @property Further definition of capability, limited to be 4 bytes wide
513 * @buf Output buffer for capability information
514 * @prop_count Size of output buffer
516 * @return code of the operation
518 u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
519 void *buf, size_t prop_count);
522 * Issue a TPM2_DictionaryAttackLockReset command.
526 * @pw_sz Length of the password
528 * @return code of the operation
530 u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
533 * Issue a TPM2_DictionaryAttackParameters command.
537 * @pw_sz Length of the password
538 * @max_tries Count of authorizations before lockout
539 * @recovery_time Time before decrementation of the failure count
540 * @lockout_recovery Time to wait after a lockout
542 * @return code of the operation
544 u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
545 const ssize_t pw_sz, unsigned int max_tries,
546 unsigned int recovery_time,
547 unsigned int lockout_recovery);
550 * Issue a TPM2_HierarchyChangeAuth command.
554 * @newpw New password
555 * @newpw_sz Length of the new password
556 * @oldpw Old password
557 * @oldpw_sz Length of the old password
559 * @return code of the operation
561 int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
562 const ssize_t newpw_sz, const char *oldpw,
563 const ssize_t oldpw_sz);
566 * Issue a TPM_PCR_SetAuthPolicy command.
569 * @pw Platform password
570 * @pw_sz Length of the password
571 * @index Index of the PCR
572 * @digest New key to access the PCR
574 * @return code of the operation
576 u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
577 const ssize_t pw_sz, u32 index, const char *key);
580 * Issue a TPM_PCR_SetAuthValue command.
583 * @pw Platform password
584 * @pw_sz Length of the password
585 * @index Index of the PCR
586 * @digest New key to access the PCR
587 * @key_sz Length of the new key
589 * @return code of the operation
591 u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
592 const ssize_t pw_sz, u32 index, const char *key,
593 const ssize_t key_sz);
596 * Issue a TPM2_GetRandom command.
599 * @param data output buffer for the random bytes
600 * @param count size of output buffer
602 * @return return code of the operation
604 u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
607 * Lock data in the TPM
609 * Once locked the data cannot be written until after a reboot
612 * @index Index of data to lock
613 * @return code of the operation
615 u32 tpm2_write_lock(struct udevice *dev, u32 index);
618 * Disable access to any platform data
620 * This can be called to close off access to the firmware data in the data,
621 * before calling the kernel.
624 * @return code of the operation
626 u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
628 #endif /* __TPM_V2_H */