1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Defines APIs and structures that allow software to interact with a
6 * Copyright (c) 2020 Linaro
7 * Copyright (c) 2018 Bootlin
9 * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
11 * Author: Miquel Raynal <miquel.raynal@bootlin.com>
17 #include <tpm-common.h>
21 #define TPM2_DIGEST_LEN 32
23 #define TPM2_SHA1_DIGEST_SIZE 20
24 #define TPM2_SHA256_DIGEST_SIZE 32
25 #define TPM2_SHA384_DIGEST_SIZE 48
26 #define TPM2_SHA512_DIGEST_SIZE 64
27 #define TPM2_SM3_256_DIGEST_SIZE 32
29 #define TPM2_MAX_PCRS 32
30 #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
31 #define TPM2_MAX_CAP_BUFFER 1024
32 #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
33 sizeof(u32)) / sizeof(struct tpms_tagged_property))
36 * We deviate from this draft of the specification by increasing the value of
37 * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
38 * implementations that have enabled a larger than typical number of PCR
39 * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
40 * in a future revision of the specification.
42 #define TPM2_NUM_PCR_BANKS 16
44 /* Definition of (UINT32) TPM2_CAP Constants */
45 #define TPM2_CAP_PCRS 0x00000005U
46 #define TPM2_CAP_TPM_PROPERTIES 0x00000006U
48 /* Definition of (UINT32) TPM2_PT Constants */
49 #define TPM2_PT_GROUP (u32)(0x00000100)
50 #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
51 #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
52 #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
53 #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
54 #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
58 * "TCG Server Management Domain Firmware Profile Specification",
59 * rev 1.00, 2020-05-01
61 #define EV_POST_CODE ((u32)0x00000001)
62 #define EV_NO_ACTION ((u32)0x00000003)
63 #define EV_SEPARATOR ((u32)0x00000004)
64 #define EV_ACTION ((u32)0x00000005)
65 #define EV_TAG ((u32)0x00000006)
66 #define EV_S_CRTM_CONTENTS ((u32)0x00000007)
67 #define EV_S_CRTM_VERSION ((u32)0x00000008)
68 #define EV_CPU_MICROCODE ((u32)0x00000009)
69 #define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
70 #define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
71 #define EV_COMPACT_HASH ((u32)0x0000000C)
73 /* TPMS_TAGGED_PROPERTY Structure */
74 struct tpms_tagged_property {
79 /* TPMS_PCR_SELECTION Structure */
80 struct tpms_pcr_selection {
83 u8 pcr_select[TPM2_PCR_SELECT_MAX];
86 /* TPML_PCR_SELECTION Structure */
87 struct tpml_pcr_selection {
89 struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
92 /* TPML_TAGGED_TPM_PROPERTY Structure */
93 struct tpml_tagged_tpm_property {
95 struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
98 /* TPMU_CAPABILITIES Union */
99 union tpmu_capabilities {
101 * Non exhaustive. Only added the structs needed for our
104 struct tpml_pcr_selection assigned_pcr;
105 struct tpml_tagged_tpm_property tpm_properties;
108 /* TPMS_CAPABILITY_DATA Structure */
109 struct tpms_capability_data {
111 union tpmu_capabilities data;
115 * SHA1 Event Log Entry Format
117 * @pcr_index: PCRIndex event extended to
118 * @event_type: Type of event (see EFI specs)
119 * @digest: Value extended into PCR index
120 * @event_size: Size of event
123 struct tcg_pcr_event {
126 u8 digest[TPM2_SHA1_DIGEST_SIZE];
132 * Definition of TPMU_HA Union
135 u8 sha1[TPM2_SHA1_DIGEST_SIZE];
136 u8 sha256[TPM2_SHA256_DIGEST_SIZE];
137 u8 sm3_256[TPM2_SM3_256_DIGEST_SIZE];
138 u8 sha384[TPM2_SHA384_DIGEST_SIZE];
139 u8 sha512[TPM2_SHA512_DIGEST_SIZE];
143 * Definition of TPMT_HA Structure
145 * @hash_alg: Hash algorithm defined in enum tpm2_algorithms
146 * @digest: Digest value for a given algorithm
150 union tmpu_ha digest;
154 * Definition of TPML_DIGEST_VALUES Structure
156 * @count: Number of algorithms supported by hardware
157 * @digests: struct for algorithm id and hash value
159 struct tpml_digest_values {
161 struct tpmt_ha digests[TPM2_NUM_PCR_BANKS];
165 * Crypto Agile Log Entry Format
167 * @pcr_index: PCRIndex event extended to
168 * @event_type: Type of event
169 * @digests: List of digestsextended to PCR index
170 * @event_size: Size of the event data
173 struct tcg_pcr_event2 {
176 struct tpml_digest_values digests;
182 * TPM2 Structure Tags for command/response buffers.
184 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
185 * @TPM2_ST_SESSIONS: the command needs an authentication.
187 enum tpm2_structures {
188 TPM2_ST_NO_SESSIONS = 0x8001,
189 TPM2_ST_SESSIONS = 0x8002,
193 * TPM2 type of boolean.
201 * TPM2 startup values.
203 * @TPM2_SU_CLEAR: reset the internal state.
204 * @TPM2_SU_STATE: restore saved state (if any).
206 enum tpm2_startup_types {
207 TPM2_SU_CLEAR = 0x0000,
208 TPM2_SU_STATE = 0x0001,
212 * TPM2 permanent handles.
214 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
215 * @TPM2_RS_PW: indicates a password.
216 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
217 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
218 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
221 TPM2_RH_OWNER = 0x40000001,
222 TPM2_RS_PW = 0x40000009,
223 TPM2_RH_LOCKOUT = 0x4000000A,
224 TPM2_RH_ENDORSEMENT = 0x4000000B,
225 TPM2_RH_PLATFORM = 0x4000000C,
229 * TPM2 command codes used at the beginning of a buffer, gives the command.
231 * @TPM2_CC_STARTUP: TPM2_Startup().
232 * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
233 * @TPM2_CC_CLEAR: TPM2_Clear().
234 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
235 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
236 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
237 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
238 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
239 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
240 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
241 * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
242 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
243 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
245 enum tpm2_command_codes {
246 TPM2_CC_STARTUP = 0x0144,
247 TPM2_CC_SELF_TEST = 0x0143,
248 TPM2_CC_HIER_CONTROL = 0x0121,
249 TPM2_CC_CLEAR = 0x0126,
250 TPM2_CC_CLEARCONTROL = 0x0127,
251 TPM2_CC_HIERCHANGEAUTH = 0x0129,
252 TPM2_CC_NV_DEFINE_SPACE = 0x012a,
253 TPM2_CC_PCR_SETAUTHPOL = 0x012C,
254 TPM2_CC_NV_WRITE = 0x0137,
255 TPM2_CC_NV_WRITELOCK = 0x0138,
256 TPM2_CC_DAM_RESET = 0x0139,
257 TPM2_CC_DAM_PARAMETERS = 0x013A,
258 TPM2_CC_NV_READ = 0x014E,
259 TPM2_CC_GET_CAPABILITY = 0x017A,
260 TPM2_CC_GET_RANDOM = 0x017B,
261 TPM2_CC_PCR_READ = 0x017E,
262 TPM2_CC_PCR_EXTEND = 0x0182,
263 TPM2_CC_PCR_SETAUTHVAL = 0x0183,
269 enum tpm2_return_codes {
270 TPM2_RC_SUCCESS = 0x0000,
271 TPM2_RC_BAD_TAG = 0x001E,
272 TPM2_RC_FMT1 = 0x0080,
273 TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
274 TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
275 TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
276 TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
277 TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
278 TPM2_RC_VER1 = 0x0100,
279 TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
280 TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
281 TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
282 TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
283 TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
284 TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
285 TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
286 TPM2_RC_NV_DEFINED = TPM2_RC_VER1 + 0x004c,
287 TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
288 TPM2_RC_WARN = 0x0900,
289 TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
290 TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
291 TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
297 enum tpm2_algorithms {
298 TPM2_ALG_SHA1 = 0x04,
300 TPM2_ALG_SHA256 = 0x0B,
301 TPM2_ALG_SHA384 = 0x0C,
302 TPM2_ALG_SHA512 = 0x0D,
303 TPM2_ALG_NULL = 0x10,
304 TPM2_ALG_SM3_256 = 0x12,
307 /* NV index attributes */
308 enum tpm_index_attrs {
309 TPMA_NV_PPWRITE = 1UL << 0,
310 TPMA_NV_OWNERWRITE = 1UL << 1,
311 TPMA_NV_AUTHWRITE = 1UL << 2,
312 TPMA_NV_POLICYWRITE = 1UL << 3,
313 TPMA_NV_COUNTER = 1UL << 4,
314 TPMA_NV_BITS = 1UL << 5,
315 TPMA_NV_EXTEND = 1UL << 6,
316 TPMA_NV_POLICY_DELETE = 1UL << 10,
317 TPMA_NV_WRITELOCKED = 1UL << 11,
318 TPMA_NV_WRITEALL = 1UL << 12,
319 TPMA_NV_WRITEDEFINE = 1UL << 13,
320 TPMA_NV_WRITE_STCLEAR = 1UL << 14,
321 TPMA_NV_GLOBALLOCK = 1UL << 15,
322 TPMA_NV_PPREAD = 1UL << 16,
323 TPMA_NV_OWNERREAD = 1UL << 17,
324 TPMA_NV_AUTHREAD = 1UL << 18,
325 TPMA_NV_POLICYREAD = 1UL << 19,
326 TPMA_NV_NO_DA = 1UL << 25,
327 TPMA_NV_ORDERLY = 1UL << 26,
328 TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
329 TPMA_NV_READLOCKED = 1UL << 28,
330 TPMA_NV_WRITTEN = 1UL << 29,
331 TPMA_NV_PLATFORMCREATE = 1UL << 30,
332 TPMA_NV_READ_STCLEAR = 1UL << 31,
334 TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
335 TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
336 TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
337 TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
341 TPM_ACCESS_VALID = 1 << 7,
342 TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
343 TPM_ACCESS_REQUEST_PENDING = 1 << 2,
344 TPM_ACCESS_REQUEST_USE = 1 << 1,
345 TPM_ACCESS_ESTABLISHMENT = 1 << 0,
349 TPM_STS_FAMILY_SHIFT = 26,
350 TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
351 TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
352 TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
353 TPM_STS_COMMAND_CANCEL = 1 << 24,
354 TPM_STS_BURST_COUNT_SHIFT = 8,
355 TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
356 TPM_STS_VALID = 1 << 7,
357 TPM_STS_COMMAND_READY = 1 << 6,
359 TPM_STS_DATA_AVAIL = 1 << 4,
360 TPM_STS_DATA_EXPECT = 1 << 3,
361 TPM_STS_SELF_TEST_DONE = 1 << 2,
362 TPM_STS_RESPONSE_RETRY = 1 << 1,
366 TPM_CMD_COUNT_OFFSET = 2,
367 TPM_CMD_ORDINAL_OFFSET = 6,
368 TPM_MAX_BUF_SIZE = 1260,
372 /* Secure storage for firmware settings */
376 TPM_HT_POLICY_SESSION,
379 HR_PCR = TPM_HT_PCR << HR_SHIFT,
380 HR_HMAC_SESSION = TPM_HT_HMAC_SESSION << HR_SHIFT,
381 HR_POLICY_SESSION = TPM_HT_POLICY_SESSION << HR_SHIFT,
382 HR_NV_INDEX = TPM_HT_NV_INDEX << HR_SHIFT,
386 * Issue a TPM2_Startup command.
389 * @mode TPM startup mode
391 * @return code of the operation
393 u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
396 * Issue a TPM2_SelfTest command.
399 * @full_test Asking to perform all tests or only the untested ones
401 * @return code of the operation
403 u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
406 * Issue a TPM2_Clear command.
411 * @pw_sz Length of the password
413 * @return code of the operation
415 u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
416 const ssize_t pw_sz);
419 * Issue a TPM_NV_DefineSpace command
421 * This allows a space to be defined with given attributes and policy
424 * @space_index index of the area
425 * @space_size size of area in bytes
426 * @nv_attributes TPM_NV_ATTRIBUTES of the area
427 * @nv_policy policy to use
428 * @nv_policy_size size of the policy
429 * @return return code of the operation
431 u32 tpm2_nv_define_space(struct udevice *dev, u32 space_index,
432 size_t space_size, u32 nv_attributes,
433 const u8 *nv_policy, size_t nv_policy_size);
436 * Issue a TPM2_PCR_Extend command.
439 * @index Index of the PCR
440 * @algorithm Algorithm used, defined in 'enum tpm2_algorithms'
441 * @digest Value representing the event to be recorded
442 * @digest_len len of the hash
444 * @return code of the operation
446 u32 tpm2_pcr_extend(struct udevice *dev, u32 index, u32 algorithm,
447 const u8 *digest, u32 digest_len);
450 * Read data from the secure storage
453 * @index Index of data to read
454 * @data Place to put data
455 * @count Number of bytes of data
456 * @return code of the operation
458 u32 tpm2_nv_read_value(struct udevice *dev, u32 index, void *data, u32 count);
461 * Write data to the secure storage
464 * @index Index of data to write
465 * @data Data to write
466 * @count Number of bytes of data
467 * @return code of the operation
469 u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data,
473 * Issue a TPM2_PCR_Read command.
476 * @idx Index of the PCR
477 * @idx_min_sz Minimum size in bytes of the pcrSelect array
478 * @data Output buffer for contents of the named PCR
479 * @updates Optional out parameter: number of updates for this PCR
481 * @return code of the operation
483 u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
484 void *data, unsigned int *updates);
487 * Issue a TPM2_GetCapability command. This implementation is limited
488 * to query property index that is 4-byte wide.
491 * @capability Partition of capabilities
492 * @property Further definition of capability, limited to be 4 bytes wide
493 * @buf Output buffer for capability information
494 * @prop_count Size of output buffer
496 * @return code of the operation
498 u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
499 void *buf, size_t prop_count);
502 * Issue a TPM2_DictionaryAttackLockReset command.
506 * @pw_sz Length of the password
508 * @return code of the operation
510 u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
513 * Issue a TPM2_DictionaryAttackParameters command.
517 * @pw_sz Length of the password
518 * @max_tries Count of authorizations before lockout
519 * @recovery_time Time before decrementation of the failure count
520 * @lockout_recovery Time to wait after a lockout
522 * @return code of the operation
524 u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
525 const ssize_t pw_sz, unsigned int max_tries,
526 unsigned int recovery_time,
527 unsigned int lockout_recovery);
530 * Issue a TPM2_HierarchyChangeAuth command.
534 * @newpw New password
535 * @newpw_sz Length of the new password
536 * @oldpw Old password
537 * @oldpw_sz Length of the old password
539 * @return code of the operation
541 int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
542 const ssize_t newpw_sz, const char *oldpw,
543 const ssize_t oldpw_sz);
546 * Issue a TPM_PCR_SetAuthPolicy command.
549 * @pw Platform password
550 * @pw_sz Length of the password
551 * @index Index of the PCR
552 * @digest New key to access the PCR
554 * @return code of the operation
556 u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
557 const ssize_t pw_sz, u32 index, const char *key);
560 * Issue a TPM_PCR_SetAuthValue command.
563 * @pw Platform password
564 * @pw_sz Length of the password
565 * @index Index of the PCR
566 * @digest New key to access the PCR
567 * @key_sz Length of the new key
569 * @return code of the operation
571 u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
572 const ssize_t pw_sz, u32 index, const char *key,
573 const ssize_t key_sz);
576 * Issue a TPM2_GetRandom command.
579 * @param data output buffer for the random bytes
580 * @param count size of output buffer
582 * @return return code of the operation
584 u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
587 * Lock data in the TPM
589 * Once locked the data cannot be written until after a reboot
592 * @index Index of data to lock
593 * @return code of the operation
595 u32 tpm2_write_lock(struct udevice *dev, u32 index);
598 * Disable access to any platform data
600 * This can be called to close off access to the firmware data in the data,
601 * before calling the kernel.
604 * @return code of the operation
606 u32 tpm2_disable_platform_hierarchy(struct udevice *dev);
608 #endif /* __TPM_V2_H */