1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Defines APIs and structures that allow software to interact with a
6 * Copyright (c) 2020 Linaro
7 * Copyright (c) 2018 Bootlin
9 * https://trustedcomputinggroup.org/resource/tss-overview-common-structures-specification/
11 * Author: Miquel Raynal <miquel.raynal@bootlin.com>
17 #include <tpm-common.h>
19 #define TPM2_DIGEST_LEN 32
21 #define TPM2_MAX_PCRS 32
22 #define TPM2_PCR_SELECT_MAX ((TPM2_MAX_PCRS + 7) / 8)
23 #define TPM2_MAX_CAP_BUFFER 1024
24 #define TPM2_MAX_TPM_PROPERTIES ((TPM2_MAX_CAP_BUFFER - sizeof(u32) /* TPM2_CAP */ - \
25 sizeof(u32)) / sizeof(struct tpms_tagged_property))
28 * We deviate from this draft of the specification by increasing the value of
29 * TPM2_NUM_PCR_BANKS from 3 to 16 to ensure compatibility with TPM2
30 * implementations that have enabled a larger than typical number of PCR
31 * banks. This larger value for TPM2_NUM_PCR_BANKS is expected to be included
32 * in a future revision of the specification.
34 #define TPM2_NUM_PCR_BANKS 16
36 /* Definition of (UINT32) TPM2_CAP Constants */
37 #define TPM2_CAP_PCRS 0x00000005U
38 #define TPM2_CAP_TPM_PROPERTIES 0x00000006U
40 /* Definition of (UINT32) TPM2_PT Constants */
41 #define TPM2_PT_GROUP (u32)(0x00000100)
42 #define TPM2_PT_FIXED (u32)(TPM2_PT_GROUP * 1)
43 #define TPM2_PT_MANUFACTURER (u32)(TPM2_PT_FIXED + 5)
44 #define TPM2_PT_PCR_COUNT (u32)(TPM2_PT_FIXED + 18)
45 #define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
46 #define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
48 /* TPMS_TAGGED_PROPERTY Structure */
49 struct tpms_tagged_property {
54 /* TPMS_PCR_SELECTION Structure */
55 struct tpms_pcr_selection {
58 u8 pcr_select[TPM2_PCR_SELECT_MAX];
61 /* TPML_PCR_SELECTION Structure */
62 struct tpml_pcr_selection {
64 struct tpms_pcr_selection selection[TPM2_NUM_PCR_BANKS];
67 /* TPML_TAGGED_TPM_PROPERTY Structure */
68 struct tpml_tagged_tpm_property {
70 struct tpms_tagged_property tpm_property[TPM2_MAX_TPM_PROPERTIES];
73 /* TPMU_CAPABILITIES Union */
74 union tpmu_capabilities {
76 * Non exhaustive. Only added the structs needed for our
79 struct tpml_pcr_selection assigned_pcr;
80 struct tpml_tagged_tpm_property tpm_properties;
83 /* TPMS_CAPABILITY_DATA Structure */
84 struct tpms_capability_data {
86 union tpmu_capabilities data;
90 * TPM2 Structure Tags for command/response buffers.
92 * @TPM2_ST_NO_SESSIONS: the command does not need an authentication.
93 * @TPM2_ST_SESSIONS: the command needs an authentication.
95 enum tpm2_structures {
96 TPM2_ST_NO_SESSIONS = 0x8001,
97 TPM2_ST_SESSIONS = 0x8002,
101 * TPM2 type of boolean.
109 * TPM2 startup values.
111 * @TPM2_SU_CLEAR: reset the internal state.
112 * @TPM2_SU_STATE: restore saved state (if any).
114 enum tpm2_startup_types {
115 TPM2_SU_CLEAR = 0x0000,
116 TPM2_SU_STATE = 0x0001,
120 * TPM2 permanent handles.
122 * @TPM2_RH_OWNER: refers to the 'owner' hierarchy.
123 * @TPM2_RS_PW: indicates a password.
124 * @TPM2_RH_LOCKOUT: refers to the 'lockout' hierarchy.
125 * @TPM2_RH_ENDORSEMENT: refers to the 'endorsement' hierarchy.
126 * @TPM2_RH_PLATFORM: refers to the 'platform' hierarchy.
129 TPM2_RH_OWNER = 0x40000001,
130 TPM2_RS_PW = 0x40000009,
131 TPM2_RH_LOCKOUT = 0x4000000A,
132 TPM2_RH_ENDORSEMENT = 0x4000000B,
133 TPM2_RH_PLATFORM = 0x4000000C,
137 * TPM2 command codes used at the beginning of a buffer, gives the command.
139 * @TPM2_CC_STARTUP: TPM2_Startup().
140 * @TPM2_CC_SELF_TEST: TPM2_SelfTest().
141 * @TPM2_CC_CLEAR: TPM2_Clear().
142 * @TPM2_CC_CLEARCONTROL: TPM2_ClearControl().
143 * @TPM2_CC_HIERCHANGEAUTH: TPM2_HierarchyChangeAuth().
144 * @TPM2_CC_PCR_SETAUTHPOL: TPM2_PCR_SetAuthPolicy().
145 * @TPM2_CC_DAM_RESET: TPM2_DictionaryAttackLockReset().
146 * @TPM2_CC_DAM_PARAMETERS: TPM2_DictionaryAttackParameters().
147 * @TPM2_CC_GET_CAPABILITY: TPM2_GetCapibility().
148 * @TPM2_CC_GET_RANDOM: TPM2_GetRandom().
149 * @TPM2_CC_PCR_READ: TPM2_PCR_Read().
150 * @TPM2_CC_PCR_EXTEND: TPM2_PCR_Extend().
151 * @TPM2_CC_PCR_SETAUTHVAL: TPM2_PCR_SetAuthValue().
153 enum tpm2_command_codes {
154 TPM2_CC_STARTUP = 0x0144,
155 TPM2_CC_SELF_TEST = 0x0143,
156 TPM2_CC_CLEAR = 0x0126,
157 TPM2_CC_CLEARCONTROL = 0x0127,
158 TPM2_CC_HIERCHANGEAUTH = 0x0129,
159 TPM2_CC_PCR_SETAUTHPOL = 0x012C,
160 TPM2_CC_DAM_RESET = 0x0139,
161 TPM2_CC_DAM_PARAMETERS = 0x013A,
162 TPM2_CC_NV_READ = 0x014E,
163 TPM2_CC_GET_CAPABILITY = 0x017A,
164 TPM2_CC_GET_RANDOM = 0x017B,
165 TPM2_CC_PCR_READ = 0x017E,
166 TPM2_CC_PCR_EXTEND = 0x0182,
167 TPM2_CC_PCR_SETAUTHVAL = 0x0183,
173 enum tpm2_return_codes {
174 TPM2_RC_SUCCESS = 0x0000,
175 TPM2_RC_BAD_TAG = 0x001E,
176 TPM2_RC_FMT1 = 0x0080,
177 TPM2_RC_HASH = TPM2_RC_FMT1 + 0x0003,
178 TPM2_RC_VALUE = TPM2_RC_FMT1 + 0x0004,
179 TPM2_RC_SIZE = TPM2_RC_FMT1 + 0x0015,
180 TPM2_RC_BAD_AUTH = TPM2_RC_FMT1 + 0x0022,
181 TPM2_RC_HANDLE = TPM2_RC_FMT1 + 0x000B,
182 TPM2_RC_VER1 = 0x0100,
183 TPM2_RC_INITIALIZE = TPM2_RC_VER1 + 0x0000,
184 TPM2_RC_FAILURE = TPM2_RC_VER1 + 0x0001,
185 TPM2_RC_DISABLED = TPM2_RC_VER1 + 0x0020,
186 TPM2_RC_AUTH_MISSING = TPM2_RC_VER1 + 0x0025,
187 TPM2_RC_COMMAND_CODE = TPM2_RC_VER1 + 0x0043,
188 TPM2_RC_AUTHSIZE = TPM2_RC_VER1 + 0x0044,
189 TPM2_RC_AUTH_CONTEXT = TPM2_RC_VER1 + 0x0045,
190 TPM2_RC_NEEDS_TEST = TPM2_RC_VER1 + 0x0053,
191 TPM2_RC_WARN = 0x0900,
192 TPM2_RC_TESTING = TPM2_RC_WARN + 0x000A,
193 TPM2_RC_REFERENCE_H0 = TPM2_RC_WARN + 0x0010,
194 TPM2_RC_LOCKOUT = TPM2_RC_WARN + 0x0021,
200 enum tpm2_algorithms {
201 TPM2_ALG_SHA1 = 0x04,
203 TPM2_ALG_SHA256 = 0x0B,
204 TPM2_ALG_SHA384 = 0x0C,
205 TPM2_ALG_SHA512 = 0x0D,
206 TPM2_ALG_NULL = 0x10,
207 TPM2_ALG_SM3_256 = 0x12,
210 /* NV index attributes */
211 enum tpm_index_attrs {
212 TPMA_NV_PPWRITE = 1UL << 0,
213 TPMA_NV_OWNERWRITE = 1UL << 1,
214 TPMA_NV_AUTHWRITE = 1UL << 2,
215 TPMA_NV_POLICYWRITE = 1UL << 3,
216 TPMA_NV_COUNTER = 1UL << 4,
217 TPMA_NV_BITS = 1UL << 5,
218 TPMA_NV_EXTEND = 1UL << 6,
219 TPMA_NV_POLICY_DELETE = 1UL << 10,
220 TPMA_NV_WRITELOCKED = 1UL << 11,
221 TPMA_NV_WRITEALL = 1UL << 12,
222 TPMA_NV_WRITEDEFINE = 1UL << 13,
223 TPMA_NV_WRITE_STCLEAR = 1UL << 14,
224 TPMA_NV_GLOBALLOCK = 1UL << 15,
225 TPMA_NV_PPREAD = 1UL << 16,
226 TPMA_NV_OWNERREAD = 1UL << 17,
227 TPMA_NV_AUTHREAD = 1UL << 18,
228 TPMA_NV_POLICYREAD = 1UL << 19,
229 TPMA_NV_NO_DA = 1UL << 25,
230 TPMA_NV_ORDERLY = 1UL << 26,
231 TPMA_NV_CLEAR_STCLEAR = 1UL << 27,
232 TPMA_NV_READLOCKED = 1UL << 28,
233 TPMA_NV_WRITTEN = 1UL << 29,
234 TPMA_NV_PLATFORMCREATE = 1UL << 30,
235 TPMA_NV_READ_STCLEAR = 1UL << 31,
237 TPMA_NV_MASK_READ = TPMA_NV_PPREAD | TPMA_NV_OWNERREAD |
238 TPMA_NV_AUTHREAD | TPMA_NV_POLICYREAD,
239 TPMA_NV_MASK_WRITE = TPMA_NV_PPWRITE | TPMA_NV_OWNERWRITE |
240 TPMA_NV_AUTHWRITE | TPMA_NV_POLICYWRITE,
244 TPM_ACCESS_VALID = 1 << 7,
245 TPM_ACCESS_ACTIVE_LOCALITY = 1 << 5,
246 TPM_ACCESS_REQUEST_PENDING = 1 << 2,
247 TPM_ACCESS_REQUEST_USE = 1 << 1,
248 TPM_ACCESS_ESTABLISHMENT = 1 << 0,
252 TPM_STS_FAMILY_SHIFT = 26,
253 TPM_STS_FAMILY_MASK = 0x3 << TPM_STS_FAMILY_SHIFT,
254 TPM_STS_FAMILY_TPM2 = 1 << TPM_STS_FAMILY_SHIFT,
255 TPM_STS_RESE_TESTABLISMENT_BIT = 1 << 25,
256 TPM_STS_COMMAND_CANCEL = 1 << 24,
257 TPM_STS_BURST_COUNT_SHIFT = 8,
258 TPM_STS_BURST_COUNT_MASK = 0xffff << TPM_STS_BURST_COUNT_SHIFT,
259 TPM_STS_VALID = 1 << 7,
260 TPM_STS_COMMAND_READY = 1 << 6,
262 TPM_STS_DATA_AVAIL = 1 << 4,
263 TPM_STS_DATA_EXPECT = 1 << 3,
264 TPM_STS_SELF_TEST_DONE = 1 << 2,
265 TPM_STS_RESPONSE_RETRY = 1 << 1,
269 TPM_CMD_COUNT_OFFSET = 2,
270 TPM_CMD_ORDINAL_OFFSET = 6,
271 TPM_MAX_BUF_SIZE = 1260,
275 * Issue a TPM2_Startup command.
278 * @mode TPM startup mode
280 * @return code of the operation
282 u32 tpm2_startup(struct udevice *dev, enum tpm2_startup_types mode);
285 * Issue a TPM2_SelfTest command.
288 * @full_test Asking to perform all tests or only the untested ones
290 * @return code of the operation
292 u32 tpm2_self_test(struct udevice *dev, enum tpm2_yes_no full_test);
295 * Issue a TPM2_Clear command.
300 * @pw_sz Length of the password
302 * @return code of the operation
304 u32 tpm2_clear(struct udevice *dev, u32 handle, const char *pw,
305 const ssize_t pw_sz);
308 * Issue a TPM2_PCR_Extend command.
311 * @index Index of the PCR
312 * @digest Value representing the event to be recorded
314 * @return code of the operation
316 u32 tpm2_pcr_extend(struct udevice *dev, u32 index, const uint8_t *digest);
319 * Issue a TPM2_PCR_Read command.
322 * @idx Index of the PCR
323 * @idx_min_sz Minimum size in bytes of the pcrSelect array
324 * @data Output buffer for contents of the named PCR
325 * @updates Optional out parameter: number of updates for this PCR
327 * @return code of the operation
329 u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz,
330 void *data, unsigned int *updates);
333 * Issue a TPM2_GetCapability command. This implementation is limited
334 * to query property index that is 4-byte wide.
337 * @capability Partition of capabilities
338 * @property Further definition of capability, limited to be 4 bytes wide
339 * @buf Output buffer for capability information
340 * @prop_count Size of output buffer
342 * @return code of the operation
344 u32 tpm2_get_capability(struct udevice *dev, u32 capability, u32 property,
345 void *buf, size_t prop_count);
348 * Issue a TPM2_DictionaryAttackLockReset command.
352 * @pw_sz Length of the password
354 * @return code of the operation
356 u32 tpm2_dam_reset(struct udevice *dev, const char *pw, const ssize_t pw_sz);
359 * Issue a TPM2_DictionaryAttackParameters command.
363 * @pw_sz Length of the password
364 * @max_tries Count of authorizations before lockout
365 * @recovery_time Time before decrementation of the failure count
366 * @lockout_recovery Time to wait after a lockout
368 * @return code of the operation
370 u32 tpm2_dam_parameters(struct udevice *dev, const char *pw,
371 const ssize_t pw_sz, unsigned int max_tries,
372 unsigned int recovery_time,
373 unsigned int lockout_recovery);
376 * Issue a TPM2_HierarchyChangeAuth command.
380 * @newpw New password
381 * @newpw_sz Length of the new password
382 * @oldpw Old password
383 * @oldpw_sz Length of the old password
385 * @return code of the operation
387 int tpm2_change_auth(struct udevice *dev, u32 handle, const char *newpw,
388 const ssize_t newpw_sz, const char *oldpw,
389 const ssize_t oldpw_sz);
392 * Issue a TPM_PCR_SetAuthPolicy command.
395 * @pw Platform password
396 * @pw_sz Length of the password
397 * @index Index of the PCR
398 * @digest New key to access the PCR
400 * @return code of the operation
402 u32 tpm2_pcr_setauthpolicy(struct udevice *dev, const char *pw,
403 const ssize_t pw_sz, u32 index, const char *key);
406 * Issue a TPM_PCR_SetAuthValue command.
409 * @pw Platform password
410 * @pw_sz Length of the password
411 * @index Index of the PCR
412 * @digest New key to access the PCR
413 * @key_sz Length of the new key
415 * @return code of the operation
417 u32 tpm2_pcr_setauthvalue(struct udevice *dev, const char *pw,
418 const ssize_t pw_sz, u32 index, const char *key,
419 const ssize_t key_sz);
422 * Issue a TPM2_GetRandom command.
425 * @param data output buffer for the random bytes
426 * @param count size of output buffer
428 * @return return code of the operation
430 u32 tpm2_get_random(struct udevice *dev, void *data, u32 count);
432 #endif /* __TPM_V2_H */