2 * Copyright (C) 2014 Spreadtrum Communications Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 *************************************************
15 * Automatically generated C header: do not edit *
16 *************************************************
19 #ifndef __SCI_GLB_REGS_H__
20 #error "Don't include this file directly, Pls include sci_glb_regs.h"
26 #ifndef __H_REGS_MM_AHB_RF_HEADFILE_H__
27 #define __H_REGS_MM_AHB_RF_HEADFILE_H__ __FILE__
29 #define REGS_MM_AHB_RF
31 /* registers definitions for MM_AHB_RF */
32 #define REG_MM_AHB_AHB_EB SCI_ADDR(REGS_MM_AHB_BASE, 0x0000)/*AHB_EB*/
33 #define REG_MM_AHB_AHB_RST SCI_ADDR(REGS_MM_AHB_BASE, 0x0004)/*AHB_RST*/
34 #define REG_MM_AHB_GEN_CKG_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0008)/*GEN_CKG_CFG*/
35 #define REG_MM_AHB_MIPI_CSI2_CTRL SCI_ADDR(REGS_MM_AHB_BASE, 0x000C)/*MIPI_CSI2_CTRL*/
36 #define REG_MM_AHB_MM_QOS_CFG SCI_ADDR(REGS_MM_AHB_BASE, 0x0010)/*MM_QOS_CFG*/
38 #define REG_MM_AHB_RF_AHB_EB REG_MM_AHB_AHB_EB
39 #define REG_MM_AHB_RF_AHB_RST REG_MM_AHB_AHB_RST
40 #define REG_MM_AHB_RF_GEN_CKG_CFG REG_MM_AHB_GEN_CKG_CFG
41 #define REG_MM_AHB_RF_MIPI_CSI2_CTRL REG_MM_AHB_MIPI_CSI2_CTRL
42 #define REG_MM_AHB_RF_MM_QOS_CFG REG_MM_AHB_MM_QOS_CFG
46 /* bits definitions for register REG_MM_AHB_AHB_EB */
47 #define BIT_MMU_EB ( BIT(7) )
48 #define BIT_MM_AHB_CKG_EB ( BIT(6) )
49 #define BIT_MM_CKG_EB BIT_MM_AHB_CKG_EB
50 #define BIT_JPG_EB ( BIT(5) )
51 #define BIT_CSI_EB ( BIT(4) )
52 #define BIT_VSP_EB ( BIT(3) )
53 #define BIT_ISP_EB ( BIT(2) )
54 #define BIT_CCIR_EB ( BIT(1) )
55 #define BIT_DCAM_EB ( BIT(0) )
57 /* bits definitions for register REG_MM_AHB_AHB_RST */
58 #define BIT_MMU_SOFT_RST ( BIT(14) )
59 #define BIT_MM_AHB_CKG_SOFT_RST ( BIT(13) )
60 #define BIT_MM_CKG_SOFT_RST BIT_MM_AHB_CKG_SOFT_RST
61 #define BIT_MM_MTX_SOFT_RST ( BIT(12) )
62 #define BIT_OR1200_SOFT_RST ( BIT(11) )
63 #define BIT_ROT_SOFT_RST ( BIT(10) )
64 #define BIT_CAM2_SOFT_RST ( BIT(9) )
65 #define BIT_CAM1_SOFT_RST ( BIT(8) )
66 #define BIT_CAM0_SOFT_RST ( BIT(7) )
67 #define BIT_JPG_SOFT_RST ( BIT(6) )
68 #define BIT_CSI_SOFT_RST ( BIT(5) )
69 #define BIT_VSP_SOFT_RST ( BIT(4) )
70 #define BIT_ISP_CFG_SOFT_RST ( BIT(3) )
71 #define BIT_ISP_LOG_SOFT_RST ( BIT(2) )
72 #define BIT_CCIR_SOFT_RST ( BIT(1) )
73 #define BIT_DCAM_SOFT_RST ( BIT(0) )
75 /* bits definitions for register REG_MM_AHB_GEN_CKG_CFG */
76 #define BIT_MM_MTX_AXI_CKG_EN ( BIT(8) )
77 #define BIT_MM_AXI_CKG_EN ( BIT(7) )
78 #define BIT_JPG_AXI_CKG_EN ( BIT(6) )
79 #define BIT_VSP_AXI_CKG_EN ( BIT(5) )
80 #define BIT_ISP_AXI_CKG_EN ( BIT(4) )
81 #define BIT_DCAM_AXI_CKG_EN ( BIT(3) )
82 #define BIT_SENSOR_CKG_EN ( BIT(2) )
83 #define BIT_MIPI_CSI_CKG_EN ( BIT(1) )
84 #define BIT_CPHY_CFG_CKG_EN ( BIT(0) )
86 /* bits definitions for register REG_MM_AHB_MIPI_CSI2_CTRL */
87 #define BITS_MIPI_CPHY_SAMPLE_SEL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
88 #define BIT_MIPI_CPHY_SYNC_MODE ( BIT(2) )
89 #define BIT_MIPI_CPHY_TEST_CTL ( BIT(1) )
90 #define BIT_MIPI_CPHY_SEL ( BIT(0) )
92 /* bits definitions for register REG_MM_AHB_MM_QOS_CFG */
93 #define BITS_QOS_R_DCAM(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
94 #define BITS_QOS_W_DCAM(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
95 #define BITS_QOS_R_JPG(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
96 #define BITS_QOS_W_JPG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
97 #define BITS_QOS_R_ISP(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
98 #define BITS_QOS_W_ISP(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
99 #define BITS_QOS_R_VSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
100 #define BITS_QOS_W_VSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )