tizen 2.4 release
[profile/mobile/platform/kernel/linux-3.10-sc7730.git] / include / soc / sprd / chip_x35l / __regs_pmu_apb_rf.h
1 /*
2  * Copyright (C) 2014 Spreadtrum Communications Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * as published by the Free Software Foundation; either version 2
7  * of the License, or (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  *************************************************
15  * Automatically generated C header: do not edit *
16  *************************************************
17  */
18
19 #ifndef __SCI_GLB_REGS_H__
20 #error  "Don't include this file directly, Pls include sci_glb_regs.h"
21 #endif
22
23
24 #ifndef __H_REGS_PMU_APB_HEADFILE_H__
25 #define __H_REGS_PMU_APB_HEADFILE_H__ __FILE__
26
27 #define REGS_PMU_APB_RF
28
29 /* registers definitions for PMU_APB_RF */
30 #define REG_PMU_APB_PD_CA7_TOP_CFG                     SCI_ADDR(REGS_PMU_APB_BASE, 0x0000)
31 #define REG_PMU_APB_PD_CA7_C0_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x0004)
32 #define REG_PMU_APB_PD_CA7_C1_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x0008)
33 #define REG_PMU_APB_PD_CA7_C2_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x000C)
34 #define REG_PMU_APB_PD_CA7_C3_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x0010)
35 #define REG_PMU_APB_PD_AP_SYS_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x0018)
36 #define REG_PMU_APB_PD_MM_TOP_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x001C)
37 #define REG_PMU_APB_PD_GPU_TOP_CFG                     SCI_ADDR(REGS_PMU_APB_BASE, 0x0020)
38 #define REG_PMU_APB_PD_CP0_ARM9_0_CFG                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0024)
39 #define REG_PMU_APB_PD_CP0_ARM9_1_CFG                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0028)
40 #define REG_PMU_APB_PD_CP0_HU3GE_CFG                   SCI_ADDR(REGS_PMU_APB_BASE, 0x002C)
41 #define REG_PMU_APB_PD_CP0_GSM_0_CFG                   SCI_ADDR(REGS_PMU_APB_BASE, 0x0030)
42 #define REG_PMU_APB_PD_CP0_GSM_1_CFG                   SCI_ADDR(REGS_PMU_APB_BASE, 0x0034)
43 #define REG_PMU_APB_PD_CP0_TD_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x0038)
44 #define REG_PMU_APB_PD_CP0_CEVA_0_CFG                  SCI_ADDR(REGS_PMU_APB_BASE, 0x003C)
45 #define REG_PMU_APB_PD_CP0_CEVA_1_CFG                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0040)
46 #define REG_PMU_APB_PD_CP0_SYS_CFG                     SCI_ADDR(REGS_PMU_APB_BASE, 0x0044)
47 #define REG_PMU_APB_PD_CP1_CA5_CFG                     SCI_ADDR(REGS_PMU_APB_BASE, 0x0048)
48 #define REG_PMU_APB_PD_CP1_LTE_P1_CFG                  SCI_ADDR(REGS_PMU_APB_BASE, 0x004C)
49 #define REG_PMU_APB_PD_CP1_LTE_P2_CFG                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0050)
50 #define REG_PMU_APB_PD_CP1_CEVA_CFG                    SCI_ADDR(REGS_PMU_APB_BASE, 0x0054)
51 #define REG_PMU_APB_PD_CP1_COMWRAP_CFG                 SCI_ADDR(REGS_PMU_APB_BASE, 0x0058)
52 #define REG_PMU_APB_PD_PUB_SYS_CFG                     SCI_ADDR(REGS_PMU_APB_BASE, 0x005C)
53 #define REG_PMU_APB_AP_WAKEUP_POR_CFG                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0060)
54 #define REG_PMU_APB_XTL_WAIT_CNT                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0070)
55 #define REG_PMU_APB_XTLBUF_WAIT_CNT                    SCI_ADDR(REGS_PMU_APB_BASE, 0x0074)
56 #define REG_PMU_APB_PLL_WAIT_CNT1                      SCI_ADDR(REGS_PMU_APB_BASE, 0x0078)
57 #define REG_PMU_APB_PLL_WAIT_CNT2                      SCI_ADDR(REGS_PMU_APB_BASE, 0x007C)
58 #define REG_PMU_APB_XTL0_REL_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0080)
59 #define REG_PMU_APB_XTL1_REL_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0084)
60 #define REG_PMU_APB_XTLBUF0_REL_CFG                    SCI_ADDR(REGS_PMU_APB_BASE, 0x008C)
61 #define REG_PMU_APB_XTLBUF1_REL_CFG                    SCI_ADDR(REGS_PMU_APB_BASE, 0x0090)
62 #define REG_PMU_APB_MPLL_REL_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0094)
63 #define REG_PMU_APB_DPLL_REL_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0098)
64 #define REG_PMU_APB_LTEPLL_REL_CFG                     SCI_ADDR(REGS_PMU_APB_BASE, 0x009C)
65 #define REG_PMU_APB_TWPLL_REL_CFG                      SCI_ADDR(REGS_PMU_APB_BASE, 0x00A0)
66 #define REG_PMU_APB_LVDSDIS_PLL_REL_CFG                SCI_ADDR(REGS_PMU_APB_BASE, 0x00A4)
67 #define REG_PMU_APB_CP_SOFT_RST                        SCI_ADDR(REGS_PMU_APB_BASE, 0x00B0)
68 #define REG_PMU_APB_CP_SLP_STATUS_DBG0                 SCI_ADDR(REGS_PMU_APB_BASE, 0x00B4)
69 #define REG_PMU_APB_PWR_STATUS0_DBG                    SCI_ADDR(REGS_PMU_APB_BASE, 0x00BC)
70 #define REG_PMU_APB_PWR_STATUS1_DBG                    SCI_ADDR(REGS_PMU_APB_BASE, 0x00C0)
71 #define REG_PMU_APB_PWR_STATUS2_DBG                    SCI_ADDR(REGS_PMU_APB_BASE, 0x00C4)
72 #define REG_PMU_APB_SLEEP_CTRL                         SCI_ADDR(REGS_PMU_APB_BASE, 0x00CC)
73 #define REG_PMU_APB_DDR_SLEEP_CTRL                     SCI_ADDR(REGS_PMU_APB_BASE, 0x00D0)
74 #define REG_PMU_APB_SLEEP_STATUS                       SCI_ADDR(REGS_PMU_APB_BASE, 0x00D4)
75 #define REG_PMU_APB_CA7_TOP_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x00E4)
76 #define REG_PMU_APB_CA7_C0_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x00E8)
77 #define REG_PMU_APB_CA7_C1_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x00EC)
78 #define REG_PMU_APB_CA7_C2_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x00F0)
79 #define REG_PMU_APB_CA7_C3_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x00F4)
80 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL0                SCI_ADDR(REGS_PMU_APB_BASE, 0x00F8)
81 #define REG_PMU_APB_DDR_CHN_SLEEP_CTRL1                SCI_ADDR(REGS_PMU_APB_BASE, 0x00FC)
82 #define REG_PMU_APB_DDR_OP_MODE_CFG                    SCI_ADDR(REGS_PMU_APB_BASE, 0x012C)
83 #define REG_PMU_APB_DDR_PHY_RET_CFG                    SCI_ADDR(REGS_PMU_APB_BASE, 0x0130)
84 #define REG_PMU_APB_26M_SEL_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0134)
85 #define REG_PMU_APB_BISR_DONE_STATUS                   SCI_ADDR(REGS_PMU_APB_BASE, 0x0138)
86 #define REG_PMU_APB_BISR_BUSY_STATUS                   SCI_ADDR(REGS_PMU_APB_BASE, 0x013C)
87 #define REG_PMU_APB_BISR_BYP_CFG                       SCI_ADDR(REGS_PMU_APB_BASE, 0x0140)
88 #define REG_PMU_APB_BISR_EN_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0144)
89 #define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0             SCI_ADDR(REGS_PMU_APB_BASE, 0x0148)
90 #define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1             SCI_ADDR(REGS_PMU_APB_BASE, 0x014C)
91 #define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2             SCI_ADDR(REGS_PMU_APB_BASE, 0x0150)
92 #define REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3             SCI_ADDR(REGS_PMU_APB_BASE, 0x0154)
93 #define REG_PMU_APB_CGM_FORCE_EN_CFG0                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0158)
94 #define REG_PMU_APB_CGM_FORCE_EN_CFG1                  SCI_ADDR(REGS_PMU_APB_BASE, 0x015C)
95 #define REG_PMU_APB_CGM_FORCE_EN_CFG2                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0160)
96 #define REG_PMU_APB_CGM_FORCE_EN_CFG3                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0164)
97 #define REG_PMU_APB_SLEEP_XTLON_CTRL                   SCI_ADDR(REGS_PMU_APB_BASE, 0x0168)
98 #define REG_PMU_APB_MEM_SLP_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x016C)
99 #define REG_PMU_APB_MEM_SD_CFG                         SCI_ADDR(REGS_PMU_APB_BASE, 0x0170)
100 #define REG_PMU_APB_CA7_CORE_PU_LOCK                   SCI_ADDR(REGS_PMU_APB_BASE, 0x0174)
101 #define REG_PMU_APB_ARM7_HOLD_CGM_EN                   SCI_ADDR(REGS_PMU_APB_BASE, 0x0178)
102 #define REG_PMU_APB_PWR_CNT_WAIT_CFG0                  SCI_ADDR(REGS_PMU_APB_BASE, 0x017C)
103 #define REG_PMU_APB_PWR_CNT_WAIT_CFG1                  SCI_ADDR(REGS_PMU_APB_BASE, 0x0180)
104 #define REG_PMU_APB_RC0_REL_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0184)
105 #define REG_PMU_APB_RC1_REL_CFG                        SCI_ADDR(REGS_PMU_APB_BASE, 0x0188)
106 #define REG_PMU_APB_RC_CNT_WAIT_CFG                    SCI_ADDR(REGS_PMU_APB_BASE, 0x018C)
107 #define REG_PMU_APB_MEM_AUTO_SLP_CFG                   SCI_ADDR(REGS_PMU_APB_BASE, 0x0190)
108 #define REG_PMU_APB_MEM_AUTO_SD_CFG                    SCI_ADDR(REGS_PMU_APB_BASE, 0x0194)
109 #define REG_PMU_APB_CP0_PD_SHUTDOWN_CFG                SCI_ADDR(REGS_PMU_APB_BASE, 0x0198)
110 #define REG_PMU_APB_CP1_PD_SHUTDOWN_CFG                SCI_ADDR(REGS_PMU_APB_BASE, 0x019C)
111 #define REG_PMU_APB_WAKEUP_LOCK_EN                     SCI_ADDR(REGS_PMU_APB_BASE, 0x01A0)
112 #if defined(CONFIG_MACH_SP9830I)
113 #define REG_PMU_APB_PD_CODEC_TOP_CFG                   SCI_ADDR(REGS_PMU_APB_BASE, 0X01A4)
114 #endif
115 #define REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS     SCI_ADDR(REGS_PMU_APB_BASE, 0x3000)
116 #define REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS     SCI_ADDR(REGS_PMU_APB_BASE, 0x3004)
117 #define REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS     SCI_ADDR(REGS_PMU_APB_BASE, 0x3008)
118 #define REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS     SCI_ADDR(REGS_PMU_APB_BASE, 0x300C)
119 #define REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS    SCI_ADDR(REGS_PMU_APB_BASE, 0x3010)
120 #define REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS     SCI_ADDR(REGS_PMU_APB_BASE, 0x3014)
121 #define REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS    SCI_ADDR(REGS_PMU_APB_BASE, 0x3018)
122 #define REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS     SCI_ADDR(REGS_PMU_APB_BASE, 0x301C)
123 #define REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3020)
124 #define REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3024)
125 #define REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3028)
126 #define REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x302C)
127 #define REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS  SCI_ADDR(REGS_PMU_APB_BASE, 0x3030)
128 #define REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS  SCI_ADDR(REGS_PMU_APB_BASE, 0x3034)
129 #define REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS     SCI_ADDR(REGS_PMU_APB_BASE, 0x3038)
130 #define REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS  SCI_ADDR(REGS_PMU_APB_BASE, 0x303C)
131 #define REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS    SCI_ADDR(REGS_PMU_APB_BASE, 0x3040)
132 #define REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS   SCI_ADDR(REGS_PMU_APB_BASE, 0x3044)
133 #define REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x3048)
134 #define REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS SCI_ADDR(REGS_PMU_APB_BASE, 0x304C)
135 #define REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS    SCI_ADDR(REGS_PMU_APB_BASE, 0x3050)
136 #define REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS    SCI_ADDR(REGS_PMU_APB_BASE, 0x3054)
137 #if defined(CONFIG_MACH_SP9830I)
138 #define REG_PMU_APB_PD_CODEC_TOP_SHUTDOWN_MARK_STATUS  SCI_ADDR(REGS_PMU_APB_BASE, 0x3058)
139 #endif
140
141 /* bits definitions for register REG_PMU_APB_PD_CA7_TOP_CFG */
142 #define BIT_PD_CA7_TOP_DBG_SHUTDOWN_EN                    ( BIT(28) )
143 #define BIT_PD_CA7_TOP_FORCE_SHUTDOWN                     ( BIT(25) )
144 #define BIT_PD_CA7_TOP_AUTO_SHUTDOWN_EN                   ( BIT(24) )
145 #define BITS_PD_CA7_TOP_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
146 #define BITS_PD_CA7_TOP_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
147 #define BITS_PD_CA7_TOP_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
148
149 /* bits definitions for register REG_PMU_APB_PD_CA7_C0_CFG */
150 #define BIT_PD_CA7_C0_WFI_SHUTDOWN_EN                     ( BIT(29) )
151 #define BIT_PD_CA7_C0_DBG_SHUTDOWN_EN                     ( BIT(28) )
152 #define BIT_PD_CA7_C0_FORCE_SHUTDOWN                      ( BIT(25) )
153 #define BIT_PD_CA7_C0_AUTO_SHUTDOWN_EN                    ( BIT(24) )
154 #define BITS_PD_CA7_C0_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
155 #define BITS_PD_CA7_C0_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
156 #define BITS_PD_CA7_C0_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
157
158 /* bits definitions for register REG_PMU_APB_PD_CA7_C1_CFG */
159 #define BIT_PD_CA7_C1_WFI_SHUTDOWN_EN                     ( BIT(29) )
160 #define BIT_PD_CA7_C1_DBG_SHUTDOWN_EN                     ( BIT(28) )
161 #define BIT_PD_CA7_C1_FORCE_SHUTDOWN                      ( BIT(25) )
162 #define BIT_PD_CA7_C1_AUTO_SHUTDOWN_EN                    ( BIT(24) )
163 #define BITS_PD_CA7_C1_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
164 #define BITS_PD_CA7_C1_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
165 #define BITS_PD_CA7_C1_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
166
167 /* bits definitions for register REG_PMU_APB_PD_CA7_C2_CFG */
168 #define BIT_PD_CA7_C2_WFI_SHUTDOWN_EN                     ( BIT(29) )
169 #define BIT_PD_CA7_C2_DBG_SHUTDOWN_EN                     ( BIT(28) )
170 #define BIT_PD_CA7_C2_FORCE_SHUTDOWN                      ( BIT(25) )
171 #define BIT_PD_CA7_C2_AUTO_SHUTDOWN_EN                    ( BIT(24) )
172 #define BITS_PD_CA7_C2_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
173 #define BITS_PD_CA7_C2_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
174 #define BITS_PD_CA7_C2_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
175
176 /* bits definitions for register REG_PMU_APB_PD_CA7_C3_CFG */
177 #define BIT_PD_CA7_C3_WFI_SHUTDOWN_EN                     ( BIT(29) )
178 #define BIT_PD_CA7_C3_DBG_SHUTDOWN_EN                     ( BIT(28) )
179 #define BIT_PD_CA7_C3_FORCE_SHUTDOWN                      ( BIT(25) )
180 #define BIT_PD_CA7_C3_AUTO_SHUTDOWN_EN                    ( BIT(24) )
181 #define BITS_PD_CA7_C3_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
182 #define BITS_PD_CA7_C3_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
183 #define BITS_PD_CA7_C3_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
184
185 /* bits definitions for register REG_PMU_APB_PD_AP_SYS_CFG */
186 #define BIT_PD_AP_SYS_FORCE_SHUTDOWN                      ( BIT(25) )
187 #define BIT_PD_AP_SYS_AUTO_SHUTDOWN_EN                    ( BIT(24) )
188 #define BITS_PD_AP_SYS_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
189 #define BITS_PD_AP_SYS_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
190 #define BITS_PD_AP_SYS_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
191
192 /* bits definitions for register REG_PMU_APB_PD_MM_TOP_CFG */
193 #define BIT_PD_MM_TOP_FORCE_SHUTDOWN                      ( BIT(25) )
194 #define BIT_PD_MM_TOP_AUTO_SHUTDOWN_EN                    ( BIT(24) )
195 #define BITS_PD_MM_TOP_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
196 #define BITS_PD_MM_TOP_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
197 #define BITS_PD_MM_TOP_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
198
199 /* bits definitions for register REG_PMU_APB_PD_GPU_TOP_CFG */
200 #define BIT_PD_GPU_TOP_FORCE_SHUTDOWN                     ( BIT(25) )
201 #define BIT_PD_GPU_TOP_AUTO_SHUTDOWN_EN                   ( BIT(24) )
202 #define BITS_PD_GPU_TOP_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
203 #define BITS_PD_GPU_TOP_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
204 #define BITS_PD_GPU_TOP_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
205
206 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_CFG */
207 #define BIT_PD_CP0_ARM9_0_FORCE_SHUTDOWN                  ( BIT(25) )
208 #define BIT_PD_CP0_ARM9_0_AUTO_SHUTDOWN_EN                ( BIT(24) )
209 #define BITS_PD_CP0_ARM9_0_PWR_ON_DLY(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
210 #define BITS_PD_CP0_ARM9_0_PWR_ON_SEQ_DLY(_X_)            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
211 #define BITS_PD_CP0_ARM9_0_ISO_ON_DLY(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
212
213 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_CFG */
214 #define BIT_PD_CP0_ARM9_1_FORCE_SHUTDOWN                  ( BIT(25) )
215 #define BIT_PD_CP0_ARM9_1_AUTO_SHUTDOWN_EN                ( BIT(24) )
216 #define BITS_PD_CP0_ARM9_1_PWR_ON_DLY(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
217 #define BITS_PD_CP0_ARM9_1_PWR_ON_SEQ_DLY(_X_)            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
218 #define BITS_PD_CP0_ARM9_1_ISO_ON_DLY(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
219
220 /* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_CFG */
221 #define BIT_PD_CP0_HU3GE_FORCE_SHUTDOWN                   ( BIT(25) )
222 #define BIT_PD_CP0_HU3GE_AUTO_SHUTDOWN_EN                 ( BIT(24) )
223 #define BITS_PD_CP0_HU3GE_PWR_ON_DLY(_X_)                 ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
224 #define BITS_PD_CP0_HU3GE_PWR_ON_SEQ_DLY(_X_)             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
225 #define BITS_PD_CP0_HU3GE_ISO_ON_DLY(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
226
227 /* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_CFG */
228 #define BIT_PD_CP0_GSM_0_FORCE_SHUTDOWN                   ( BIT(25) )
229 #define BIT_PD_CP0_GSM_0_AUTO_SHUTDOWN_EN                 ( BIT(24) )
230 #define BITS_PD_CP0_GSM_0_PWR_ON_DLY(_X_)                 ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
231 #define BITS_PD_CP0_GSM_0_PWR_ON_SEQ_DLY(_X_)             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
232 #define BITS_PD_CP0_GSM_0_ISO_ON_DLY(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
233
234 /* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_CFG */
235 #define BIT_PD_CP0_GSM_1_FORCE_SHUTDOWN                   ( BIT(25) )
236 #define BIT_PD_CP0_GSM_1_AUTO_SHUTDOWN_EN                 ( BIT(24) )
237 #define BITS_PD_CP0_GSM_1_PWR_ON_DLY(_X_)                 ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
238 #define BITS_PD_CP0_GSM_1_PWR_ON_SEQ_DLY(_X_)             ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
239 #define BITS_PD_CP0_GSM_1_ISO_ON_DLY(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
240
241 /* bits definitions for register REG_PMU_APB_PD_CP0_TD_CFG */
242 #define BIT_PD_CP0_TD_FORCE_SHUTDOWN                      ( BIT(25) )
243 #define BIT_PD_CP0_TD_AUTO_SHUTDOWN_EN                    ( BIT(24) )
244 #define BITS_PD_CP0_TD_PWR_ON_DLY(_X_)                    ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
245 #define BITS_PD_CP0_TD_PWR_ON_SEQ_DLY(_X_)                ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
246 #define BITS_PD_CP0_TD_ISO_ON_DLY(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
247
248 /* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_CFG */
249 #define BIT_PD_CP0_CEVA_0_FORCE_SHUTDOWN                  ( BIT(25) )
250 #define BIT_PD_CP0_CEVA_0_AUTO_SHUTDOWN_EN                ( BIT(24) )
251 #define BITS_PD_CP0_CEVA_0_PWR_ON_DLY(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
252 #define BITS_PD_CP0_CEVA_0_PWR_ON_SEQ_DLY(_X_)            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
253 #define BITS_PD_CP0_CEVA_0_ISO_ON_DLY(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
254
255 /* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_CFG */
256 #define BIT_PD_CP0_CEVA_1_FORCE_SHUTDOWN                  ( BIT(25) )
257 #define BIT_PD_CP0_CEVA_1_AUTO_SHUTDOWN_EN                ( BIT(24) )
258 #define BITS_PD_CP0_CEVA_1_PWR_ON_DLY(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
259 #define BITS_PD_CP0_CEVA_1_PWR_ON_SEQ_DLY(_X_)            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
260 #define BITS_PD_CP0_CEVA_1_ISO_ON_DLY(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
261
262 /* bits definitions for register REG_PMU_APB_PD_CP0_SYS_CFG */
263
264 /* bits definitions for register REG_PMU_APB_PD_CP1_CA5_CFG */
265 #define BIT_PD_CP1_CA5_FORCE_SHUTDOWN                     ( BIT(25) )
266 #define BIT_PD_CP1_CA5_AUTO_SHUTDOWN_EN                   ( BIT(24) )
267 #define BITS_PD_CP1_CA5_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
268 #define BITS_PD_CP1_CA5_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
269 #define BITS_PD_CP1_CA5_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
270
271 /* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_CFG */
272 #define BIT_PD_CP1_LTE_P1_FORCE_SHUTDOWN                  ( BIT(25) )
273 #define BIT_PD_CP1_LTE_P1_AUTO_SHUTDOWN_EN                ( BIT(24) )
274 #define BITS_PD_CP1_LTE_P1_PWR_ON_DLY(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
275 #define BITS_PD_CP1_LTE_P1_PWR_ON_SEQ_DLY(_X_)            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
276 #define BITS_PD_CP1_LTE_P1_ISO_ON_DLY(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
277
278 /* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_CFG */
279 #define BIT_PD_CP1_LTE_P2_FORCE_SHUTDOWN                  ( BIT(25) )
280 #define BIT_PD_CP1_LTE_P2_AUTO_SHUTDOWN_EN                ( BIT(24) )
281 #define BITS_PD_CP1_LTE_P2_PWR_ON_DLY(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
282 #define BITS_PD_CP1_LTE_P2_PWR_ON_SEQ_DLY(_X_)            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
283 #define BITS_PD_CP1_LTE_P2_ISO_ON_DLY(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
284
285 /* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_CFG */
286 #define BIT_PD_CP1_CEVA_FORCE_SHUTDOWN                    ( BIT(25) )
287 #define BIT_PD_CP1_CEVA_AUTO_SHUTDOWN_EN                  ( BIT(24) )
288 #define BITS_PD_CP1_CEVA_PWR_ON_DLY(_X_)                  ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
289 #define BITS_PD_CP1_CEVA_PWR_ON_SEQ_DLY(_X_)              ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
290 #define BITS_PD_CP1_CEVA_ISO_ON_DLY(_X_)                  ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
291
292 /* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_CFG */
293 #define BIT_PD_CP1_COMWRAP_FORCE_SHUTDOWN                 ( BIT(25) )
294 #define BIT_PD_CP1_COMWRAP_AUTO_SHUTDOWN_EN               ( BIT(24) )
295 #define BITS_PD_CP1_COMWRAP_PWR_ON_DLY(_X_)               ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
296 #define BITS_PD_CP1_COMWRAP_PWR_ON_SEQ_DLY(_X_)           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
297 #define BITS_PD_CP1_COMWRAP_ISO_ON_DLY(_X_)               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
298
299 /* bits definitions for register REG_PMU_APB_PD_PUB_SYS_CFG */
300 #define BIT_PD_PUB_SYS_FORCE_SHUTDOWN                     ( BIT(25) )
301 #define BIT_PD_PUB_SYS_AUTO_SHUTDOWN_EN                   ( BIT(24) )
302 #define BITS_PD_PUB_SYS_PWR_ON_DLY(_X_)                   ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
303 #define BITS_PD_PUB_SYS_PWR_ON_SEQ_DLY(_X_)               ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
304 #define BITS_PD_PUB_SYS_ISO_ON_DLY(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
305
306 /* bits definitions for register REG_PMU_APB_AP_WAKEUP_POR_CFG */
307 #define BIT_AP_WAKEUP_POR_N                               ( BIT(0) )
308
309 /* bits definitions for register REG_PMU_APB_XTL_WAIT_CNT */
310 #define BITS_XTL1_WAIT_CNT(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
311 #define BITS_XTL0_WAIT_CNT(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
312
313 /* bits definitions for register REG_PMU_APB_XTLBUF_WAIT_CNT */
314 #define BITS_XTLBUF1_WAIT_CNT(_X_)                        ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
315 #define BITS_XTLBUF0_WAIT_CNT(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
316
317 /* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT1 */
318 #define BITS_LTEPLL_WAIT_CNT(_X_)                         ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
319 #define BITS_TWPLL_WAIT_CNT(_X_)                          ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
320 #define BITS_DPLL_WAIT_CNT(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
321 #define BITS_MPLL_WAIT_CNT(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
322
323 /* bits definitions for register REG_PMU_APB_PLL_WAIT_CNT2 */
324 #define BITS_LVDSDIS_PLL_WAIT_CNT(_X_)                    ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
325
326 /* bits definitions for register REG_PMU_APB_XTL0_REL_CFG */
327 #define BIT_XTL0_ARM7_SEL                                 ( BIT(5) )
328 #define BIT_XTL0_VCP1_SEL                                 ( BIT(4) )
329 #define BIT_XTL0_VCP0_SEL                                 ( BIT(3) )
330 #define BIT_XTL0_CP1_SEL                                  ( BIT(2) )
331 #define BIT_XTL0_CP0_SEL                                  ( BIT(1) )
332 #define BIT_XTL0_AP_SEL                                   ( BIT(0) )
333
334 /* bits definitions for register REG_PMU_APB_XTL1_REL_CFG */
335 #define BIT_XTL1_ARM7_SEL                                 ( BIT(5) )
336 #define BIT_XTL1_VCP1_SEL                                 ( BIT(4) )
337 #define BIT_XTL1_VCP0_SEL                                 ( BIT(3) )
338 #define BIT_XTL1_CP1_SEL                                  ( BIT(2) )
339 #define BIT_XTL1_CP0_SEL                                  ( BIT(1) )
340 #define BIT_XTL1_AP_SEL                                   ( BIT(0) )
341
342 /* bits definitions for register REG_PMU_APB_XTLBUF0_REL_CFG */
343 #define BIT_XTLBUF0_ARM7_SEL                              ( BIT(5) )
344 #define BIT_XTLBUF0_VCP1_SEL                              ( BIT(4) )
345 #define BIT_XTLBUF0_VCP0_SEL                              ( BIT(3) )
346 #define BIT_XTLBUF0_CP1_SEL                               ( BIT(2) )
347 #define BIT_XTLBUF0_CP0_SEL                               ( BIT(1) )
348 #define BIT_XTLBUF0_AP_SEL                                ( BIT(0) )
349
350 /* bits definitions for register REG_PMU_APB_XTLBUF1_REL_CFG */
351 #define BIT_XTLBUF1_ARM7_SEL                              ( BIT(5) )
352 #define BIT_XTLBUF1_VCP1_SEL                              ( BIT(4) )
353 #define BIT_XTLBUF1_VCP0_SEL                              ( BIT(3) )
354 #define BIT_XTLBUF1_CP1_SEL                               ( BIT(2) )
355 #define BIT_XTLBUF1_CP0_SEL                               ( BIT(1) )
356 #define BIT_XTLBUF1_AP_SEL                                ( BIT(0) )
357
358 /* bits definitions for register REG_PMU_APB_MPLL_REL_CFG */
359 #define BIT_MPLL_REF_SEL                                  ( BIT(8) )
360 #define BIT_MPLL_ARM7_SEL                                 ( BIT(5) )
361 #define BIT_MPLL_VCP1_SEL                                 ( BIT(4) )
362 #define BIT_MPLL_VCP0_SEL                                 ( BIT(3) )
363 #define BIT_MPLL_CP1_SEL                                  ( BIT(2) )
364 #define BIT_MPLL_CP0_SEL                                  ( BIT(1) )
365 #define BIT_MPLL_AP_SEL                                   ( BIT(0) )
366
367 /* bits definitions for register REG_PMU_APB_DPLL_REL_CFG */
368 #define BIT_DPLL_REF_SEL                                  ( BIT(8) )
369 #define BIT_DPLL_ARM7_SEL                                 ( BIT(5) )
370 #define BIT_DPLL_VCP1_SEL                                 ( BIT(4) )
371 #define BIT_DPLL_VCP0_SEL                                 ( BIT(3) )
372 #define BIT_DPLL_CP1_SEL                                  ( BIT(2) )
373 #define BIT_DPLL_CP0_SEL                                  ( BIT(1) )
374 #define BIT_DPLL_AP_SEL                                   ( BIT(0) )
375
376 /* bits definitions for register REG_PMU_APB_LTEPLL_REL_CFG */
377 #define BIT_LTEPLL_REF_SEL                                ( BIT(8) )
378 #define BIT_LTEPLL_ARM7_SEL                               ( BIT(5) )
379 #define BIT_LTEPLL_VCP1_SEL                               ( BIT(4) )
380 #define BIT_LTEPLL_VCP0_SEL                               ( BIT(3) )
381 #define BIT_LTEPLL_CP1_SEL                                ( BIT(2) )
382 #define BIT_LTEPLL_CP0_SEL                                ( BIT(1) )
383 #define BIT_LTEPLL_AP_SEL                                 ( BIT(0) )
384
385 /* bits definitions for register REG_PMU_APB_TWPLL_REL_CFG */
386 #define BIT_TWPLL_REF_SEL                                 ( BIT(8) )
387 #define BIT_TWPLL_ARM7_SEL                                ( BIT(5) )
388 #define BIT_TWPLL_VCP1_SEL                                ( BIT(4) )
389 #define BIT_TWPLL_VCP0_SEL                                ( BIT(3) )
390 #define BIT_TWPLL_CP1_SEL                                 ( BIT(2) )
391 #define BIT_TWPLL_CP0_SEL                                 ( BIT(1) )
392 #define BIT_TWPLL_AP_SEL                                  ( BIT(0) )
393
394 /* bits definitions for register REG_PMU_APB_LVDSDIS_PLL_REL_CFG */
395 #define BIT_LVDSDIS_PLL_REF_SEL                           ( BIT(8) )
396 #define BIT_LVDSDIS_PLL_ARM7_SEL                          ( BIT(5) )
397 #define BIT_LVDSDIS_PLL_VCP1_SEL                          ( BIT(4) )
398 #define BIT_LVDSDIS_PLL_VCP0_SEL                          ( BIT(3) )
399 #define BIT_LVDSDIS_PLL_CP1_SEL                           ( BIT(2) )
400 #define BIT_LVDSDIS_PLL_CP0_SEL                           ( BIT(1) )
401 #define BIT_LVDSDIS_PLL_AP_SEL                            ( BIT(0) )
402
403 /* bits definitions for register REG_PMU_APB_CP_SOFT_RST */
404 #define BIT_ARM7_SOFT_RST                                 ( BIT(8) )
405 #define BIT_PUB_SOFT_RST                                  ( BIT(6) )
406 #define BIT_AP_SOFT_RST                                   ( BIT(5) )
407 #define BIT_GPU_SOFT_RST                                  ( BIT(4) )
408 #define BIT_MM_SOFT_RST                                   ( BIT(3) )
409 #if defined(CONFIG_MACH_SP9830I)
410 #define BIT_CODEC_SOFT_RST                                (bit(2))
411 #endif
412 #define BIT_CP1_SOFT_RST                                  ( BIT(1) )
413 #define BIT_CP0_SOFT_RST                                  ( BIT(0) )
414
415 /* bits definitions for register REG_PMU_APB_CP_SLP_STATUS_DBG0 */
416 #define BITS_CP1_DEEP_SLP_DBG(_X_)                        ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
417 #define BITS_CP0_DEEP_SLP_DBG(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
418
419 /* bits definitions for register REG_PMU_APB_PWR_STATUS0_DBG */
420 #define BITS_PD_MM_TOP_STATE(_X_)                         ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
421 #define BITS_PD_GPU_TOP_STATE(_X_)                        ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
422 #define BITS_PD_AP_SYS_STATE(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
423 #define BITS_PD_CA7_C3_STATE(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
424 #define BITS_PD_CA7_C2_STATE(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
425 #define BITS_PD_CA7_C1_STATE(_X_)                         ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
426 #define BITS_PD_CA7_C0_STATE(_X_)                         ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
427 #define BITS_PD_CA7_TOP_STATE(_X_)                        ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
428
429 /* bits definitions for register REG_PMU_APB_PWR_STATUS1_DBG */
430 #define BITS_PD_CP0_CEVA_1_STATE(_X_)                     ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
431 #define BITS_PD_CP0_CEVA_0_STATE(_X_)                     ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
432 #define BITS_PD_CP0_GSM_0_STATE(_X_)                      ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
433 #define BITS_PD_CP0_GSM_1_STATE(_X_)                      ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
434 #define BITS_PD_CP0_HU3GE_STATE(_X_)                      ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
435 #define BITS_PD_CP0_ARM9_1_STATE(_X_)                     ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
436 #define BITS_PD_CP0_ARM9_0_STATE(_X_)                     ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
437 #define BITS_PD_CP0_TD_STATE(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
438
439 /* bits definitions for register REG_PMU_APB_PWR_STATUS2_DBG */
440 #define BITS_PD_PUB_SYS_STATE(_X_)                        ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
441 #define BITS_PD_CP1_COMWRAP_STATE(_X_)                    ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
442 #define BITS_PD_CP1_LTE_P2_STATE(_X_)                     ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
443 #define BITS_PD_CP1_LTE_P1_STATE(_X_)                     ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
444 #define BITS_PD_CP1_CEVA_STATE(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
445 #define BITS_PD_CP1_CA5_STATE(_X_)                        ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
446
447 /* bits definitions for register REG_PMU_APB_SLEEP_CTRL */
448 #define BIT_VCP1_FORCE_LIGHT_SLEEP                        ( BIT(28) )
449 #define BIT_VCP0_FORCE_LIGHT_SLEEP                        ( BIT(27) )
450 #define BIT_CP1_FORCE_LIGHT_SLEEP                         ( BIT(26) )
451 #define BIT_CP0_FORCE_LIGHT_SLEEP                         ( BIT(25) )
452 #define BIT_AP_FORCE_LIGHT_SLEEP                          ( BIT(24) )
453 #define BIT_ARM7_FORCE_DEEP_SLEEP                         ( BIT(21) )
454 #define BIT_VCP1_FORCE_DEEP_SLEEP                         ( BIT(20) )
455 #define BIT_VCP0_FORCE_DEEP_SLEEP                         ( BIT(19) )
456 #define BIT_CP1_FORCE_DEEP_SLEEP                          ( BIT(18) )
457 #define BIT_CP0_FORCE_DEEP_SLEEP                          ( BIT(17) )
458 #define BIT_AP_FORCE_DEEP_SLEEP                           ( BIT(16) )
459 #define BIT_VCP1_LIGHT_SLEEP                              ( BIT(12) )
460 #define BIT_VCP0_LIGHT_SLEEP                              ( BIT(11) )
461 #define BIT_CP1_LIGHT_SLEEP                               ( BIT(10) )
462 #define BIT_CP0_LIGHT_SLEEP                               ( BIT(9) )
463 #define BIT_AP_LIGHT_SLEEP                                ( BIT(8) )
464 #define BIT_VCP1_DEEP_SLEEP                               ( BIT(4) )
465 #define BIT_VCP0_DEEP_SLEEP                               ( BIT(3) )
466 #define BIT_CP1_DEEP_SLEEP                                ( BIT(2) )
467 #define BIT_CP0_DEEP_SLEEP                                ( BIT(1) )
468 #define BIT_AP_DEEP_SLEEP                                 ( BIT(0) )
469
470 /* bits definitions for register REG_PMU_APB_DDR_SLEEP_CTRL */
471 #define BIT_BUSY_TRANSFER_HWDATA_SEL                      ( BIT(16) )
472 #define BIT_DDR_PUBL_APB_SOFT_RST                         ( BIT(12) )
473 #define BIT_DDR_UMCTL_APB_SOFT_RST                        ( BIT(11) )
474 #define BIT_DDR_PUBL_SOFT_RST                             ( BIT(10) )
475 #define BIT_DDR_PHY_SOFT_RST                              ( BIT(8) )
476 #define BIT_DDR_PHY_AUTO_GATE_EN                          ( BIT(6) )
477 #define BIT_DDR_PUBL_AUTO_GATE_EN                         ( BIT(5) )
478 #define BIT_DDR_UMCTL_AUTO_GATE_EN                        ( BIT(4) )
479 #define BIT_DDR_PHY_EB                                    ( BIT(2) )
480 #define BIT_DDR_UMCTL_EB                                  ( BIT(1) )
481 #define BIT_DDR_PUBL_EB                                   ( BIT(0) )
482
483 /* bits definitions for register REG_PMU_APB_SLEEP_STATUS */
484 #define BITS_ARM7_SLP_STATUS(_X_)                         ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
485 #define BITS_VCP1_SLP_STATUS(_X_)                         ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
486 #define BITS_VCP0_SLP_STATUS(_X_)                         ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
487 #define BITS_CP1_SLP_STATUS(_X_)                          ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
488 #define BITS_CP0_SLP_STATUS(_X_)                          ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
489 #define BITS_AP_SLP_STATUS(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
490
491 /* bits definitions for register REG_PMU_APB_CA7_TOP_CFG */
492 #define BIT_CA7_L2RSTDISABLE                              ( BIT(0) )
493
494 /* bits definitions for register REG_PMU_APB_CA7_C0_CFG */
495 #define BIT_CA7_VINITHI_C0                                ( BIT(0) )
496
497 /* bits definitions for register REG_PMU_APB_CA7_C1_CFG */
498 #define BIT_CA7_VINITHI_C1                                ( BIT(0) )
499
500 /* bits definitions for register REG_PMU_APB_CA7_C2_CFG */
501 #define BIT_CA7_VINITHI_C2                                ( BIT(0) )
502
503 /* bits definitions for register REG_PMU_APB_CA7_C3_CFG */
504 #define BIT_CA7_VINITHI_C3                                ( BIT(0) )
505
506 /* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL0 */
507 #define BIT_DDR_CTRL_AXI_LP_EN                            ( BIT(31) )
508 #define BIT_DDR_CTRL_CGM_SEL                              ( BIT(30) )
509 #define BIT_DDR_CHN9_AXI_LP_EN                            ( BIT(25) )
510 #define BIT_DDR_CHN8_AXI_LP_EN                            ( BIT(24) )
511 #define BIT_DDR_CHN7_AXI_LP_EN                            ( BIT(23) )
512 #define BIT_DDR_CHN6_AXI_LP_EN                            ( BIT(22) )
513 #define BIT_DDR_CHN5_AXI_LP_EN                            ( BIT(21) )
514 #define BIT_DDR_CHN4_AXI_LP_EN                            ( BIT(20) )
515 #define BIT_DDR_CHN3_AXI_LP_EN                            ( BIT(19) )
516 #define BIT_DDR_CHN2_AXI_LP_EN                            ( BIT(18) )
517 #define BIT_DDR_CHN1_AXI_LP_EN                            ( BIT(17) )
518 #define BIT_DDR_CHN0_AXI_LP_EN                            ( BIT(16) )
519 #define BIT_DDR_CHN9_CGM_SEL                              ( BIT(9) )
520 #define BIT_DDR_CHN8_CGM_SEL                              ( BIT(8) )
521 #define BIT_DDR_CHN7_CGM_SEL                              ( BIT(7) )
522 #define BIT_DDR_CHN6_CGM_SEL                              ( BIT(6) )
523 #define BIT_DDR_CHN5_CGM_SEL                              ( BIT(5) )
524 #define BIT_DDR_CHN4_CGM_SEL                              ( BIT(4) )
525 #define BIT_DDR_CHN3_CGM_SEL                              ( BIT(3) )
526 #define BIT_DDR_CHN2_CGM_SEL                              ( BIT(2) )
527 #define BIT_DDR_CHN1_CGM_SEL                              ( BIT(1) )
528 #define BIT_DDR_CHN0_CGM_SEL                              ( BIT(0) )
529
530 /* bits definitions for register REG_PMU_APB_DDR_CHN_SLEEP_CTRL1 */
531 #define BIT_DDR_CHN9_AXI_STOP_SEL                         ( BIT(9) )
532 #define BIT_DDR_CHN8_AXI_STOP_SEL                         ( BIT(8) )
533 #define BIT_DDR_CHN7_AXI_STOP_SEL                         ( BIT(7) )
534 #define BIT_DDR_CHN6_AXI_STOP_SEL                         ( BIT(6) )
535 #define BIT_DDR_CHN5_AXI_STOP_SEL                         ( BIT(5) )
536 #define BIT_DDR_CHN4_AXI_STOP_SEL                         ( BIT(4) )
537 #define BIT_DDR_CHN3_AXI_STOP_SEL                         ( BIT(3) )
538 #define BIT_DDR_CHN2_AXI_STOP_SEL                         ( BIT(2) )
539 #define BIT_DDR_CHN1_AXI_STOP_SEL                         ( BIT(1) )
540 #define BIT_DDR_CHN0_AXI_STOP_SEL                         ( BIT(0) )
541
542 /* bits definitions for register REG_PMU_APB_DDR_OP_MODE_CFG */
543 #define BIT_DDR_OPERATE_MODE_BUSY                         ( BIT(28) )
544 #define BIT_DDR_PUBL_RET_EN                               ( BIT(27) )
545 #define BIT_DDR_PHY_ISO_RST_EN                            ( BIT(26) )
546 #define BIT_DDR_UMCTL_RET_EN                              ( BIT(25) )
547 #define BIT_DDR_PHY_AUTO_RET_EN                           ( BIT(24) )
548 #define BITS_DDR_OPERATE_MODE_CNT_LMT(_X_)                ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
549 #define BITS_DDR_OPERATE_MODE(_X_)                        ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
550 #define BITS_DDR_OPERATE_MODE_IDLE(_X_)                   ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
551
552 /* bits definitions for register REG_PMU_APB_DDR_PHY_RET_CFG */
553 #define BIT_DDR_UMCTL_SOFT_RST                            ( BIT(16) )
554 #define BIT_DDR_PHY_CKE_RET_EN                            ( BIT(0) )
555
556 /* bits definitions for register REG_PMU_APB_26M_SEL_CFG */
557 #define BIT_AON_RC_4M_SEL                                 ( BIT(8) )
558 #define BIT_GGE_26M_SEL                                   ( BIT(6) )
559 #define BIT_PUB_26M_SEL                                   ( BIT(5) )
560 #define BIT_AON_26M_SEL                                   ( BIT(4) )
561 #define BIT_CP1_26M_SEL                                   ( BIT(2) )
562 #define BIT_CP0_26M_SEL                                   ( BIT(1) )
563 #define BIT_AP_26M_SEL                                    ( BIT(0) )
564
565 /* bits definitions for register REG_PMU_APB_BISR_DONE_STATUS */
566 #define BIT_PD_CP1_COMWRAP_BISR_DONE                      ( BIT(21) )
567 #define BIT_PD_CP1_LTE_P2_BISR_DONE                       ( BIT(20) )
568 #define BIT_PD_CP1_LTE_P1_BISR_DONE                       ( BIT(19) )
569 #define BIT_PD_CP1_CEVA_BISR_DONE                         ( BIT(18) )
570 #define BIT_PD_CP1_CA5_BISR_DONE                          ( BIT(17) )
571 #define BIT_PD_CP0_HU3GE_BISR_DONE                        ( BIT(15) )
572 #define BIT_PD_CP0_TD_BISR_DONE                           ( BIT(14) )
573 #define BIT_PD_CP0_GSM_1_BISR_DONE                        ( BIT(13) )
574 #define BIT_PD_CP0_GSM_0_BISR_DONE                        ( BIT(12) )
575 #define BIT_PD_CP0_CEVA_1_BISR_DONE                       ( BIT(11) )
576 #define BIT_PD_CP0_CEVA_0_BISR_DONE                       ( BIT(10) )
577 #define BIT_PD_CP0_ARM9_1_BISR_DONE                       ( BIT(9) )
578 #define BIT_PD_CP0_ARM9_0_BISR_DONE                       ( BIT(8) )
579 #define BIT_PD_MM_TOP_BISR_DONE                           ( BIT(7) )
580 #define BIT_PD_GPU_TOP_BISR_DONE                          ( BIT(6) )
581 #define BIT_PD_AP_SYS_BISR_DONE                           ( BIT(5) )
582 #define BIT_PD_CA7_TOP_BISR_DONE                          ( BIT(4) )
583 #define BIT_PD_CA7_C3_BISR_DONE                           ( BIT(3) )
584 #define BIT_PD_CA7_C2_BISR_DONE                           ( BIT(2) )
585 #define BIT_PD_CA7_C1_BISR_DONE                           ( BIT(1) )
586 #define BIT_PD_CA7_C0_BISR_DONE                           ( BIT(0) )
587
588 /* bits definitions for register REG_PMU_APB_BISR_BUSY_STATUS */
589 #define BIT_PD_CP1_COMWRAP_BISR_BUSY                      ( BIT(21) )
590 #define BIT_PD_CP1_LTE_P2_BISR_BUSY                       ( BIT(20) )
591 #define BIT_PD_CP1_LTE_P1_BISR_BUSY                       ( BIT(19) )
592 #define BIT_PD_CP1_CEVA_BISR_BUSY                         ( BIT(18) )
593 #define BIT_PD_CP1_CA5_BISR_BUSY                          ( BIT(17) )
594 #define BIT_PD_CP0_HU3GE_BISR_BUSY                        ( BIT(15) )
595 #define BIT_PD_CP0_TD_BISR_BUSY                           ( BIT(14) )
596 #define BIT_PD_CP0_GSM_1_BISR_BUSY                        ( BIT(13) )
597 #define BIT_PD_CP0_GSM_0_BISR_BUSY                        ( BIT(12) )
598 #define BIT_PD_CP0_CEVA_1_BISR_BUSY                       ( BIT(11) )
599 #define BIT_PD_CP0_CEVA_0_BISR_BUSY                       ( BIT(10) )
600 #define BIT_PD_CP0_ARM9_1_BISR_BUSY                       ( BIT(9) )
601 #define BIT_PD_CP0_ARM9_0_BISR_BUSY                       ( BIT(8) )
602 #define BIT_PD_MM_TOP_BISR_BUSY                           ( BIT(7) )
603 #define BIT_PD_GPU_TOP_BISR_BUSY                          ( BIT(6) )
604 #define BIT_PD_AP_SYS_BISR_BUSY                           ( BIT(5) )
605 #define BIT_PD_CA7_TOP_BISR_BUSY                          ( BIT(4) )
606 #define BIT_PD_CA7_C3_BISR_BUSY                           ( BIT(3) )
607 #define BIT_PD_CA7_C2_BISR_BUSY                           ( BIT(2) )
608 #define BIT_PD_CA7_C1_BISR_BUSY                           ( BIT(1) )
609 #define BIT_PD_CA7_C0_BISR_BUSY                           ( BIT(0) )
610
611 /* bits definitions for register REG_PMU_APB_BISR_BYP_CFG */
612 #define BIT_PD_CP1_COMWRAP_BISR_FORCE_BYP                 ( BIT(21) )
613 #define BIT_PD_CP1_LTE_P2_BISR_FORCE_BYP                  ( BIT(20) )
614 #define BIT_PD_CP1_LTE_P1_BISR_FORCE_BYP                  ( BIT(19) )
615 #define BIT_PD_CP1_CEVA_BISR_FORCE_BYP                    ( BIT(18) )
616 #define BIT_PD_CP1_CA5_BISR_FORCE_BYP                     ( BIT(17) )
617 #if defined(CONFIG_MACH_SP9830I)
618 #define BIT_PD_CODEC_TOP_BISR_FORCE_BYP                   (BIT(16))
619 #endif
620 #define BIT_PD_CP0_HU3GE_BISR_FORCE_BYP                   ( BIT(15) )
621 #define BIT_PD_CP0_TD_BISR_FORCE_BYP                      ( BIT(14) )
622 #define BIT_PD_CP0_GSM_1_BISR_FORCE_BYP                   ( BIT(13) )
623 #define BIT_PD_CP0_GSM_0_BISR_FORCE_BYP                   ( BIT(12) )
624 #define BIT_PD_CP0_CEVA_1_BISR_FORCE_BYP                  ( BIT(11) )
625 #define BIT_PD_CP0_CEVA_0_BISR_FORCE_BYP                  ( BIT(10) )
626 #define BIT_PD_CP0_ARM9_1_BISR_FORCE_BYP                  ( BIT(9) )
627 #define BIT_PD_CP0_ARM9_0_BISR_FORCE_BYP                  ( BIT(8) )
628 #define BIT_PD_MM_TOP_BISR_FORCE_BYP                      ( BIT(7) )
629 #define BIT_PD_GPU_TOP_BISR_FORCE_BYP                     ( BIT(6) )
630 #define BIT_PD_AP_SYS_BISR_FORCE_BYP                      ( BIT(5) )
631 #define BIT_PD_CA7_TOP_BISR_FORCE_BYP                     ( BIT(4) )
632 #define BIT_PD_CA7_C3_BISR_FORCE_BYP                      ( BIT(3) )
633 #define BIT_PD_CA7_C2_BISR_FORCE_BYP                      ( BIT(2) )
634 #define BIT_PD_CA7_C1_BISR_FORCE_BYP                      ( BIT(1) )
635 #define BIT_PD_CA7_C0_BISR_FORCE_BYP                      ( BIT(0) )
636
637 /* bits definitions for register REG_PMU_APB_BISR_EN_CFG */
638 #define BIT_PD_CP1_COMWRAP_BISR_FORCE_EN                  ( BIT(21) )
639 #define BIT_PD_CP1_LTE_P2_BISR_FORCE_EN                   ( BIT(20) )
640 #define BIT_PD_CP1_LTE_P1_BISR_FORCE_EN                   ( BIT(19) )
641 #define BIT_PD_CP1_CEVA_BISR_FORCE_EN                     ( BIT(18) )
642 #define BIT_PD_CP1_CA5_BISR_FORCE_EN                      ( BIT(17) )
643 #if defined(CONFIG_MACH_SP9830I)
644 #define BIT_CODEC_TOP_BISR_FORCE_EN                       (BIT(16))
645 #endif
646 #define BIT_PD_CP0_HU3GE_BISR_FORCE_EN                    ( BIT(15) )
647 #define BIT_PD_CP0_TD_BISR_FORCE_EN                       ( BIT(14) )
648 #define BIT_PD_CP0_GSM_1_BISR_FORCE_EN                    ( BIT(13) )
649 #define BIT_PD_CP0_GSM_0_BISR_FORCE_EN                    ( BIT(12) )
650 #define BIT_PD_CP0_CEVA_1_BISR_FORCE_EN                   ( BIT(11) )
651 #define BIT_PD_CP0_CEVA_0_BISR_FORCE_EN                   ( BIT(10) )
652 #define BIT_PD_CP0_ARM9_1_BISR_FORCE_EN                   ( BIT(9) )
653 #define BIT_PD_CP0_ARM9_0_BISR_FORCE_EN                   ( BIT(8) )
654 #define BIT_PD_MM_TOP_BISR_FORCE_EN                       ( BIT(7) )
655 #define BIT_PD_GPU_TOP_BISR_FORCE_EN                      ( BIT(6) )
656 #define BIT_PD_AP_SYS_BISR_FORCE_EN                       ( BIT(5) )
657 #define BIT_PD_CA7_TOP_BISR_FORCE_EN                      ( BIT(4) )
658 #define BIT_PD_CA7_C3_BISR_FORCE_EN                       ( BIT(3) )
659 #define BIT_PD_CA7_C2_BISR_FORCE_EN                       ( BIT(2) )
660 #define BIT_PD_CA7_C1_BISR_FORCE_EN                       ( BIT(1) )
661 #define BIT_PD_CA7_C0_BISR_FORCE_EN                       ( BIT(0) )
662
663 /* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG0 */
664 #define BITS_CGM_AUTO_GATE_SEL_CFG0(_X_)                  (_X_)
665
666 /* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG1 */
667 #define BITS_CGM_AUTO_GATE_SEL_CFG1(_X_)                  (_X_)
668
669 /* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG2 */
670 #define BITS_CGM_AUTO_GATE_SEL_CFG2(_X_)                  (_X_)
671
672 /* bits definitions for register REG_PMU_APB_CGM_AUTO_GATE_SEL_CFG3 */
673 #define BITS_CGM_AUTO_GATE_SEL_CFG3(_X_)                  (_X_)
674
675 /* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG0 */
676 #define BITS_CGM_FORCE_EN_CFG0(_X_)                       (_X_)
677
678 /* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG1 */
679 #define BITS_CGM_FORCE_EN_CFG1(_X_)                       (_X_)
680
681 /* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG2 */
682 #define BITS_CGM_FORCE_EN_CFG2(_X_)                       (_X_)
683
684 /* bits definitions for register REG_PMU_APB_CGM_FORCE_EN_CFG3 */
685 #define BITS_CGM_FORCE_EN_CFG3(_X_)                       (_X_)
686
687 /* bits definitions for register REG_PMU_APB_SLEEP_XTLON_CTRL */
688 #define BIT_ARM7_SLEEP_XTL_ON                             ( BIT(5) )
689 #define BIT_VCP1_SLEEP_XTL_ON                             ( BIT(4) )
690 #define BIT_VCP0_SLEEP_XTL_ON                             ( BIT(3) )
691 #define BIT_CP1_SLEEP_XTL_ON                              ( BIT(2) )
692 #define BIT_CP0_SLEEP_XTL_ON                              ( BIT(1) )
693 #define BIT_AP_SLEEP_XTL_ON                               ( BIT(0) )
694
695 /* bits definitions for register REG_PMU_APB_MEM_SLP_CFG */
696 #define BITS_MEM_SLP_CFG(_X_)                             (_X_)
697
698 /* bits definitions for register REG_PMU_APB_MEM_SD_CFG */
699 #define BITS_MEM_SD_CFG(_X_)                              (_X_)
700
701 /* bits definitions for register REG_PMU_APB_CA7_CORE_PU_LOCK */
702 #define BIT_CA7_C3_GIC_WAKEUP_EN                          ( BIT(11) )
703 #define BIT_CA7_C2_GIC_WAKEUP_EN                          ( BIT(10) )
704 #define BIT_CA7_C1_GIC_WAKEUP_EN                          ( BIT(9) )
705 #define BIT_CA7_C0_GIC_WAKEUP_EN                          ( BIT(8) )
706 #define BIT_CA7_C3_PU_LOCK                                ( BIT(3) )
707 #define BIT_CA7_C2_PU_LOCK                                ( BIT(2) )
708 #define BIT_CA7_C1_PU_LOCK                                ( BIT(1) )
709 #define BIT_CA7_C0_PU_LOCK                                ( BIT(0) )
710
711 /* bits definitions for register REG_PMU_APB_ARM7_HOLD_CGM_EN */
712 #define BIT_PD_CP1_CEVA_CGM_HOLD_EN                       ( BIT(10) )
713 #define BIT_PD_CP1_CA5_CGM_HOLD_EN                        ( BIT(9) )
714 #define BIT_PD_CP0_CEVA_1_CGM_HOLD_EN                     ( BIT(8) )
715 #define BIT_PD_CP0_CEVA_0_CGM_HOLD_EN                     ( BIT(7) )
716 #define BIT_PD_CP0_ARM9_1_CGM_HOLD_EN                     ( BIT(6) )
717 #define BIT_PD_CP0_ARM9_0_CGM_HOLD_EN                     ( BIT(5) )
718 #define BIT_PD_CA7_TOP_CMG_HOLD_EN                        ( BIT(4) )
719 #define BIT_PD_CA7_C3_CMG_HOLD_EN                         ( BIT(3) )
720 #define BIT_PD_CA7_C2_CMG_HOLD_EN                         ( BIT(2) )
721 #define BIT_PD_CA7_C1_CMG_HOLD_EN                         ( BIT(1) )
722 #define BIT_PD_CA7_C0_CMG_HOLD_EN                         ( BIT(0) )
723
724 /* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG0 */
725 #define BITS_VCP0_PWR_WAIT_CNT(_X_)                       ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
726 #define BITS_CP1_PWR_WAIT_CNT(_X_)                        ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
727 #define BITS_CP0_PWR_WAIT_CNT(_X_)                        ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
728 #define BITS_AP_PWR_WAIT_CNT(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
729
730 /* bits definitions for register REG_PMU_APB_PWR_CNT_WAIT_CFG1 */
731 #define BITS_ARM7_PWR_WAIT_CNT(_X_)                       ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
732 #define BITS_VCP1_PWR_WAIT_CNT(_X_)                       ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
733
734 /* bits definitions for register REG_PMU_APB_RC0_REL_CFG */
735 #define BIT_RC0_ARM7_SEL                                  ( BIT(5) )
736 #define BIT_RC0_VCP1_SEL                                  ( BIT(4) )
737 #define BIT_RC0_VCP0_SEL                                  ( BIT(3) )
738 #define BIT_RC0_CP1_SEL                                   ( BIT(2) )
739 #define BIT_RC0_CP0_SEL                                   ( BIT(1) )
740 #define BIT_RC0_AP_SEL                                    ( BIT(0) )
741
742 /* bits definitions for register REG_PMU_APB_RC1_REL_CFG */
743 #define BIT_RC1_ARM7_SEL                                  ( BIT(5) )
744 #define BIT_RC1_VCP1_SEL                                  ( BIT(4) )
745 #define BIT_RC1_VCP0_SEL                                  ( BIT(3) )
746 #define BIT_RC1_CP1_SEL                                   ( BIT(2) )
747 #define BIT_RC1_CP0_SEL                                   ( BIT(1) )
748 #define BIT_RC1_AP_SEL                                    ( BIT(0) )
749
750 /* bits definitions for register REG_PMU_APB_RC_CNT_WAIT_CFG */
751 #define BITS_RC1_WAIT_CNT(_X_)                            ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
752 #define BITS_RC0_WAIT_CNT(_X_)                            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
753
754 /* bits definitions for register REG_PMU_APB_MEM_AUTO_SLP_CFG */
755 #define BITS_MEM_AUTO_SLP_EN(_X_)                         (_X_)
756
757 /* bits definitions for register REG_PMU_APB_MEM_AUTO_SD_CFG */
758 #define BITS_MEM_AUTO_SD_EN(_X_)                          (_X_)
759
760 /* bits definitions for register REG_PMU_APB_CP0_PD_SHUTDOWN_CFG */
761 #define BIT_PD_CP0_HU3GE_VCP1_SEL                         ( BIT(20) )
762 #define BIT_PD_CP0_TD_VCP1_SEL                            ( BIT(19) )
763 #define BIT_PD_CP0_GSM_0_VCP1_SEL                         ( BIT(18) )
764 #define BIT_PD_CP0_CEVA_0_VCP1_SEL                        ( BIT(17) )
765 #define BIT_PD_CP0_ARM9_1_VCP1_SEL                        ( BIT(16) )
766 #define BIT_PD_CP0_ARM9_0_VCP0_SEL                        ( BIT(8) )
767 #define BIT_PD_CP0_HU3GE_CP0_SEL                          ( BIT(5) )
768 #define BIT_PD_CP0_TD_CP0_SEL                             ( BIT(4) )
769 #define BIT_PD_CP0_GSM_0_CP0_SEL                          ( BIT(3) )
770 #define BIT_PD_CP0_CEVA_0_CP0_SEL                         ( BIT(2) )
771 #define BIT_PD_CP0_ARM9_1_CP0_SEL                         ( BIT(1) )
772 #define BIT_PD_CP0_ARM9_0_CP0_SEL                         ( BIT(0) )
773
774 /* bits definitions for register REG_PMU_APB_CP1_PD_SHUTDOWN_CFG */
775 #define BIT_PD_CP1_COMWRAP_VCP1_SEL                       ( BIT(20) )
776 #define BIT_PD_CP1_CEVA_VCP1_SEL                          ( BIT(19) )
777 #define BIT_PD_CP1_LTE_P2_VCP1_SEL                        ( BIT(18) )
778 #define BIT_PD_CP1_LTE_P1_VCP1_SEL                        ( BIT(17) )
779 #define BIT_PD_CP1_CA5_VCP1_SEL                           ( BIT(16) )
780 #define BIT_PD_CP1_COMWRAP_CP1_SEL                        ( BIT(4) )
781 #define BIT_PD_CP1_CEVA_CP1_SEL                           ( BIT(3) )
782 #define BIT_PD_CP1_LTE_P2_CP1_SEL                         ( BIT(2) )
783 #define BIT_PD_CP1_LTE_P1_CP1_SEL                         ( BIT(1) )
784 #define BIT_PD_CP1_CA5_CP1_SEL                            ( BIT(0) )
785
786 /* bits definitions for register REG_PMU_APB_WAKEUP_LOCK_EN */
787 #define BIT_VCP1_SYS_WAKEUP_LOCK_EN                       ( BIT(26) )
788 #define BIT_VCP0_SYS_WAKEUP_LOCK_EN                       ( BIT(25) )
789 #define BIT_CP1_SYS_WAKEUP_LOCK_EN                        ( BIT(24) )
790 #define BIT_CP0_SYS_WAKEUP_LOCK_EN                        ( BIT(23) )
791 #define BIT_AP_SYS_WAKEUP_LOCK_EN                         ( BIT(22) )
792 #define BIT_PD_PUB_SYS_WAKEUP_LOCK_EN                     ( BIT(21) )
793 #define BIT_PD_CP1_COMWRAP_WAKEUP_LOCK_EN                 ( BIT(20) )
794 #define BIT_PD_CP1_CEVA_WAKEUP_LOCK_EN                    ( BIT(19) )
795 #define BIT_PD_CP1_LTE_P2_WAKEUP_LOCK_EN                  ( BIT(18) )
796 #define BIT_PD_CP1_LTE_P1_WAKEUP_LOCK_EN                  ( BIT(17) )
797 #define BIT_PD_CP1_CA5_WAKEUP_LOCK_EN                     ( BIT(16) )
798 #define BIT_PD_CP0_CEVA_1_WAKEUP_LOCK_EN                  ( BIT(15) )
799 #define BIT_PD_CP0_CEVA_0_WAKEUP_LOCK_EN                  ( BIT(14) )
800 #define BIT_PD_CP0_TD_WAKEUP_LOCK_EN                      ( BIT(13) )
801 #define BIT_PD_CP0_GSM_1_WAKEUP_LOCK_EN                   ( BIT(12) )
802 #define BIT_PD_CP0_GSM_0_WAKEUP_LOCK_EN                   ( BIT(11) )
803 #define BIT_PD_CP0_HU3GE_WAKEUP_LOCK_EN                   ( BIT(10) )
804 #define BIT_PD_CP0_ARM9_1_WAKEUP_LOCK_EN                  ( BIT(9) )
805 #define BIT_PD_CP0_ARM9_0_WAKEUP_LOCK_EN                  ( BIT(8) )
806 #define BIT_PD_MM_TOP_WAKEUP_LOCK_EN                      ( BIT(7) )
807 #define BIT_PD_GPU_TOP_WAKEUP_LOCK_EN                     ( BIT(6) )
808 #define BIT_PD_AP_SYS_WAKEUP_LOCK_EN                      ( BIT(5) )
809 #define BIT_PD_CA7_TOP_WAKEUP_LOCK_EN                     ( BIT(4) )
810 #define BIT_PD_CA7_C3_WAKEUP_LOCK_EN                      ( BIT(3) )
811 #define BIT_PD_CA7_C2_WAKEUP_LOCK_EN                      ( BIT(2) )
812 #define BIT_PD_CA7_C1_WAKEUP_LOCK_EN                      ( BIT(1) )
813 #define BIT_PD_CA7_C0_WAKEUP_LOCK_EN                      ( BIT(0) )
814
815 /* bits definitions for register REG_PMU_APB_PD_CODEC_TOP_CFG  */
816 #define BIT_PD_CODEC_TOP_FORCE_SHUTDOWN                   (BIT(25))
817 #define BIT_PD_CODEC_TOP_AUTO_SHUTDOWN_EN                 (BIT(24))
818 #define BITS_PD_CODEC_TOP_PWR_ON_DLY(_X_)                 ((_X_) & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)))
819 #define BITS_PD_CODEC_TOP_PWR_ON_SEQ_DLY(_X_)             ((_X_) & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)))
820 #define BITS_PD_CODEC_TOP_ISO_ON_DLY(_X_)                 ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)))
821
822 /* bits definitions for register REG_PMU_APB_PD_CA7_C0_SHUTDOWN_MARK_STATUS */
823 #define BITS_PD_CA7_C0_SHUTDOWN_MARK(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
824
825 /* bits definitions for register REG_PMU_APB_PD_CA7_C1_SHUTDOWN_MARK_STATUS */
826 #define BITS_PD_CA7_C1_SHUTDOWN_MARK(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
827
828 /* bits definitions for register REG_PMU_APB_PD_CA7_C2_SHUTDOWN_MARK_STATUS */
829 #define BITS_PD_CA7_C2_SHUTDOWN_MARK(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
830
831 /* bits definitions for register REG_PMU_APB_PD_CA7_C3_SHUTDOWN_MARK_STATUS */
832 #define BITS_PD_CA7_C3_SHUTDOWN_MARK(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
833
834 /* bits definitions for register REG_PMU_APB_PD_CA7_TOP_SHUTDOWN_MARK_STATUS */
835 #define BITS_PD_CA7_TOP_SHUTDOWN_MARK(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
836
837 /* bits definitions for register REG_PMU_APB_PD_AP_SYS_SHUTDOWN_MARK_STATUS */
838 #define BITS_PD_AP_SYS_SHUTDOWN_MARK(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
839
840 /* bits definitions for register REG_PMU_APB_PD_GPU_TOP_SHUTDOWN_MARK_STATUS */
841 #define BITS_PD_GPU_TOP_SHUTDOWN_MARK(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
842
843 /* bits definitions for register REG_PMU_APB_PD_MM_TOP_SHUTDOWN_MARK_STATUS */
844 #define BITS_PD_MM_TOP_SHUTDOWN_MARK(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
845
846 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_0_SHUTDOWN_MARK_STATUS */
847 #define BITS_PD_CP0_ARM9_0_SHUTDOWN_MARK(_X_)             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
848
849 /* bits definitions for register REG_PMU_APB_PD_CP0_ARM9_1_SHUTDOWN_MARK_STATUS */
850 #define BITS_PD_CP0_ARM9_1_SHUTDOWN_MARK(_X_)             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
851
852 /* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_0_SHUTDOWN_MARK_STATUS */
853 #define BITS_PD_CP0_CEVA_0_SHUTDOWN_MARK(_X_)             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
854
855 /* bits definitions for register REG_PMU_APB_PD_CP0_CEVA_1_SHUTDOWN_MARK_STATUS */
856 #define BITS_PD_CP0_CEVA_1_SHUTDOWN_MARK(_X_)             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
857
858 /* bits definitions for register REG_PMU_APB_PD_CP0_GSM_0_SHUTDOWN_MARK_STATUS */
859 #define BITS_PD_CP0_GSM_0_SHUTDOWN_MARK(_X_)              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
860
861 /* bits definitions for register REG_PMU_APB_PD_CP0_GSM_1_SHUTDOWN_MARK_STATUS */
862 #define BITS_PD_CP0_GSM_1_SHUTDOWN_MARK(_X_)              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
863
864 /* bits definitions for register REG_PMU_APB_PD_CP0_TD_SHUTDOWN_MARK_STATUS */
865 #define BITS_PD_CP0_TD_SHUTDOWN_MARK(_X_)                 ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
866
867 /* bits definitions for register REG_PMU_APB_PD_CP0_HU3GE_SHUTDOWN_MARK_STATUS */
868 #define BITS_PD_CP0_HU3GE_SHUTDOWN_MARK(_X_)              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
869
870 /* bits definitions for register REG_PMU_APB_PD_CP1_CA5_SHUTDOWN_MARK_STATUS */
871 #define BITS_PD_CP1_CA5_SHUTDOWN_MARK(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
872
873 /* bits definitions for register REG_PMU_APB_PD_CP1_CEVA_SHUTDOWN_MARK_STATUS */
874 #define BITS_PD_CP1_CEVA_SHUTDOWN_MARK(_X_)               ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
875
876 /* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P1_SHUTDOWN_MARK_STATUS */
877 #define BITS_PD_CP1_LTE_P1_SHUTDOWN_MARK(_X_)             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
878
879 /* bits definitions for register REG_PMU_APB_PD_CP1_LTE_P2_SHUTDOWN_MARK_STATUS */
880 #define BITS_PD_CP1_LTE_P2_SHUTDOWN_MARK(_X_)             ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
881
882 /* bits definitions for register REG_PMU_APB_PD_CP1_COMWRAP_SHUTDOWN_MARK_STATUS */
883 #define BITS_PD_CP1_COMWRAP_SHUTDOWN_MARK(_X_)            ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
884
885 /* bits definitions for register REG_PMU_APB_PD_PUB_SYS_SHUTDOWN_MARK_STATUS */
886 #define BITS_PD_PUB_SYS_SHUTDOWN_MARK(_X_)                ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
887
888 #if defined(CONFIG_MACH_SP9830I)
889 /* bits definitions for register REG_PMU_APB_PD_CODEC_TOP_SHUTDOWN_MARK_STATUS  */
890 #define BITS_PD_CODEC_TOP_SHUTDOWN_MARK(_X_)              ((_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)))
891 #endif
892
893 #endif