include/soc/sprd/chip_x35l/__regs_arm7_ahb_rf.h

   1 /*
   2  * Copyright (C) 2014 Spreadtrum Communications Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  *************************************************
  15  * Automatically generated C header: do not edit *
  16  *************************************************
  17  */
  18
  19 #ifndef __SCI_GLB_REGS_H__
  20 #error  "Don't include this file directly, Pls include sci_glb_regs.h"
  21 #endif
  22
  23
  24 #ifndef __H_REGS_ARM7_AHB_RF_HEADFILE_H__
  25 #define __H_REGS_ARM7_AHB_RF_HEADFILE_H__ __FILE__
  26
  27 #define REGS_ARM7_AHB_RF
  28
  29 /* registers definitions for ARM7_AHB_RF */
  30 #define REG_ARM7_AHB_RF_ARM7_EB                           SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0000)
  31 #define REG_ARM7_AHB_RF_ARM7_SOFT_RST                     SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0004)
  32 #define REG_ARM7_AHB_RF_AHB_PAUSE                         SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x0008)
  33 #define REG_ARM7_AHB_RF_ARM7_SLP_CTL                      SCI_ADDR(REGS_ARM7_AHB_RF_BASE, 0x000C)
  34
  35
  36
  37 /* bits definitions for register REG_ARM7_AHB_RF_ARM7_EB */
  38 #define BIT_ARM7_GPIO_EB                                  ( BIT(10) )
  39 #define BIT_ARM7_UART_EB                                  ( BIT(9) )
  40 #define BIT_ARM7_TMR_EB                                   ( BIT(8) )
  41 #define BIT_ARM7_SYST_EB                                  ( BIT(7) )
  42 #define BIT_ARM7_WDG_EB                                   ( BIT(6) )
  43 #define BIT_ARM7_EIC_EB                                   ( BIT(5) )
  44 #define BIT_ARM7_INTC_EB                                  ( BIT(4) )
  45 #define BIT_ARM7_IMC_EB                                   ( BIT(2) )
  46 #define BIT_ARM7_TIC_EB                                   ( BIT(1) )
  47 #define BIT_ARM7_DMA_EB                                   ( BIT(0) )
  48
  49 /* bits definitions for register REG_ARM7_AHB_RF_ARM7_SOFT_RST */
  50 #define BIT_ARM7_GPIO_SOFT_RST                            ( BIT(10) )
  51 #define BIT_ARM7_UART_SOFT_RST                            ( BIT(9) )
  52 #define BIT_ARM7_TMR_SOFT_RST                             ( BIT(8) )
  53 #define BIT_ARM7_SYST_SOFT_RST                            ( BIT(7) )
  54 #define BIT_ARM7_WDG_SOFT_RST                             ( BIT(6) )
  55 #define BIT_ARM7_EIC_SOFT_RST                             ( BIT(5) )
  56 #define BIT_ARM7_INTC_SOFT_RST                            ( BIT(4) )
  57 #define BIT_ARM7_IMC_SOFT_RST                             ( BIT(2) )
  58 #define BIT_ARM7_TIC_SOFT_RST                             ( BIT(1) )
  59 #define BIT_ARM7_ARCH_SOFT_RST                            ( BIT(0) )
  60
  61 /* bits definitions for register REG_ARM7_AHB_RF_AHB_PAUSE */
  62 #define BIT_ARM7_DEEP_SLEEP_EN                            ( BIT(2) )
  63 #define BIT_ARM7_SYS_SLEEP_EN                             ( BIT(1) )
  64 #define BIT_ARM7_CORE_SLEEP                               ( BIT(0) )
  65
  66 /* bits definitions for register REG_ARM7_AHB_RF_ARM7_SLP_CTL */
  67 #define BIT_ARM7_SYS_AUTO_GATE_EN                         ( BIT(2) )
  68 #define BIT_ARM7_AHB_AUTO_GATE_EN                         ( BIT(1) )
  69 #define BIT_ARM7_CORE_AUTO_GATE_EN                        ( BIT(0) )
  70
  71 #endif