2 * Copyright (C) 2014 Spreadtrum Communications Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 *************************************************
15 * Automatically generated C header: do not edit *
16 *************************************************
19 #ifndef __SCI_GLB_REGS_H__
20 #error "Don't include this file directly, Pls include sci_glb_regs.h"
24 #ifndef __H_REGS_AON_APB_HEADFILE_H__
25 #define __H_REGS_AON_APB_HEADFILE_H__ __FILE__
29 /* registers definitions for AON_APB_ */
30 #define REG_AON_APB_APB_EB0 SCI_ADDR(REGS_AON_APB_BASE, 0x0000)
31 #define REG_AON_APB_APB_EB1 SCI_ADDR(REGS_AON_APB_BASE, 0x0004)
32 #define REG_AON_APB_APB_RST0 SCI_ADDR(REGS_AON_APB_BASE, 0x0008)
33 #define REG_AON_APB_APB_RST1 SCI_ADDR(REGS_AON_APB_BASE, 0x000C)
34 #define REG_AON_APB_APB_RTC_EB SCI_ADDR(REGS_AON_APB_BASE, 0x0010)
35 #define REG_AON_APB_REC_26MHZ_BUF_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0014)
36 #define REG_AON_APB_SINDRV_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0018)
37 #define REG_AON_APB_ADA_SEL_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x001C)
38 #define REG_AON_APB_VBC_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0020)
39 #define REG_AON_APB_PWR_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0024)
40 #define REG_AON_APB_TS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0028)
41 #define REG_AON_APB_BOOT_MODE SCI_ADDR(REGS_AON_APB_BASE, 0x002C)
42 #define REG_AON_APB_BB_BG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0030)
43 #define REG_AON_APB_CP_ARM_JTAG_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x0034)
44 #define REG_AON_APB_PLL_SOFT_CNT_DONE SCI_ADDR(REGS_AON_APB_BASE, 0x0038)
45 #define REG_AON_APB_DCXO_LC_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x003C)
46 #define REG_AON_APB_DCXO_LC_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0040)
47 #define REG_AON_APB_MPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0044)
48 #define REG_AON_APB_MPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0048)
49 #define REG_AON_APB_DPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x004C)
50 #define REG_AON_APB_DPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0050)
51 #define REG_AON_APB_TWPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0054)
52 #define REG_AON_APB_TWPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0058)
53 #define REG_AON_APB_LTEPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x005C)
54 #define REG_AON_APB_LTEPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0060)
55 #define REG_AON_APB_LVDSDISPLL_CFG1 SCI_ADDR(REGS_AON_APB_BASE, 0x0064)
56 #define REG_AON_APB_LVDSDISPLL_CFG2 SCI_ADDR(REGS_AON_APB_BASE, 0x0068)
57 #define REG_AON_APB_AON_REG_PROT SCI_ADDR(REGS_AON_APB_BASE, 0x006C)/*Big endian protect register*/
58 #define REG_AON_APB_LDSP_BOOT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0070)/*DSP boot enable*/
59 #define REG_AON_APB_LDSP_BOOT_VEC SCI_ADDR(REGS_AON_APB_BASE, 0x0074)/*DSP boot vector*/
60 #define REG_AON_APB_LDSP_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0078)/*DSP reset*/
61 #define REG_AON_APB_LDSP_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x007C)
62 #define REG_AON_APB_LDSP_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0080)
63 #define REG_AON_APB_LDSP_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0084)
64 #define REG_AON_APB_AON_CGM_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0088)
65 #define REG_AON_APB_LACC_MTX_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x008C)
66 #define REG_AON_APB_CORTEX_MTX_CTRL1 SCI_ADDR(REGS_AON_APB_BASE, 0x0090)
67 #define REG_AON_APB_CORTEX_MTX_CTRL2 SCI_ADDR(REGS_AON_APB_BASE, 0x0094)
68 #define REG_AON_APB_CORTEX_MTX_CTRL3 SCI_ADDR(REGS_AON_APB_BASE, 0x0098)/*DSP reset*/
69 #define REG_AON_APB_CA5_TCLK_DLY_LEN SCI_ADDR(REGS_AON_APB_BASE, 0x009C)/*APB clock control*/
70 #define REG_AON_APB_CCIR_RCVR_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0100)/*APB clock control*/
71 #define REG_AON_APB_AON_CHIP_ID_H SCI_ADDR(REGS_AON_APB_BASE, 0x00F8)
72 #define REG_AON_APB_AON_CHIP_ID SCI_ADDR(REGS_AON_APB_BASE, 0x00FC)
73 #define REG_AON_APB_AON_CHIP_ID_L REG_AON_APB_AON_CHIP_ID
74 #define REG_AON_APB_PLL_BG_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0108)
75 #define REG_AON_APB_LVDSDIS_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x010C)
76 #define REG_AON_APB_DJTAG_MUX_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x0110)
77 #define REG_AON_APB_ARM7_SYS_SOFT_RST SCI_ADDR(REGS_AON_APB_BASE, 0x0114)
78 #define REG_AON_APB_CP1_CP0_ADDR_MSB SCI_ADDR(REGS_AON_APB_BASE, 0x0118)
79 #define REG_AON_APB_AON_DMA_INT_EN SCI_ADDR(REGS_AON_APB_BASE, 0x011C)
80 #define REG_AON_APB_EMC_AUTO_GATE_EN SCI_ADDR(REGS_AON_APB_BASE, 0x0120)
81 #define REG_AON_APB_ARM7_CFG_BUS SCI_ADDR(REGS_AON_APB_BASE, 0x0124)
82 #define REG_AON_APB_RTC4M_0_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x0128)
83 #define REG_AON_APB_RTC4M_1_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x012C)
84 #define REG_AON_APB_APB_RST2 SCI_ADDR(REGS_AON_APB_BASE, 0x0130)
85 #define REG_AON_APB_AP_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3004)
86 #define REG_AON_APB_CP0_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x3008)
87 #define REG_AON_APB_CP1_WPROT_EN1 SCI_ADDR(REGS_AON_APB_BASE, 0x300C)
88 #define REG_AON_APB_IO_DLY_CTRL SCI_ADDR(REGS_AON_APB_BASE, 0x3014)
89 #define REG_AON_APB_AP_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3018)
90 #define REG_AON_APB_CP0_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3020)
91 #define REG_AON_APB_CP1_WPROT_EN0 SCI_ADDR(REGS_AON_APB_BASE, 0x3024)
92 #define REG_AON_APB_PMU_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x302C)
93 #define REG_AON_APB_THM_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3030)
94 #define REG_AON_APB_AP_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3034)
95 #define REG_AON_APB_CA7_RST_MONITOR SCI_ADDR(REGS_AON_APB_BASE, 0x3038)
96 #define REG_AON_APB_BOND_OPT0 SCI_ADDR(REGS_AON_APB_BASE, 0x303C)
97 #define REG_AON_APB_BOND_OPT1 SCI_ADDR(REGS_AON_APB_BASE, 0x3040)
98 #define REG_AON_APB_RES_REG0 SCI_ADDR(REGS_AON_APB_BASE, 0x3044)
99 #define REG_AON_APB_RES_REG1 SCI_ADDR(REGS_AON_APB_BASE, 0x3048)
100 #define REG_AON_APB_AON_QOS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x304C)
101 #define REG_AON_APB_BB_LDO_CAL_START SCI_ADDR(REGS_AON_APB_BASE, 0x3050)
102 #define REG_AON_APB_AON_MTX_PROT_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3058)
103 #define REG_AON_APB_LVDS_CFG SCI_ADDR(REGS_AON_APB_BASE, 0x3060)
104 #define REG_AON_APB_PLL_LOCK_OUT_SEL SCI_ADDR(REGS_AON_APB_BASE, 0x3064)
105 #define REG_AON_APB_RTC4M_RC_VAL SCI_ADDR(REGS_AON_APB_BASE, 0x3068)
106 #define REG_AON_APB_AON_APB_RSV SCI_ADDR(REGS_AON_APB_BASE, 0x30F0)
108 /* bits definitions for register REG_AON_APB_APB_EB0 */
109 #define BIT_I2C_EB ( BIT(31) )
110 #define BIT_CA7_DAP_EB ( BIT(30) )
111 #define BIT_CA7_TS1_EB ( BIT(29) )
112 #define BIT_CA7_TS0_EB ( BIT(28) )
113 #define BIT_GPU_EB ( BIT(27) )
114 #define BIT_AON_CKG_EB ( BIT(26) )
115 #define BIT_MM_EB ( BIT(25) )
116 #define BIT_AP_WDG_EB ( BIT(24) )
117 #define BIT_MSPI_EB ( BIT(23) )
118 #define BIT_SPLK_EB ( BIT(22) )
119 #define BIT_IPI_EB ( BIT(21) )
120 #define BIT_PIN_EB ( BIT(20) )
121 #define BIT_VBC_EB ( BIT(19) )
122 #define BIT_AUD_EB ( BIT(18) )
123 #define BIT_AUDIF_EB ( BIT(17) )
124 #define BIT_ADI_EB ( BIT(16) )
125 #define BIT_INTC_EB ( BIT(15) )
126 #define BIT_EIC_EB ( BIT(14) )
127 #define BIT_EFUSE_EB ( BIT(13) )
128 #define BIT_AP_TMR0_EB ( BIT(12) )
129 #define BIT_AON_TMR_EB ( BIT(11) )
130 #define BIT_AP_SYST_EB ( BIT(10) )
131 #define BIT_AON_SYST_EB ( BIT(9) )
132 #define BIT_KPD_EB ( BIT(8) )
133 #define BIT_PWM3_EB ( BIT(7) )
134 #define BIT_PWM2_EB ( BIT(6) )
135 #define BIT_PWM1_EB ( BIT(5) )
136 #define BIT_PWM0_EB ( BIT(4) )
137 #define BIT_GPIO_EB ( BIT(3) )
138 #define BIT_TPC_EB ( BIT(2) )
139 #define BIT_FM_EB ( BIT(1) )
140 #define BIT_ADC_EB ( BIT(0) )
142 /* bits definitions for register REG_AON_APB_APB_EB1 */
143 #if defined(CONFIG_MACH_SP9830I)
144 #define BIT_CODEC_EB (BIT(28))
146 #define BIT_ORP_JTAG_EB ( BIT(27) )
147 #define BIT_CA5_TS0_EB ( BIT(26) )
148 #define BIT_DEF_EB ( BIT(25) )
149 #define BIT_LVDS_PLL_DIV_EN ( BIT(24) )
150 #define BIT_ARM7_JTAG_EB ( BIT(23) )
151 #define BIT_AON_DMA_EB ( BIT(22) )
152 #define BIT_MBOX_EB ( BIT(21) )
153 #define BIT_DJTAG_EB ( BIT(20) )
154 #define BIT_RTC4M1_CAL_EB ( BIT(19) )
155 #define BIT_RTC4M0_CAL_EB ( BIT(18) )
156 #define BIT_MDAR_EB ( BIT(17) )
157 #define BIT_LVDS_TCXO_EB ( BIT(16) )
158 #define BIT_LVDS_TRX_EB ( BIT(15) )
159 #define BIT_CA5_DAP_EB ( BIT(14) )
160 #define BIT_GSP_EMC_EB ( BIT(13) )
161 #define BIT_ZIP_EMC_EB ( BIT(12) )
162 #define BIT_DISP_EMC_EB ( BIT(11) )
163 #define BIT_AP_TMR2_EB ( BIT(10) )
164 #define BIT_AP_TMR1_EB ( BIT(9) )
165 #define BIT_CA7_WDG_EB ( BIT(8) )
166 #define BIT_AVS_EB ( BIT(6) )
167 #define BIT_PROBE_EB ( BIT(5) )
168 #define BIT_AUX2_EB ( BIT(4) )
169 #define BIT_AUX1_EB ( BIT(3) )
170 #define BIT_AUX0_EB ( BIT(2) )
171 #define BIT_THM_EB ( BIT(1) )
172 #define BIT_PMU_EB ( BIT(0) )
174 /* bits definitions for register REG_AON_APB_APB_RST0 */
175 #define BIT_CA5_TS0_SOFT_RST ( BIT(31) )
176 #define BIT_I2C_SOFT_RST ( BIT(30) )
177 #define BIT_CA7_TS1_SOFT_RST ( BIT(29) )
178 #define BIT_CA7_TS0_SOFT_RST ( BIT(28) )
179 #define BIT_DAP_MTX_SOFT_RST ( BIT(27) )
180 #define BIT_MSPI1_SOFT_RST ( BIT(26) )
181 #define BIT_MSPI0_SOFT_RST ( BIT(25) )
182 #define BIT_SPLK_SOFT_RST ( BIT(24) )
183 #define BIT_IPI_SOFT_RST ( BIT(23) )
184 #define BIT_AON_CKG_SOFT_RST ( BIT(22) )
185 #define BIT_PIN_SOFT_RST ( BIT(21) )
186 #define BIT_VBC_SOFT_RST ( BIT(20) )
187 #define BIT_AUD_SOFT_RST ( BIT(19) )
188 #define BIT_AUDIF_SOFT_RST ( BIT(18) )
189 #define BIT_ADI_SOFT_RST ( BIT(17) )
190 #define BIT_INTC_SOFT_RST ( BIT(16) )
191 #define BIT_EIC_SOFT_RST ( BIT(15) )
192 #define BIT_EFUSE_SOFT_RST ( BIT(14) )
193 #define BIT_AP_WDG_SOFT_RST ( BIT(13) )
194 #define BIT_AP_TMR0_SOFT_RST ( BIT(12) )
195 #define BIT_AON_TMR_SOFT_RST ( BIT(11) )
196 #define BIT_AP_SYST_SOFT_RST ( BIT(10) )
197 #define BIT_AON_SYST_SOFT_RST ( BIT(9) )
198 #define BIT_KPD_SOFT_RST ( BIT(8) )
199 #define BIT_PWM3_SOFT_RST ( BIT(7) )
200 #define BIT_PWM2_SOFT_RST ( BIT(6) )
201 #define BIT_PWM1_SOFT_RST ( BIT(5) )
202 #define BIT_PWM0_SOFT_RST ( BIT(4) )
203 #define BIT_GPIO_SOFT_RST ( BIT(3) )
204 #define BIT_TPC_SOFT_RST ( BIT(2) )
205 #define BIT_FM_SOFT_RST ( BIT(1) )
206 #define BIT_ADC_SOFT_RST ( BIT(0) )
208 /* bits definitions for register REG_AON_APB_APB_RST1 */
209 #define BIT_RTC4M_ANA_SOFT_RST ( BIT(31) )
210 #define BIT_DEF_SLV_INT_SOFT_CLR ( BIT(30) )
211 #define BIT_DEF_SOFT_RST ( BIT(29) )
212 #define BIT_ADC3_SOFT_RST ( BIT(28) )
213 #define BIT_ADC2_SOFT_RST ( BIT(27) )
214 #define BIT_ADC1_SOFT_RST ( BIT(26) )
215 #define BIT_MBOX_SOFT_RST ( BIT(25) )
216 #define BIT_RTC4M1_CAL_SOFT_RST ( BIT(23) )
217 #define BIT_RTC4M0_CAL_SOFT_RST ( BIT(22) )
218 #define BIT_LDSP_SYS_SOFT_RST ( BIT(21) )
219 #define BIT_LCP_SYS_SOFT_RST ( BIT(20) )
220 #define BIT_DAC3_SOFT_RST ( BIT(19) )
221 #define BIT_DAC2_SOFT_RST ( BIT(18) )
222 #define BIT_DAC1_SOFT_RST ( BIT(17) )
223 #define BIT_ADC3_CAL_SOFT_RST ( BIT(16) )
224 #define BIT_ADC2_CAL_SOFT_RST ( BIT(15) )
225 #define BIT_ADC1_CAL_SOFT_RST ( BIT(14) )
226 #define BIT_MDAR_SOFT_RST ( BIT(13) )
227 #define BIT_LVDSDIS_SOFT_RST ( BIT(12) )
228 #define BIT_BB_CAL_SOFT_RST ( BIT(11) )
229 #define BIT_DCXO_LC_SOFT_RST ( BIT(10) )
230 #define BIT_AP_TMR2_SOFT_RST ( BIT(9) )
231 #define BIT_AP_TMR1_SOFT_RST ( BIT(8) )
232 #define BIT_CA7_WDG_SOFT_RST ( BIT(7) )
233 #define BIT_AON_DMA_SOFT_RST ( BIT(6) )
234 #define BIT_AVS_SOFT_RST ( BIT(5) )
235 #define BIT_DMC_PHY_SOFT_RST ( BIT(4) )
236 #define BIT_GPU_THMA_SOFT_RST ( BIT(3) )
237 #define BIT_ARM_THMA_SOFT_RST ( BIT(2) )
238 #define BIT_THM_SOFT_RST ( BIT(1) )
239 #define BIT_PMU_SOFT_RST ( BIT(0) )
241 /* bits definitions for register REG_AON_APB_APB_RTC_EB */
242 #define BIT_CP0_LTE_EB ( BIT(19) )
243 #define BIT_BB_CAL_RTC_EB ( BIT(18) )
244 #define BIT_DCXO_LC_RTC_EB ( BIT(17) )
245 #define BIT_AP_TMR2_RTC_EB ( BIT(16) )
246 #define BIT_AP_TMR1_RTC_EB ( BIT(15) )
247 #define BIT_GPU_THMA_RTC_AUTO_EN ( BIT(14) )
248 #define BIT_ARM_THMA_RTC_AUTO_EN ( BIT(13) )
249 #define BIT_GPU_THMA_RTC_EB ( BIT(12) )
250 #define BIT_ARM_THMA_RTC_EB ( BIT(11) )
251 #define BIT_THM_RTC_EB ( BIT(10) )
252 #define BIT_CA7_WDG_RTC_EB ( BIT(9) )
253 #define BIT_AP_WDG_RTC_EB ( BIT(8) )
254 #define BIT_EIC_RTCDV5_EB ( BIT(7) )
255 #define BIT_EIC_RTC_EB ( BIT(6) )
256 #define BIT_AP_TMR0_RTC_EB ( BIT(5) )
257 #define BIT_AON_TMR_RTC_EB ( BIT(4) )
258 #define BIT_AP_SYST_RTC_EB ( BIT(3) )
259 #define BIT_AON_SYST_RTC_EB ( BIT(2) )
260 #define BIT_KPD_RTC_EB ( BIT(1) )
261 #define BIT_ARCH_RTC_EB ( BIT(0) )
263 /* bits definitions for register REG_AON_APB_REC_26MHZ_BUF_CFG */
264 #define BITS_PLL_PROBE_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
265 #define BIT_REC_26MHZ_1_CUR_SEL ( BIT(4) )
266 #define BIT_REC_26MHZ_0_CUR_SEL ( BIT(0) )
268 /* bits definitions for register REG_AON_APB_SINDRV_CTRL */
269 #define BITS_SINDRV_LVL(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)) )
270 #define BIT_SINDRV_CLIP_MODE ( BIT(2) )
271 #define BIT_SINDRV_ENA_SQUARE ( BIT(1) )
272 #define BIT_SINDRV_ENA ( BIT(0) )
274 /* bits definitions for register REG_AON_APB_ADA_SEL_CTRL */
275 #define BIT_TW_MODE_SEL ( BIT(3) )
276 #define BIT_WGADC_DIV_EN ( BIT(2) )
277 #define BIT_AFCDAC_SYS_SEL ( BIT(1) )
278 #define BIT_APCDAC_SYS_SEL ( BIT(0) )
280 /* bits definitions for register REG_AON_APB_VBC_CTRL */
281 #define BIT_AUDIF_CKG_AUTO_EN ( BIT(20) )
282 #define BITS_AUD_INT_SYS_SEL(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
283 #define BITS_VBC_AFIFO_INT_SYS_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
284 #define BITS_VBC_AD23_INT_SYS_SEL(_X_) ( (_X_) << 14 & (BIT(14)|BIT(15)) )
285 #define BITS_VBC_AD01_INT_SYS_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
286 #define BITS_VBC_DA01_INT_SYS_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
287 #define BITS_VBC_AD23_DMA_SYS_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
288 #define BITS_VBC_AD01_DMA_SYS_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
289 #define BITS_VBC_DA01_DMA_SYS_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
290 #define BIT_VBC_INT_CP0_ARM_SEL ( BIT(3) )
291 #define BIT_VBC_INT_CP1_ARM_SEL ( BIT(2) )
292 #define BIT_VBC_DMA_CP0_ARM_SEL ( BIT(1) )
293 #define BIT_VBC_DMA_CP1_ARM_SEL ( BIT(0) )
295 /* bits definitions for register REG_AON_APB_PWR_CTRL */
296 #define BIT_HSIC_PLL_EN ( BIT(19) )
297 #define BIT_HSIC_PHY_PD ( BIT(18) )
298 #define BIT_HSIC_PS_PD_S ( BIT(17) )
299 #define BIT_HSIC_PS_PD_L ( BIT(16) )
300 #define BIT_MIPI_DSI_PS_PD_S ( BIT(15) )
301 #define BIT_MIPI_DSI_PS_PD_L ( BIT(14) )
302 #define BIT_MIPI_CSI_4LANE_PS_PD_S ( BIT(13) )
303 #define BIT_MIPI_CSI_4LANE_PS_PD_L ( BIT(12) )
304 #define BIT_MIPI_CSI_2LANE_PS_PD_S ( BIT(11) )
305 #define BIT_MIPI_CSI_2LANE_PS_PD_L ( BIT(10) )
306 #define BIT_CA7_TS1_STOP ( BIT(9) )
307 #define BIT_CA7_TS0_STOP ( BIT(8) )
308 #define BIT_EFUSE_BIST_PWR_ON ( BIT(3) )
309 #define BIT_FORCE_DSI_PHY_SHUTDOWNZ ( BIT(2) )
310 #define BIT_FORCE_CSI_PHY_SHUTDOWNZ ( BIT(1) )
311 #define BIT_USB_PHY_PD ( BIT(0) )
313 #define BIT_CSI1_PHY_PD ( BIT(11) )
314 #define BIT_CSI0_PHY_PD ( BIT(10) )
316 /* bits definitions for register REG_AON_APB_TS_CFG */
317 #define BIT_CSYSACK_TS_LP_2 ( BIT(13) )
318 #define BIT_CSYSREQ_TS_LP_2 ( BIT(12) )
319 #define BIT_CSYSACK_TS_LP_1 ( BIT(11) )
320 #define BIT_CSYSREQ_TS_LP_1 ( BIT(10) )
321 #define BIT_CSYSACK_TS_LP_0 ( BIT(9) )
322 #define BIT_CSYSREQ_TS_LP_0 ( BIT(8) )
323 #define BIT_EVENTACK_RESTARTREQ_TS01 ( BIT(4) )
324 #define BIT_EVENT_RESTARTREQ_TS01 ( BIT(1) )
325 #define BIT_EVENT_HALTREQ_TS01 ( BIT(0) )
327 /* bits definitions for register REG_AON_APB_BOOT_MODE */
328 #define BIT_ARM_JTAG_EN ( BIT(13) )
329 #define BIT_WPLL_OVR_FREQ_SEL ( BIT(12) )
330 #define BIT_PTEST_FUNC_ATSPEED_SEL ( BIT(8) )
331 #define BIT_PTEST_FUNC_MODE ( BIT(7) )
332 #define BIT_USB_DLOAD_EN ( BIT(4) )
333 #define BIT_ARM_BOOT_MD3 ( BIT(3) )
334 #define BIT_ARM_BOOT_MD2 ( BIT(2) )
335 #define BIT_ARM_BOOT_MD1 ( BIT(1) )
336 #define BIT_ARM_BOOT_MD0 ( BIT(0) )
338 /* bits definitions for register REG_AON_APB_BB_BG_CTRL */
339 #define BIT_BB_CON_BG ( BIT(22) )
340 #define BITS_BB_BG_RSV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)) )
341 #define BITS_BB_LDO_V(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
342 #define BIT_BB_BG_RBIAS_EN ( BIT(15) )
343 #define BIT_BB_BG_IEXT_IB_EN ( BIT(14) )
344 #define BITS_BB_LDO_REFCTRL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
345 #define BIT_BB_LDO_AUTO_PD_EN ( BIT(11) )
346 #define BIT_BB_LDO_SLP_PD_EN ( BIT(10) )
347 #define BIT_BB_LDO_FORCE_ON ( BIT(9) )
348 #define BIT_BB_LDO_FORCE_PD ( BIT(8) )
349 #define BIT_BB_BG_AUTO_PD_EN ( BIT(3) )
350 #define BIT_BB_BG_SLP_PD_EN ( BIT(2) )
351 #define BIT_BB_BG_FORCE_ON ( BIT(1) )
352 #define BIT_BB_BG_FORCE_PD ( BIT(0) )
354 /* bits definitions for register REG_AON_APB_CP_ARM_JTAG_CTRL */
355 #define BITS_CP_ARM_JTAG_PIN_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
357 /* bits definitions for register REG_AON_APB_PLL_SOFT_CNT_DONE */
358 #define BIT_RC1_SOFT_CNT_DONE ( BIT(13) )
359 #define BIT_RC0_SOFT_CNT_DONE ( BIT(12) )
360 #define BIT_XTLBUF1_SOFT_CNT_DONE ( BIT(9) )
361 #define BIT_XTLBUF0_SOFT_CNT_DONE ( BIT(8) )
362 #define BIT_LVDSPLL_SOFT_CNT_DONE ( BIT(4) )
363 #define BIT_LPLL_SOFT_CNT_DONE ( BIT(3) )
364 #define BIT_TWPLL_SOFT_CNT_DONE ( BIT(2) )
365 #define BIT_DPLL_SOFT_CNT_DONE ( BIT(1) )
366 #define BIT_MPLL_SOFT_CNT_DONE ( BIT(0) )
368 /* bits definitions for register REG_AON_APB_DCXO_LC_REG0 */
369 #define BIT_DCXO_LC_FLAG ( BIT(8) )
370 #define BIT_DCXO_LC_FLAG_CLR ( BIT(1) )
371 #define BIT_DCXO_LC_CNT_CLR ( BIT(0) )
373 /* bits definitions for register REG_AON_APB_DCXO_LC_REG1 */
374 #define BITS_DCXO_LC_CNT(_X_) (_X_)
376 /* bits definitions for register REG_AON_APB_MPLL_CFG1 */
377 #define BITS_MPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
378 #define BIT_MPLL_LOCK_DONE ( BIT(27) )
379 #define BIT_MPLL_DIV_S ( BIT(26) )
380 #define BIT_MPLL_MOD_EN ( BIT(25) )
381 #define BIT_MPLL_SDM_EN ( BIT(24) )
382 #define BITS_MPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
383 #define BITS_MPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
384 #define BITS_MPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
385 #define BITS_MPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
387 /* bits definitions for register REG_AON_APB_MPLL_CFG2 */
388 #define BITS_MPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
389 #define BITS_MPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
391 /* bits definitions for register REG_AON_APB_DPLL_CFG1 */
392 #define BITS_DPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
393 #define BIT_DPLL_LOCK_DONE ( BIT(27) )
394 #define BIT_DPLL_DIV_S ( BIT(26) )
395 #define BIT_DPLL_MOD_EN ( BIT(25) )
396 #define BIT_DPLL_SDM_EN ( BIT(24) )
397 #define BITS_DPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
398 #define BITS_DPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
399 #define BITS_DPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
400 #define BITS_DPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
402 /* bits definitions for register REG_AON_APB_DPLL_CFG2 */
403 #define BITS_DPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
404 #define BITS_DPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
406 /* bits definitions for register REG_AON_APB_TWPLL_CFG1 */
407 #define BITS_TWPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
408 #define BIT_TWPLL_LOCK_DONE ( BIT(27) )
409 #define BIT_TWPLL_DIV_S ( BIT(26) )
410 #define BIT_TWPLL_MOD_EN ( BIT(25) )
411 #define BIT_TWPLL_SDM_EN ( BIT(24) )
412 #define BITS_TWPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
413 #define BITS_TWPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
414 #define BITS_TWPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
415 #define BITS_TWPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
417 /* bits definitions for register REG_AON_APB_TWPLL_CFG2 */
418 #define BITS_TWPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
419 #define BITS_TWPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
421 /* bits definitions for register REG_AON_APB_LTEPLL_CFG1 */
422 #define BITS_LTEPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)) )
423 #define BIT_LTEPLL_LOCK_DONE ( BIT(27) )
424 #define BIT_LTEPLL_DIV_S ( BIT(26) )
425 #define BIT_LTEPLL_MOD_EN ( BIT(25) )
426 #define BIT_LTEPLL_SDM_EN ( BIT(24) )
427 #define BITS_LTEPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
428 #define BITS_LTEPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
429 #define BITS_LTEPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
430 #define BITS_LTEPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
432 /* bits definitions for register REG_AON_APB_LTEPLL_CFG2 */
433 #define BITS_LTEPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
434 #define BITS_LTEPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
436 /* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG1 */
437 #define BITS_LVDSDISPLL_RES(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
438 #define BIT_LVDSDISPLL_LOCK_DONE ( BIT(27) )
439 #define BIT_LVDSDISPLL_DIV_S ( BIT(26) )
440 #define BIT_LVDSDISPLL_MOD_EN ( BIT(25) )
441 #define BIT_LVDSDISPLL_SDM_EN ( BIT(24) )
442 #define BITS_LVDSDISPLL_LPF(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)) )
443 #define BITS_LVDSDISPLL_REFIN(_X_) ( (_X_) << 18 & (BIT(18)|BIT(19)) )
444 #define BITS_LVDSDISPLL_IBIAS(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)) )
445 #define BITS_LVDSDISPLL_N(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)) )
447 /* bits definitions for register REG_AON_APB_LVDSDISPLL_CFG2 */
448 #define BITS_LVDSDISPLL_NINT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
449 #define BITS_LVDSDISPLL_KINT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
451 /* bits definitions for register REG_AON_APB_AON_REG_PROT */
452 #define BIT_LDSP_CTRL_PROT ( BIT(31) )
453 #define BITS_REG_PROT_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
455 /* bits definitions for register REG_AON_APB_LDSP_BOOT_EN */
456 #define BIT_FRC_CLK_LDSP_EN ( BIT(1) )
457 #define BIT_LDSP_BOOT_EN ( BIT(0) )
459 /* bits definitions for register REG_AON_APB_LDSP_BOOT_VEC */
460 #define BITS_LDSP_BOOT_VECTOR(_X_) (_X_)
462 /* bits definitions for register REG_AON_APB_LDSP_RST */
463 #define BIT_LDSP_SYS_SRST ( BIT(1) )
464 #define BIT_LDSP_CORE_SRST_N ( BIT(0) )
466 /* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL1 */
467 #define BITS_LDSP_MTX_CTRL1(_X_) (_X_)
469 /* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL2 */
470 #define BITS_LDSP_MTX_CTRL2(_X_) (_X_)
472 /* bits definitions for register REG_AON_APB_LDSP_MTX_CTRL3 */
473 #define BITS_LDSP_MTX_CTRL3(_X_) (_X_)
475 /* bits definitions for register REG_AON_APB_AON_CGM_CFG */
476 #define BITS_PROBE_CKG_DIV(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
477 #define BITS_AUX2_CKG_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
478 #define BITS_AUX1_CKG_DIV(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
479 #define BITS_AUX0_CKG_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
480 #define BITS_PROBE_CKG_SEL(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
481 #define BITS_AUX2_CKG_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
482 #define BITS_AUX1_CKG_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
483 #define BITS_AUX0_CKG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
485 /* bits definitions for register REG_AON_APB_LACC_MTX_CTRL */
486 #define BITS_LACC_MTX_CTRL(_X_) (_X_)
488 /* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL1 */
489 #define BITS_CORTEX_MTX_CTRL1(_X_) (_X_)
491 /* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL2 */
492 #define BITS_CORTEX_MTX_CTRL2(_X_) (_X_)
494 /* bits definitions for register REG_AON_APB_CORTEX_MTX_CTRL3 */
495 #define BITS_CORTEX_MTX_CTRL3(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
497 /* bits definitions for register REG_AON_APB_CA5_TCLK_DLY_LEN */
498 #define BITS_CA5_TCLK_DLY_LEN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
500 /* bits definitions for register REG_AON_APB_CCIR_RCVR_CFG */
501 #define BITS_ANALOG_PLL_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
502 #define BITS_ANALOG_TESTMUX(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
503 #define BIT_CCIR_SE ( BIT(1) )
504 #define BIT_CCIR_IE ( BIT(0) )
506 /* bits definitions for register REG_AON_APB_PLL_BG_CFG */
507 #define BITS_PLL_BG_RSV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
508 #define BIT_PLL_BG_RBIAS_EN ( BIT(3) )
509 #define BIT_PLL_BG_PD ( BIT(2) )
510 #define BIT_PLL_BG_IEXT_IBEN ( BIT(1) )
511 #define BIT_PLL_CON_BG ( BIT(0) )
513 /* bits definitions for register REG_AON_APB_LVDSDIS_SEL */
514 #define BITS_LVDSDIS_LOG_SEL(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
515 #define BIT_LVDSDIS_DBG_SEL ( BIT(0) )
517 /* bits definitions for register REG_AON_APB_DJTAG_MUX_SEL */
518 #if defined(CONFIG_MACH_SP9830I)
519 #define BIT_DjTAG_CODEC_SEL (BIT(7))
521 #define BIT_DJTAG_AON_SEL ( BIT(6) )
522 #define BIT_DJTAG_PUB_SEL ( BIT(5) )
523 #define BIT_DJTAG_CP1_SEL ( BIT(4) )
524 #define BIT_DJTAG_CP0_SEL ( BIT(3) )
525 #define BIT_DJTAG_GPU_SEL ( BIT(2) )
526 #define BIT_DJTAG_MM_SEL ( BIT(1) )
527 #define BIT_DJTAG_AP_SEL ( BIT(0) )
529 /* bits definitions for register REG_AON_APB_ARM7_SYS_SOFT_RST */
530 #define BIT_ARM7_SYS_SOFT_RST ( BIT(4) )
531 #define BIT_ARM7_CORE_SOFT_RST ( BIT(0) )
533 /* bits definitions for register REG_AON_APB_CP1_CP0_ADDR_MSB */
534 #define BITS_CP1_CP0_ADDR_MSB(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
536 /* bits definitions for register REG_AON_APB_AON_DMA_INT_EN */
537 #define BIT_AON_DMA_INT_ARM7_EN ( BIT(6) )
538 #define BIT_AON_DMA_INT_CP1_DSP_EN ( BIT(5) )
539 #define BIT_AON_DMA_INT_CP1_CA5_EN ( BIT(4) )
540 #define BIT_AON_DMA_INT_CP0_DSP_1_EN ( BIT(3) )
541 #define BIT_AON_DMA_INT_CP0_DSP_0_EN ( BIT(2) )
542 #define BIT_AON_DMA_INT_CP0_ARM9_0_EN ( BIT(1) )
543 #define BIT_AON_DMA_INT_AP_EN ( BIT(0) )
545 /* bits definitions for register REG_AON_APB_EMC_AUTO_GATE_EN */
546 #define BIT_CP1_PUB_AUTO_GATE_EN ( BIT(19) )
547 #define BIT_CP0_PUB_AUTO_GATE_EN ( BIT(18) )
548 #define BIT_AP_PUB_AUTO_GATE_EN ( BIT(17) )
549 #define BIT_AON_APB_PUB_AUTO_GATE_EN ( BIT(16) )
550 #define BIT_CP1_EMC_AUTO_GATE_EN ( BIT(3) )
551 #define BIT_CP0_EMC_AUTO_GATE_EN ( BIT(2) )
552 #define BIT_AP_EMC_AUTO_GATE_EN ( BIT(1) )
553 #define BIT_CA7_EMC_AUTO_GATE_EN ( BIT(0) )
555 /* bits definitions for register REG_AON_APB_ARM7_CFG_BUS */
556 #define BIT_ARM7_CFG_BUS_SLEEP ( BIT(0) )
558 /* bits definitions for register REG_AON_APB_RTC4M_0_CFG */
559 #define BITS_RTC4M0_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
560 #define BITS_RTC4M0_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
561 #define BIT_RTC4M0_CAL_DONE ( BIT(6) )
562 #define BIT_RTC4M0_CAL_START ( BIT(5) )
563 #define BIT_RTC4M0_CHOP_EN ( BIT(4) )
564 #define BIT_RTC4M0_FORCE_EN ( BIT(1) )
565 #define BIT_RTC4M0_AUTO_GATE_EN ( BIT(0) )
567 /* bits definitions for register REG_AON_APB_RTC4M_1_CFG */
568 #define BITS_RTC4M1_RSV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
569 #define BITS_RTC4M1_I_C(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
570 #define BIT_RTC4M1_CAL_DONE ( BIT(6) )
571 #define BIT_RTC4M1_CAL_START ( BIT(5) )
572 #define BIT_RTC4M1_CHOP_EN ( BIT(4) )
573 #define BIT_RTC4M1_FORCE_EN ( BIT(1) )
574 #define BIT_RTC4M1_AUTO_GATE_EN ( BIT(0) )
576 /* bits definitions for register REG_AON_APB_APB_RST2 */
577 #if defined(CONFIG_MACH_SP9830I)
578 #define BIT_CODEC_DJTAG_SOFT_RST (BIT(7))
580 #define BIT_AON_DJTAG_SOFT_RST ( BIT(6) )
581 #define BIT_PUB_DJTAG_SOFT_RST ( BIT(5) )
582 #define BIT_GPU_DJTAG_SOFT_RST ( BIT(4) )
583 #define BIT_MM_DJTAG_SOFT_RST ( BIT(3) )
584 #define BIT_CP1_DJTAG_SOFT_RST ( BIT(2) )
585 #define BIT_CP0_DJTAG_SOFT_RST ( BIT(1) )
586 #define BIT_AP_DJTAG_SOFT_RST ( BIT(0) )
588 /* bits definitions for register REG_AON_APB_AP_WPROT_EN1 */
589 #define BITS_AP_AWADDR_WPROT_EN1(_X_) (_X_)
591 /* bits definitions for register REG_AON_APB_CP0_WPROT_EN1 */
592 #define BITS_CP0_AWADDR_WPROT_EN1(_X_) (_X_)
594 /* bits definitions for register REG_AON_APB_CP1_WPROT_EN1 */
595 #define BITS_CP1_AWADDR_WPROT_EN1(_X_) (_X_)
597 /* bits definitions for register REG_AON_APB_IO_DLY_CTRL */
598 #define BITS_CLK_CCIR_DLY_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
599 #define BITS_CLK_CP1DSP_DLY_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
600 #define BITS_CLK_CP0DSP_DLY_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
602 /* bits definitions for register REG_AON_APB_AP_WPROT_EN0 */
603 #define BITS_AP_AWADDR_WPROT_EN0(_X_) (_X_)
605 /* bits definitions for register REG_AON_APB_CP0_WPROT_EN0 */
606 #define BITS_CP0_AWADDR_WPROT_EN0(_X_) (_X_)
608 /* bits definitions for register REG_AON_APB_CP1_WPROT_EN0 */
609 #define BITS_CP1_AWADDR_WPROT_EN0(_X_) (_X_)
611 /* bits definitions for register REG_AON_APB_PMU_RST_MONITOR */
612 #define BITS_PMU_RST_MONITOR(_X_) (_X_)
614 /* bits definitions for register REG_AON_APB_THM_RST_MONITOR */
615 #define BITS_THM_RST_MONITOR(_X_) (_X_)
617 /* bits definitions for register REG_AON_APB_AP_RST_MONITOR */
618 #define BITS_AP_RST_MONITOR(_X_) (_X_)
620 /* bits definitions for register REG_AON_APB_CA7_RST_MONITOR */
621 #define BITS_CA7_RST_MONITOR(_X_) (_X_)
623 /* bits definitions for register REG_AON_APB_BOND_OPT0 */
624 #define BITS_BOND_OPTION0(_X_) (_X_)
626 /* bits definitions for register REG_AON_APB_BOND_OPT1 */
627 #define BITS_BOND_OPTION1(_X_) (_X_)
629 /* bits definitions for register REG_AON_APB_RES_REG0 */
630 #define BITS_RES_REG0(_X_) (_X_)
632 /* bits definitions for register REG_AON_APB_RES_REG1 */
633 #define BITS_RES_REG1(_X_) (_X_)
635 /* bits definitions for register REG_AON_APB_AON_QOS_CFG */
636 #define BITS_QOS_R_GPU(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
637 #define BITS_QOS_W_GPU(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
638 #define BITS_QOS_R_GSP(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
639 #define BITS_QOS_W_GSP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
641 /* bits definitions for register REG_AON_APB_BB_LDO_CAL_START */
642 #define BIT_BB_LDO_CAL_START ( BIT(0) )
644 /* bits definitions for register REG_AON_APB_AON_MTX_PROT_CFG */
645 #define BITS_HPROT_DMAW(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
646 #define BITS_HPROT_DMAR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
648 /* bits definitions for register REG_AON_APB_LVDS_CFG */
649 #define BITS_LVDSDIS_TXCLKDATA(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)) )
650 #define BITS_LVDSDIS_TXCOM(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)) )
651 #define BITS_LVDSDIS_TXSLEW(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
652 #define BITS_LVDSDIS_TXSW(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
653 #define BITS_LVDSDIS_TXRERSER(_X_) ( (_X_) << 3 & (BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
654 #define BITS_LVDSDIS_PRE_EMP(_X_) ( (_X_) << 1 & (BIT(1)|BIT(2)) )
655 #define BIT_LVDSDIS_TXPD ( BIT(0) )
657 /* bits definitions for register REG_AON_APB_PLL_LOCK_OUT_SEL */
658 #define BIT_SLEEP_PLLLOCK_SEL ( BIT(7) )
659 #define BITS_PLL_LOCK_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
660 #define BITS_SLEEP_DBG_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
662 /* bits definitions for register REG_AON_APB_RTC4M_RC_VAL */
663 #define BIT_RTC4M1_RC_SEL ( BIT(31) )
664 #define BITS_RTC4M1_RC_VAL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)) )
665 #define BIT_RTC4M0_RC_SEL ( BIT(15) )
666 #define BITS_RTC4M0_RC_VAL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
668 /* bits definitions for register REG_AON_APB_AON_APB_RSV */
669 #define BITS_AON_APB_RSV(_X_) (_X_)
671 /* bits definitions for register REG_AON_APB_AON_CHIP_ID */
672 #define BITS_AON_CHIP_ID(_X_) (_X_)
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