2 * Copyright (C) 2014 Spreadtrum Communications Inc.
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4 * This program is free software; you can redistribute it and/or
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5 * modify it under the terms of the GNU General Public License
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6 * as published by the Free Software Foundation; either version 2
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7 * of the License, or (at your option) any later version.
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9 * This program is distributed in the hope that it will be useful,
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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12 * GNU General Public License for more details.
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14 *************************************************
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15 * Automatically generated C header: do not edit *
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16 *************************************************
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19 #ifndef __SCI_GLB_REGS_H__
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20 #error "Don't include this file directly, Pls include sci_glb_regs.h"
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24 #ifndef __H_REGS_PUB_APB_HEADFILE_H__
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25 #define __H_REGS_PUB_APB_HEADFILE_H__ __FILE__
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27 #define REGS_PUB_APB
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29 /* registers definitions for PUB_APB */
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30 #define REG_PUB_APB_BUSMON_CNT_START SCI_ADDR(REGS_PUB_APB_BASE, 0x0000)
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31 #define REG_PUB_APB_BUSMON_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0004)
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32 #define REG_PUB_APB_DDR_EB SCI_ADDR(REGS_PUB_APB_BASE, 0x0008)
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33 #define REG_PUB_APB_DDR_SOFT_RST SCI_ADDR(REGS_PUB_APB_BASE, 0x000C)
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34 #define REG_PUB_APB_DDR_QOS_CFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0010)
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35 #define REG_PUB_APB_DDR_QOS_CFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0014)
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36 #define REG_PUB_APB_DDR_QOS_CFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x0018)
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37 #define REG_PUB_APB_DDR_MRR_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x001C)
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38 #define REG_PUB_APB_DDR_ID2QOS_SEL SCI_ADDR(REGS_PUB_APB_BASE, 0x003C)
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39 #define REG_PUB_APB_DDR_ID2QOS_RCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0040)
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40 #define REG_PUB_APB_DDR_ID2QOS_RCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0044)
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41 #define REG_PUB_APB_DDR_ID2QOS_RCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0048)
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42 #define REG_PUB_APB_DDR_ID2QOS_RCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x004c)
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43 #define REG_PUB_APB_DDR_ID2QOS_RCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0050)
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44 #define REG_PUB_APB_DDR_ID2QOS_RCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0054)
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45 #define REG_PUB_APB_DDR_ID2QOS_RCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0058)
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46 #define REG_PUB_APB_DDR_ID2QOS_RCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x005c)
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47 #define REG_PUB_APB_DDR_ID2QOS_RCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x0060)
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48 #define REG_PUB_APB_DDR_ID2QOS_RCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x0064)
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49 #define REG_PUB_APB_DDR_ID2QOS_WCFG0 SCI_ADDR(REGS_PUB_APB_BASE, 0x0080)
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50 #define REG_PUB_APB_DDR_ID2QOS_WCFG1 SCI_ADDR(REGS_PUB_APB_BASE, 0x0084)
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51 #define REG_PUB_APB_DDR_ID2QOS_WCFG2 SCI_ADDR(REGS_PUB_APB_BASE, 0x0088)
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52 #define REG_PUB_APB_DDR_ID2QOS_WCFG3 SCI_ADDR(REGS_PUB_APB_BASE, 0x008c)
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53 #define REG_PUB_APB_DDR_ID2QOS_WCFG4 SCI_ADDR(REGS_PUB_APB_BASE, 0x0090)
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54 #define REG_PUB_APB_DDR_ID2QOS_WCFG5 SCI_ADDR(REGS_PUB_APB_BASE, 0x0094)
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55 #define REG_PUB_APB_DDR_ID2QOS_WCFG6 SCI_ADDR(REGS_PUB_APB_BASE, 0x0098)
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56 #define REG_PUB_APB_DDR_ID2QOS_WCFG7 SCI_ADDR(REGS_PUB_APB_BASE, 0x009c)
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57 #define REG_PUB_APB_DDR_ID2QOS_WCFG8 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a0)
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58 #define REG_PUB_APB_DDR_ID2QOS_WCFG9 SCI_ADDR(REGS_PUB_APB_BASE, 0x00a4)
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59 #define REG_PUB_APB_DFI_TIMEOUT_CFG SCI_ADDR(REGS_PUB_APB_BASE, 0x0100)
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60 #define REG_PUB_APB_DFI_TIMEOUT_STATUS SCI_ADDR(REGS_PUB_APB_BASE, 0x0104)
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61 #define REG_PUB_APB_DFI_TIMEOUT_EN_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x0108)
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62 #define REG_PUB_APB_DFI_TIMEOUT_VALID_CNT SCI_ADDR(REGS_PUB_APB_BASE, 0x010c)
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63 #define REG_PUB_APB_DMC_PORT_REMAP_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3000)
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64 #define REG_PUB_APB_DMC_PORTS_MPU_EN SCI_ADDR(REGS_PUB_APB_BASE, 0x3004)
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65 #define REG_PUB_APB_DMC_PORT0_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3008)
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66 #define REG_PUB_APB_DMC_PORT1_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x300C)
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67 #define REG_PUB_APB_DMC_PORT2_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3010)
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68 #define REG_PUB_APB_DMC_PORT3_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3014)
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69 #define REG_PUB_APB_DMC_PORT4_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3018)
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70 #define REG_PUB_APB_DMC_PORT5_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x301C)
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71 #define REG_PUB_APB_DMC_PORT6_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3020)
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72 #define REG_PUB_APB_DMC_PORT7_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3024)
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73 #define REG_PUB_APB_DMC_PORT8_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x3028)
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74 #define REG_PUB_APB_DMC_PORT9_ADDR_REMAP SCI_ADDR(REGS_PUB_APB_BASE, 0x302C)
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75 #define REG_PUB_APB_DMC_PORT0_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3030)
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76 #define REG_PUB_APB_DMC_PORT1_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3034)
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77 #define REG_PUB_APB_DMC_PORT2_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3038)
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78 #define REG_PUB_APB_DMC_PORT3_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x303C)
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79 #define REG_PUB_APB_DMC_PORT4_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3040)
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80 #define REG_PUB_APB_DMC_PORT5_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3044)
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81 #define REG_PUB_APB_DMC_PORT6_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3048)
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82 #define REG_PUB_APB_DMC_PORT7_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3050)
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83 #define REG_PUB_APB_DMC_PORT8_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3054)
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84 #define REG_PUB_APB_DMC_PORT9_MPU_RANGE SCI_ADDR(REGS_PUB_APB_BASE, 0x3058)
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85 #define REG_PUB_APB_DMC_PORT0_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x305C)
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86 #define REG_PUB_APB_DMC_PORT1_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3060)
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87 #define REG_PUB_APB_DMC_PORT2_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3064)
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88 #define REG_PUB_APB_DMC_PORT3_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3068)
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89 #define REG_PUB_APB_DMC_PORT4_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x306C)
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90 #define REG_PUB_APB_DMC_PORT5_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3070)
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91 #define REG_PUB_APB_DMC_PORT6_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3074)
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92 #define REG_PUB_APB_DMC_PORT7_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3078)
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93 #define REG_PUB_APB_DMC_PORT8_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x307C)
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94 #define REG_PUB_APB_DMC_PORT9_DUMP_ADDR SCI_ADDR(REGS_PUB_APB_BASE, 0x3080)
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98 /* bits definitions for register REG_PUB_APB_BUSMON_CNT_START */
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99 #define BIT_PUB_BUSMON_CNT_START ( BIT(0) )
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101 /* bits definitions for register REG_PUB_APB_BUSMON_CFG */
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102 #define BIT_PUB_BUSMON9_EB ( BIT(25) )
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103 #define BIT_PUB_BUSMON8_EB ( BIT(24) )
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104 #define BIT_PUB_BUSMON7_EB ( BIT(23) )
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105 #define BIT_PUB_BUSMON6_EB ( BIT(22) )
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106 #define BIT_PUB_BUSMON5_EB ( BIT(21) )
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107 #define BIT_PUB_BUSMON4_EB ( BIT(20) )
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108 #define BIT_PUB_BUSMON3_EB ( BIT(19) )
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109 #define BIT_PUB_BUSMON2_EB ( BIT(18) )
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110 #define BIT_PUB_BUSMON1_EB ( BIT(17) )
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111 #define BIT_PUB_BUSMON0_EB ( BIT(16) )
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112 #define BIT_PUB_BUSMON9_SOFT_RST ( BIT(9) )
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113 #define BIT_PUB_BUSMON8_SOFT_RST ( BIT(8) )
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114 #define BIT_PUB_BUSMON7_SOFT_RST ( BIT(7) )
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115 #define BIT_PUB_BUSMON6_SOFT_RST ( BIT(6) )
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116 #define BIT_PUB_BUSMON5_SOFT_RST ( BIT(5) )
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117 #define BIT_PUB_BUSMON4_SOFT_RST ( BIT(4) )
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118 #define BIT_PUB_BUSMON3_SOFT_RST ( BIT(3) )
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119 #define BIT_PUB_BUSMON2_SOFT_RST ( BIT(2) )
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120 #define BIT_PUB_BUSMON1_SOFT_RST ( BIT(1) )
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121 #define BIT_PUB_BUSMON0_SOFT_RST ( BIT(0) )
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123 /* bits definitions for register REG_PUB_APB_DDR_EB */
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125 /* bits definitions for register REG_PUB_APB_DDR_SOFT_RST */
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127 /* bits definitions for register REG_PUB_APB_DDR_QOS_CFG1 */
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128 #define BITS_DMC_ARQOS_3(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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129 #define BITS_DMC_AWQOS_3(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
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130 #define BITS_DMC_ARQOS_2(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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131 #define BITS_DMC_AWQOS_2(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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132 #define BITS_DMC_ARQOS_1(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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133 #define BITS_DMC_AWQOS_1(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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134 #define BITS_DMC_ARQOS_0(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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135 #define BITS_DMC_AWQOS_0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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137 /* bits definitions for register REG_PUB_APB_DDR_QOS_CFG2 */
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138 #define BITS_DMC_ARQOS_7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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139 #define BITS_DMC_AWQOS_7(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
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140 #define BITS_DMC_ARQOS_6(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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141 #define BITS_DMC_AWQOS_6(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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142 #define BITS_DMC_ARQOS_5(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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143 #define BITS_DMC_AWQOS_5(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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144 #define BITS_DMC_ARQOS_4(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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145 #define BITS_DMC_AWQOS_4(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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147 /* bits definitions for register REG_PUB_APB_DDR_QOS_CFG3 */
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148 #define BITS_DMC_ARQOS_9(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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149 #define BITS_DMC_AWQOS_9(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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150 #define BITS_DMC_ARQOS_8(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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151 #define BITS_DMC_AWQOS_8(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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153 /* bits definitions for register REG_PUB_APB_DDR_MRR_STATUS */
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154 #define BIT_DDRC_CO_RD_MRR_DATA_VALID ( BIT(8) )
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155 #define BITS_DDRC_CO_RD_MRR_DATA(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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157 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_SEL */
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158 #define BITS_DMC_ID_SEL(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) )
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159 #define BITS_DMC_QOS_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
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161 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG0 */
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162 #define BITS_DMC_ARQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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163 #define BITS_DMC_ARQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
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164 #define BITS_DMC_ARQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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165 #define BITS_DMC_ARQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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166 #define BITS_DMC_ARQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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167 #define BITS_DMC_ARQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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168 #define BITS_DMC_ARQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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169 #define BITS_DMC_ARQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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171 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG1 */
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172 #define BITS_DMC_ARQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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173 #define BITS_DMC_ARQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
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174 #define BITS_DMC_ARQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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175 #define BITS_DMC_ARQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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176 #define BITS_DMC_ARQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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177 #define BITS_DMC_ARQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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178 #define BITS_DMC_ARQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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179 #define BITS_DMC_ARQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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181 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG2 */
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182 #define BITS_DMC_ARQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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183 #define BITS_DMC_ARQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
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184 #define BITS_DMC_ARQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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185 #define BITS_DMC_ARQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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186 #define BITS_DMC_ARQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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187 #define BITS_DMC_ARQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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188 #define BITS_DMC_ARQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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189 #define BITS_DMC_ARQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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191 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG3 */
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192 #define BITS_DMC_ARQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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193 #define BITS_DMC_ARQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
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194 #define BITS_DMC_ARQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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195 #define BITS_DMC_ARQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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196 #define BITS_DMC_ARQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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197 #define BITS_DMC_ARQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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198 #define BITS_DMC_ARQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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199 #define BITS_DMC_ARQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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201 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG4 */
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202 #define BITS_DMC_ARQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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203 #define BITS_DMC_ARQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
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204 #define BITS_DMC_ARQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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205 #define BITS_DMC_ARQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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206 #define BITS_DMC_ARQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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207 #define BITS_DMC_ARQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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208 #define BITS_DMC_ARQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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209 #define BITS_DMC_ARQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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211 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG5 */
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212 #define BITS_DMC_ARQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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213 #define BITS_DMC_ARQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
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214 #define BITS_DMC_ARQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
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215 #define BITS_DMC_ARQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
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216 #define BITS_DMC_ARQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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217 #define BITS_DMC_ARQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
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218 #define BITS_DMC_ARQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
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219 #define BITS_DMC_ARQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
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221 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG6 */
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222 #define BITS_DMC_ARQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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223 #define BITS_DMC_ARQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
224 #define BITS_DMC_ARQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
225 #define BITS_DMC_ARQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
226 #define BITS_DMC_ARQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
227 #define BITS_DMC_ARQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
228 #define BITS_DMC_ARQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
229 #define BITS_DMC_ARQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
231 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG7 */
\r
232 #define BITS_DMC_ARQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
233 #define BITS_DMC_ARQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
234 #define BITS_DMC_ARQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
235 #define BITS_DMC_ARQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
236 #define BITS_DMC_ARQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
237 #define BITS_DMC_ARQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
238 #define BITS_DMC_ARQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
239 #define BITS_DMC_ARQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
241 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG8 */
\r
242 #define BITS_DMC_ARQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
243 #define BITS_DMC_ARQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
244 #define BITS_DMC_ARQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
245 #define BITS_DMC_ARQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
246 #define BITS_DMC_ARQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
247 #define BITS_DMC_ARQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
248 #define BITS_DMC_ARQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
249 #define BITS_DMC_ARQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
251 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_RCFG9 */
\r
252 #define BITS_DMC_ARQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
253 #define BITS_DMC_ARQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
254 #define BITS_DMC_ARQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
255 #define BITS_DMC_ARQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
256 #define BITS_DMC_ARQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
257 #define BITS_DMC_ARQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
258 #define BITS_DMC_ARQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
259 #define BITS_DMC_ARQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
261 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG0 */
\r
262 #define BITS_DMC_AWQOS_0_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
263 #define BITS_DMC_AWQOS_0_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
264 #define BITS_DMC_AWQOS_0_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
265 #define BITS_DMC_AWQOS_0_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
266 #define BITS_DMC_AWQOS_0_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
267 #define BITS_DMC_AWQOS_0_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
268 #define BITS_DMC_AWQOS_0_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
269 #define BITS_DMC_AWQOS_0_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
271 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG1 */
\r
272 #define BITS_DMC_AWQOS_1_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
273 #define BITS_DMC_AWQOS_1_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
274 #define BITS_DMC_AWQOS_1_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
275 #define BITS_DMC_AWQOS_1_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
276 #define BITS_DMC_AWQOS_1_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
277 #define BITS_DMC_AWQOS_1_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
278 #define BITS_DMC_AWQOS_1_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
279 #define BITS_DMC_AWQOS_1_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
281 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG2 */
\r
282 #define BITS_DMC_AWQOS_2_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
283 #define BITS_DMC_AWQOS_2_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
284 #define BITS_DMC_AWQOS_2_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
285 #define BITS_DMC_AWQOS_2_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
286 #define BITS_DMC_AWQOS_2_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
287 #define BITS_DMC_AWQOS_2_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
288 #define BITS_DMC_AWQOS_2_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
289 #define BITS_DMC_AWQOS_2_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
291 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG3 */
\r
292 #define BITS_DMC_AWQOS_3_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
293 #define BITS_DMC_AWQOS_3_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
294 #define BITS_DMC_AWQOS_3_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
295 #define BITS_DMC_AWQOS_3_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
296 #define BITS_DMC_AWQOS_3_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
297 #define BITS_DMC_AWQOS_3_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
298 #define BITS_DMC_AWQOS_3_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
299 #define BITS_DMC_AWQOS_3_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
301 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG4 */
\r
302 #define BITS_DMC_AWQOS_4_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
303 #define BITS_DMC_AWQOS_4_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
304 #define BITS_DMC_AWQOS_4_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
305 #define BITS_DMC_AWQOS_4_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
306 #define BITS_DMC_AWQOS_4_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
307 #define BITS_DMC_AWQOS_4_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
308 #define BITS_DMC_AWQOS_4_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
309 #define BITS_DMC_AWQOS_4_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
311 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG5 */
\r
312 #define BITS_DMC_AWQOS_5_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
313 #define BITS_DMC_AWQOS_5_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
314 #define BITS_DMC_AWQOS_5_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
315 #define BITS_DMC_AWQOS_5_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
316 #define BITS_DMC_AWQOS_5_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
317 #define BITS_DMC_AWQOS_5_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
318 #define BITS_DMC_AWQOS_5_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
319 #define BITS_DMC_AWQOS_5_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
321 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG6 */
\r
322 #define BITS_DMC_AWQOS_6_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
323 #define BITS_DMC_AWQOS_6_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
324 #define BITS_DMC_AWQOS_6_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
325 #define BITS_DMC_AWQOS_6_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
326 #define BITS_DMC_AWQOS_6_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
327 #define BITS_DMC_AWQOS_6_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
328 #define BITS_DMC_AWQOS_6_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
329 #define BITS_DMC_AWQOS_6_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
331 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG7 */
\r
332 #define BITS_DMC_AWQOS_7_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
333 #define BITS_DMC_AWQOS_7_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
334 #define BITS_DMC_AWQOS_7_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
335 #define BITS_DMC_AWQOS_7_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
336 #define BITS_DMC_AWQOS_7_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
337 #define BITS_DMC_AWQOS_7_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
338 #define BITS_DMC_AWQOS_7_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
339 #define BITS_DMC_AWQOS_7_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
341 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG8 */
\r
342 #define BITS_DMC_AWQOS_8_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
343 #define BITS_DMC_AWQOS_8_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
344 #define BITS_DMC_AWQOS_8_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
345 #define BITS_DMC_AWQOS_8_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
346 #define BITS_DMC_AWQOS_8_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
347 #define BITS_DMC_AWQOS_8_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
348 #define BITS_DMC_AWQOS_8_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
349 #define BITS_DMC_AWQOS_8_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
351 /* bits definitions for register REG_PUB_APB_DDR_ID2QOS_WCFG9 */
\r
352 #define BITS_DMC_AWQOS_9_ID7(_X_) ( (_X_) << 28 & (BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
353 #define BITS_DMC_AWQOS_9_ID6(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)) )
\r
354 #define BITS_DMC_AWQOS_9_ID5(_X_) ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
355 #define BITS_DMC_AWQOS_9_ID4(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
356 #define BITS_DMC_AWQOS_9_ID3(_X_) ( (_X_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
357 #define BITS_DMC_AWQOS_9_ID2(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
\r
358 #define BITS_DMC_AWQOS_9_ID1(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
359 #define BITS_DMC_AWQOS_9_ID0(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
361 /* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_CFG */
\r
362 #define BITS_DFI_TIMEOUT_THRESHOLD(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
363 #define BITS_DFI_TIMEOUT_CLR(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
364 #define BITS_DFI_TIMEOUT_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
366 /* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_STATUS */
\r
367 #define BITS_DFI_TIMEOUT_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
\r
369 /* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_EN_CNT */
\r
370 #define BITS_DFI_TIMEOUT_EN3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
371 #define BITS_DFI_TIMEOUT_EN2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
372 #define BITS_DFI_TIMEOUT_EN1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
373 #define BITS_DFI_TIMEOUT_EN0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
375 /* bits definitions for register REG_PUB_APB_DFI_TIMEOUT_VALID_CNT */
\r
376 #define BITS_DFI_TIMEOUT_VALID3_CNT(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
\r
377 #define BITS_DFI_TIMEOUT_VALID2_CNT(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
\r
378 #define BITS_DFI_TIMEOUT_VALID1_CNT(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
\r
379 #define BITS_DFI_TIMEOUT_VALID0_CNT(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
\r
381 /* bits definitions for register REG_PUB_APB_DMC_PORT_REMAP_EN */
\r
382 #define BITS_DMC_PORTS_REMAP_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
384 /* bits definitions for register REG_PUB_APB_DMC_PORTS_MPU_EN */
\r
385 #define BITS_DMC_PORTS_MPU_EN(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
\r
387 /* bits definitions for register REG_PUB_APB_DMC_PORT0_ADDR_REMAP */
\r
388 #define BITS_DMC_PORT0_ADDR_REMAP(_X_) (_X_)
\r
390 /* bits definitions for register REG_PUB_APB_DMC_PORT1_ADDR_REMAP */
\r
391 #define BITS_DMC_PORT1_ADDR_REMAP(_X_) (_X_)
\r
393 /* bits definitions for register REG_PUB_APB_DMC_PORT2_ADDR_REMAP */
\r
394 #define BITS_DMC_PORT2_ADDR_REMAP(_X_) (_X_)
\r
396 /* bits definitions for register REG_PUB_APB_DMC_PORT3_ADDR_REMAP */
\r
397 #define BITS_DMC_PORT3_ADDR_REMAP(_X_) (_X_)
\r
399 /* bits definitions for register REG_PUB_APB_DMC_PORT4_ADDR_REMAP */
\r
400 #define BITS_DMC_PORT4_ADDR_REMAP(_X_) (_X_)
\r
402 /* bits definitions for register REG_PUB_APB_DMC_PORT5_ADDR_REMAP */
\r
403 #define BITS_DMC_PORT5_ADDR_REMAP(_X_) (_X_)
\r
405 /* bits definitions for register REG_PUB_APB_DMC_PORT6_ADDR_REMAP */
\r
406 #define BITS_DMC_PORT6_ADDR_REMAP(_X_) (_X_)
\r
408 /* bits definitions for register REG_PUB_APB_DMC_PORT7_ADDR_REMAP */
\r
409 #define BITS_DMC_PORT7_ADDR_REMAP(_X_) (_X_)
\r
411 /* bits definitions for register REG_PUB_APB_DMC_PORT8_ADDR_REMAP */
\r
412 #define BITS_DMC_PORT8_ADDR_REMAP(_X_) (_X_)
\r
414 /* bits definitions for register REG_PUB_APB_DMC_PORT9_ADDR_REMAP */
\r
415 #define BITS_DMC_PORT9_ADDR_REMAP(_X_) (_X_)
\r
417 /* bits definitions for register REG_PUB_APB_DMC_PORT0_MPU_RANGE */
\r
418 #define BITS_DMC_PORT0_MPU_RANGE(_X_) (_X_)
\r
420 /* bits definitions for register REG_PUB_APB_DMC_PORT1_MPU_RANGE */
\r
421 #define BITS_DMC_PORT1_MPU_RANGE(_X_) (_X_)
\r
423 /* bits definitions for register REG_PUB_APB_DMC_PORT2_MPU_RANGE */
\r
424 #define BITS_DMC_PORT2_MPU_RANGE(_X_) (_X_)
\r
426 /* bits definitions for register REG_PUB_APB_DMC_PORT3_MPU_RANGE */
\r
427 #define BITS_DMC_PORT3_MPU_RANGE(_X_) (_X_)
\r
429 /* bits definitions for register REG_PUB_APB_DMC_PORT4_MPU_RANGE */
\r
430 #define BITS_DMC_PORT4_MPU_RANGE(_X_) (_X_)
\r
432 /* bits definitions for register REG_PUB_APB_DMC_PORT5_MPU_RANGE */
\r
433 #define BITS_DMC_PORT5_MPU_RANGE(_X_) (_X_)
\r
435 /* bits definitions for register REG_PUB_APB_DMC_PORT6_MPU_RANGE */
\r
436 #define BITS_DMC_PORT6_MPU_RANGE(_X_) (_X_)
\r
438 /* bits definitions for register REG_PUB_APB_DMC_PORT7_MPU_RANGE */
\r
439 #define BITS_DMC_PORT7_MPU_RANGE(_X_) (_X_)
\r
441 /* bits definitions for register REG_PUB_APB_DMC_PORT8_MPU_RANGE */
\r
442 #define BITS_DMC_PORT8_MPU_RANGE(_X_) (_X_)
\r
444 /* bits definitions for register REG_PUB_APB_DMC_PORT9_MPU_RANGE */
\r
445 #define BITS_DMC_PORT9_MPU_RANGE(_X_) (_X_)
\r
447 /* bits definitions for register REG_PUB_APB_DMC_PORT0_DUMP_ADDR */
\r
448 #define BITS_DMC_PORT0_DUMP_ADDR(_X_) (_X_)
\r
450 /* bits definitions for register REG_PUB_APB_DMC_PORT1_DUMP_ADDR */
\r
451 #define BITS_DMC_PORT1_DUMP_ADDR(_X_) (_X_)
\r
453 /* bits definitions for register REG_PUB_APB_DMC_PORT2_DUMP_ADDR */
\r
454 #define BITS_DMC_PORT2_DUMP_ADDR(_X_) (_X_)
\r
456 /* bits definitions for register REG_PUB_APB_DMC_PORT3_DUMP_ADDR */
\r
457 #define BITS_DMC_PORT3_DUMP_ADDR(_X_) (_X_)
\r
459 /* bits definitions for register REG_PUB_APB_DMC_PORT4_DUMP_ADDR */
\r
460 #define BITS_DMC_PORT4_DUMP_ADDR(_X_) (_X_)
\r
462 /* bits definitions for register REG_PUB_APB_DMC_PORT5_DUMP_ADDR */
\r
463 #define BITS_DMC_PORT5_DUMP_ADDR(_X_) (_X_)
\r
465 /* bits definitions for register REG_PUB_APB_DMC_PORT6_DUMP_ADDR */
\r
466 #define BITS_DMC_PORT6_DUMP_ADDR(_X_) (_X_)
\r
468 /* bits definitions for register REG_PUB_APB_DMC_PORT7_DUMP_ADDR */
\r
469 #define BITS_DMC_PORT7_DUMP_ADDR(_X_) (_X_)
\r
471 /* bits definitions for register REG_PUB_APB_DMC_PORT8_DUMP_ADDR */
\r
472 #define BITS_DMC_PORT8_DUMP_ADDR(_X_) (_X_)
\r
474 /* bits definitions for register REG_PUB_APB_DMC_PORT9_DUMP_ADDR */
\r
475 #define BITS_DMC_PORT9_DUMP_ADDR(_X_) (_X_)
\r
projects / profile / mobile / platform / kernel / linux-3.10-sc7730.git / blob