2 * Copyright (C) 2014 Spreadtrum Communications Inc.
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4 * This program is free software; you can redistribute it and/or
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5 * modify it under the terms of the GNU General Public License
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6 * as published by the Free Software Foundation; either version 2
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7 * of the License, or (at your option) any later version.
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9 * This program is distributed in the hope that it will be useful,
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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12 * GNU General Public License for more details.
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14 *************************************************
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15 * Automatically generated C header: do not edit *
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16 *************************************************
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19 #ifndef __SCI_GLB_REGS_H__
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20 #error "Don't include this file directly, Pls include sci_glb_regs.h"
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24 #ifndef __H_REGS_CP_APB_RF_HEADFILE_H__
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25 #define __H_REGS_CP_APB_RF_HEADFILE_H__ __FILE__
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27 #define REGS_CP_APB_RF
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29 /* registers definitions for CP_APB_RF */
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30 #define REG_CP_APB_RF_APB_EB0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0008)
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31 #define REG_CP_APB_RF_APB_RST0_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0014)
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32 #define REG_CP_APB_RF_APB_MCU_RST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0018)
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33 #define REG_CP_APB_RF_APB_CLK_SEL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x001C)
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34 #define REG_CP_APB_RF_APB_CLK_DIV0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0020)
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35 #define REG_CP_APB_RF_APB_ARCH_EB SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0024)
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36 #define REG_CP_APB_RF_APB_MISC_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0028)
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37 #define REG_CP_APB_RF_APB_MISC_CTL1 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x002C)
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38 #define REG_CP_APB_RF_APB_PIN_SEL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0040)
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39 #define REG_CP_APB_RF_APB_SLP_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0044)
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40 #define REG_CP_APB_RF_APB_WSYS_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0048)
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41 #define REG_CP_APB_RF_APB_SLP_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0050)
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42 #define REG_CP_APB_RF_APB_ROM_PD_CTL SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0054)
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43 #define REG_CP_APB_RF_APB_BUS_CTL0 SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0058)
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44 #define REG_CP_APB_RF_APB_DSP_INT_CLR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0074)
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45 #define REG_CP_APB_RF_APB_MISC_INT_STS SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0078)
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46 #define REG_CP_APB_RF_APB_HWRST SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0080)
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47 #define REG_CP_APB_RF_APB_ARM_BOOT_ADDR SCI_ADDR(REGS_CP_APB_RF_BASE, 0x0084)
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51 /* bits definitions for register REG_CP_APB_RF_APB_EB0_STS */
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52 #define BIT_ADA_EB ( BIT(18) )
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53 #define BIT_RFFE_EB ( BIT(17) )
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54 #define BIT_EPT_EB ( BIT(16) )
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55 #define BIT_GPIO_EB ( BIT(15) )
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56 #define BIT_TMR_RTC_EB ( BIT(14) )
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57 #define BIT_TMR_EB ( BIT(13) )
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58 #define BIT_SYSTMR_RTC_EB ( BIT(12) )
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59 #define BIT_SYSTMR_EB ( BIT(11) )
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60 #define BIT_IIS3_EB ( BIT(10) )
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61 #define BIT_IIS2_EB ( BIT(9) )
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62 #define BIT_IIS1_EB ( BIT(8) )
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63 #define BIT_IIS0_EB ( BIT(7) )
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64 #define BIT_SIM2_EB ( BIT(6) )
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65 #define BIT_SIM1_EB ( BIT(5) )
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66 #define BIT_SIM0_EB ( BIT(4) )
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67 #define BIT_UART1_EB ( BIT(3) )
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68 #define BIT_UART0_EB ( BIT(2) )
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69 #define BIT_WDG_RTC_EB ( BIT(1) )
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70 #define BIT_WDG_EB ( BIT(0) )
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72 /* bits definitions for register REG_CP_APB_RF_APB_RST0_STS */
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73 #define BIT_ADA_TX_SOFT_RST ( BIT(18) )
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74 #define BIT_ADA_RX_SOFT_RST ( BIT(17) )
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75 #define BIT_ADA_SOFT_RST ( BIT(16) )
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76 #define BIT_RFFE_SOFT_RST ( BIT(15) )
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77 #define BIT_MCU_DSP_RST ( BIT(14) )
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78 #define BIT_EPT_SOFT_RST ( BIT(13) )
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79 #define BIT_GPIO_SOFT_RST ( BIT(12) )
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80 #define BIT_TMR_SOFT_RST ( BIT(11) )
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81 #define BIT_SYSTMR_SOFT_RST ( BIT(10) )
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82 #define BIT_IIS3_SOFT_RST ( BIT(9) )
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83 #define BIT_IIS2_SOFT_RST ( BIT(8) )
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84 #define BIT_IIS1_SOFT_RST ( BIT(7) )
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85 #define BIT_IIS0_SOFT_RST ( BIT(6) )
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86 #define BIT_SIM2_SOFT_RST ( BIT(5) )
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87 #define BIT_SIM1_SOFT_RST ( BIT(4) )
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88 #define BIT_SIM0_SOFT_RST ( BIT(3) )
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89 #define BIT_UART1_SOFT_RST ( BIT(2) )
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90 #define BIT_UART0_SOFT_RST ( BIT(1) )
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91 #define BIT_WDG_SOFT_RST ( BIT(0) )
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93 /* bits definitions for register REG_CP_APB_RF_APB_MCU_RST */
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94 #define BIT_MCU_SOFT_RST_SET ( BIT(0) )
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96 /* bits definitions for register REG_CP_APB_RF_APB_CLK_SEL0 */
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97 #define BITS_CLK_IIS3_SEL(_X_) ( (_X_) << 10 & (BIT(10)|BIT(11)) )
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98 #define BITS_CLK_IIS2_SEL(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)) )
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99 #define BITS_CLK_IIS1_SEL(_X_) ( (_X_) << 6 & (BIT(6)|BIT(7)) )
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100 #define BITS_CLK_IIS0_SEL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)) )
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101 #define BITS_CLK_UART1_SEL(_X_) ( (_X_) << 2 & (BIT(2)|BIT(3)) )
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102 #define BITS_CLK_UART0_SEL(_X_) ( (_X_) & (BIT(0)|BIT(1)) )
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104 /* bits definitions for register REG_CP_APB_RF_APB_CLK_DIV0 */
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105 #define BITS_CLK_IIS2_DIV(_X_) ( (_X_) << 24 & (BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)) )
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106 #define BITS_CLK_IIS1_DIV(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)) )
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107 #define BITS_CLK_IIS0_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
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108 #define BITS_CLK_UART1_DIV(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
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109 #define BITS_CLK_UART0_DIV(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
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111 /* bits definitions for register REG_CP_APB_RF_APB_ARCH_EB */
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112 #define BITS_CLK_IIS3_DIV(_X_) ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
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113 #define BIT_RTC_ARCH_EB ( BIT(1) )
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114 #define BIT_APB_ARCH_EB ( BIT(0) )
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116 /* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL0 */
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117 #define BIT_ALL_CLK_EN ( BIT(28) )
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118 #define BIT_DMA_LSLP_EN ( BIT(27) )
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119 #define BIT_WAKEUP_XTL_EN_3G_W ( BIT(26) )
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120 #define BIT_WAKEUP_XTL_EN_2G ( BIT(25) )
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121 #define BIT_ARM_JTAG_EN ( BIT(24) )
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122 #define BIT_WAKEUP_XTL_EN_3G_TD ( BIT(23) )
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123 #define BITS_ARM_FRC_STOP(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
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125 /* bits definitions for register REG_CP_APB_RF_APB_MISC_CTL1 */
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126 #define BITS_BUFON_CTRL(_X_) ( (_X_) << 4 & (BIT(4)|BIT(5)|BIT(6)) )
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127 #define BIT_SIM2_CLK_POLARITY ( BIT(3) )
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128 #define BIT_SIM1_CLK_POLARITY ( BIT(2) )
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129 #define BIT_SIM0_CLK_POLARITY ( BIT(1) )
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130 #define BIT_ROM_CLK_EN ( BIT(0) )
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132 /* bits definitions for register REG_CP_APB_RF_APB_PIN_SEL */
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133 #define BIT_DJTAG_PIN_IN_SEL ( BIT(0) )
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135 /* bits definitions for register REG_CP_APB_RF_APB_SLP_CTL */
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136 #define BIT_APB_PERI_FRC_ON ( BIT(20) )
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137 #define BIT_APB_PERI_FRC_SLP ( BIT(16) )
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138 #define BIT_MCU_XTLEN_AUTOPD_EN ( BIT(12) )
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139 #define BIT_CHIP_SLP_ARM_CLR ( BIT(4) )
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140 #define BIT_MCU_FORCE_WSYS_LT_STOP ( BIT(2) )
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141 #define BIT_MCU_FORCE_WSYS_STOP ( BIT(1) )
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142 #define BIT_MCU_FORCE_DEEP_SLEEP ( BIT(0) )
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144 /* bits definitions for register REG_CP_APB_RF_APB_WSYS_STS */
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145 #define BITS_DEEP_SLP_DBG(_X_) ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
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146 #define BITS_WSYS_STATUS(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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148 /* bits definitions for register REG_CP_APB_RF_APB_SLP_STS */
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149 #define BIT_DSP_MAHB_SLEEP_EN ( BIT(28) )
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150 #define BIT_MCU_PERI_STOP ( BIT(27) )
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151 #define BIT_DSP_PERI_STOP ( BIT(26) )
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152 #define BIT_ECC_CKG_EN ( BIT(25) )
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153 #define BIT_QBC_CKG_EN ( BIT(24) )
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154 #define BIT_DSP_DPLL_EN ( BIT(23) )
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155 #define BIT_DSP_TDPLL_EN ( BIT(22) )
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156 #define BIT_DSP_MPLL_EN ( BIT(21) )
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157 #define BIT_STC_TMR_AUTOPD_XTL_EN ( BIT(20) )
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158 #define BIT_RFT_TMR_AUTOPD_XTL_EN ( BIT(19) )
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159 #define BIT_STC_TMR_AUTOPD_RF_EN ( BIT(18) )
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160 #define BIT_RFT_TMR_AUTOPD_RF_EN ( BIT(17) )
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161 #define BIT_CHIP_SLEEP_REC_ARM ( BIT(16) )
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162 #define BIT_DSP_CORE_STOP ( BIT(15) )
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163 #define BIT_DSP_MTX_STOP ( BIT(14) )
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164 #define BIT_DSP_AHB_STOP ( BIT(13) )
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165 #define BIT_DSP_SYS_STOP ( BIT(12) )
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166 #define BIT_DSP_DEEP_STOP ( BIT(11) )
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167 #define BIT_ASHB_DSPTOARM_EN ( BIT(10) )
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168 #define BIT_ASHB_ARMTODSP_VALID ( BIT(9) )
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169 #define BIT_EMC_STOP_CH3 ( BIT(8) )
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170 #define BIT_EMC_STOP_CH4 ( BIT(7) )
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171 #define BIT_EMC_STOP_CH5 ( BIT(6) )
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172 #define BIT_FRC_WAKE_EN ( BIT(5) )
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173 #define BIT_TMR_WAKE_AFC ( BIT(4) )
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174 #define BIT_SCH_SLEEP ( BIT(3) )
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175 #define BIT_DSP_STOP ( BIT(2) )
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176 #define BIT_MCU_STOP ( BIT(1) )
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177 #define BIT_EMC_STOP ( BIT(0) )
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179 /* bits definitions for register REG_CP_APB_RF_APB_ROM_PD_CTL */
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180 #define BIT_ROM_FORCE_ON ( BIT(0) )
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182 /* bits definitions for register REG_CP_APB_RF_APB_BUS_CTL0 */
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183 #define BIT_ADA_CTRL_SEL ( BIT(6) )
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184 #define BIT_RFFE_CTRL_SEL ( BIT(5) )
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185 #define BIT_IIS3_CTRL_SEL ( BIT(4) )
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186 #define BIT_IIS2_CTRL_SEL ( BIT(3) )
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187 #define BIT_IIS1_CTRL_SEL ( BIT(2) )
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188 #define BIT_IIS0_CTRL_SEL ( BIT(1) )
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189 #define BIT_UART1_CTRL_SEL ( BIT(0) )
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191 /* bits definitions for register REG_CP_APB_RF_APB_DSP_INT_CLR */
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192 #define BIT_RFT_INT_CLR ( BIT(2) )
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194 /* bits definitions for register REG_CP_APB_RF_APB_MISC_INT_STS */
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195 #define BIT_RFT_INT ( BIT(2) )
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197 /* bits definitions for register REG_CP_APB_RF_APB_HWRST */
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198 #define BITS_HWRST_REG(_X_) (_X_)
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200 /* bits definitions for register REG_CP_APB_RF_APB_ARM_BOOT_ADDR */
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201 #define BITS_ARMBOOT_ADDR(_X_) ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
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