include/soc/sprd/chip_x20l/__regs_lte_cevax_pmu.h

   1 /*
   2  * Copyright (C) 2014 Spreadtrum Communications Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  *************************************************
  15  * Automatically generated C header: do not edit *
  16  *************************************************
  17  */
  18
  19 #ifndef __SCI_GLB_REGS_H__
  20 #error  "Don't include this file directly, Pls include sci_glb_regs.h"
  21 #endif
  22
  23
  24 #ifndef __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__
  25 #define __H_REGS_LTE_CEVAX_PMU_HEADFILE_H__ __FILE__
  26
  27 #define REGS_LTE_CEVAX_PMU
  28
  29 /* registers definitions for LTE_CEVAX_PMU */
  30 #define REG_LTE_CEVAX_PMU_PLL_CFG0                        SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0000)
  31 #define REG_LTE_CEVAX_PMU_PLL_CFG1                        SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0004)
  32 #define REG_LTE_CEVAX_PMU_CXCLK_DIV                       SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0008)
  33 #define REG_LTE_CEVAX_PMU_XHCLK_DIV                       SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x000C)
  34 #define REG_LTE_CEVAX_PMU_XPCLK_DIV                       SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0010)
  35 #define REG_LTE_CEVAX_PMU_CXPMOD                          SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0014)
  36 #define REG_LTE_CEVAX_PMU_XHPMOD                          SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0018)
  37 #define REG_LTE_CEVAX_PMU_XAPBMOD                         SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x001C)
  38 #define REG_LTE_CEVAX_PMU_VERSION_CR                      SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0020)
  39 #define REG_LTE_CEVAX_PMU_SLEEP_STATUS                    SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0024)
  40 #define REG_LTE_CEVAX_PMU_POW_CTL0                        SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0028)
  41 #define REG_LTE_CEVAX_PMU_POW_CTL1                        SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x002C)
  42 #define REG_LTE_CEVAX_PMU_POW_CTL2                        SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0030)
  43 #define REG_LTE_CEVAX_PMU_ACCCLK_EN0                      SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0034)
  44 #define REG_LTE_CEVAX_PMU_ACCCLK_EN1                      SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0038)
  45 #define REG_LTE_CEVAX_PMU_ACCCLK_EN2                      SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x003C)
  46 #define REG_LTE_CEVAX_PMU_SOFT_RST0                       SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0040)
  47 #define REG_LTE_CEVAX_PMU_SOFT_RST1                       SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0044)
  48 #define REG_LTE_CEVAX_PMU_DSP_CKG_SEL                     SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0048)
  49 #define REG_LTE_CEVAX_PMU_CLK_DLCH_SEL                    SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0050)
  50 #define REG_LTE_CEVAX_PMU_CLK_ULCH_SEL                    SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0054)
  51 #define REG_LTE_CEVAX_PMU_CLK_RATEM_SEL                   SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0058)
  52 #define REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL             SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x005C)
  53 #define REG_LTE_CEVAX_PMU_CX_CKG_DIV                      SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0078)
  54 #define REG_LTE_CEVAX_PMU_XH_CKG_DIV                      SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x007C)
  55 #define REG_LTE_CEVAX_PMU_XP_CKG_DIV                      SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0080)
  56 #define REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN                  SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0084)
  57 #define REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN                  SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0088)
  58 #define REG_LTE_CEVAX_PMU_APB_CLK_SEL0                    SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x008C)
  59 #define REG_LTE_CEVAX_PMU_APB_CLK_SEL1                    SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0090)
  60 #define REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL                  SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0094)
  61 #define REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL                  SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0098)
  62 #define REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL                  SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x009C)
  63 #define REG_LTE_CEVAX_PMU_APB_CLK_SEL2                    SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x00A0)
  64 #define REG_LTE_CEVAX_PMU_MEM_LP_CTRL                     SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0xA4)
  65 #define REG_LTE_CEVAX_PMU_AXI_MON_CTRL                    SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0xA8)
  66 #define REG_LTE_CEVAX_PMU_RES_REG0                        SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0140)
  67 #define REG_LTE_CEVAX_PMU_RES_REG1                        SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0144)
  68 #define REG_LTE_CEVAX_PMU_RES_REG2                        SCI_ADDR(REGS_LTE_CEVAX_PMU_BASE, 0x0148)
  69
  70
  71
  72 /* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG0 */
  73 #define BITS_PLL_CFG0_R(_X_)                              ( (_X_) << 11 & (BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)|BIT(27)|BIT(28)|BIT(29)|BIT(30)|BIT(31)) )
  74 #define BIT_DSP_DLCH_EN                                   ( BIT(8) )
  75 #define BIT_DSP_ULCH_EN                                   ( BIT(7) )
  76 #define BIT_DLCH_AUTO_EN                                  ( BIT(6) )
  77 #define BIT_ULCH_AUTO_EN                                  ( BIT(5) )
  78 #define BIT_UART1_EB                                      ( BIT(2) )
  79 #define BIT_UART0_EB                                      ( BIT(1) )
  80 #define BIT_RFFE_EB                                       ( BIT(0) )
  81
  82 /* bits definitions for register REG_LTE_CEVAX_PMU_PLL_CFG1 */
  83 #define BIT_CHIP_SLP_REC_DSP                              ( BIT(16) )
  84 #define BIT_LTE_POW_OFF                                   ( BIT(10) )
  85 #define BIT_LTE_POW_READY                                 ( BIT(9) )
  86 #define BITS_LTE_POW_WAIT(_X_)                            ( (_X_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)) )
  87 #define BIT_CHIP_SLP_DSP_CLR                              ( BIT(0) )
  88
  89 /* bits definitions for register REG_LTE_CEVAX_PMU_CXCLK_DIV */
  90 #define BITS_CXREG_AUTO_OFF(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
  91
  92 /* bits definitions for register REG_LTE_CEVAX_PMU_XHCLK_DIV */
  93 #define BIT_BUSMON2_CHN_SEL                               ( BIT(25) )
  94 #define BIT_BUSMON1_CHN_SEL                               ( BIT(24) )
  95 #define BIT_BUSMON0_CHN_SEL                               ( BIT(23) )
  96 #define BITS_DSP_SHM_CTRL(_X_)                            ( (_X_) << 21 & (BIT(21)|BIT(22)) )
  97 #define BIT_DSPAPB_DES_AUTO_EN                            ( BIT(20) )
  98 #define BIT_DSPAHB_DES_AUTO_EN                            ( BIT(19) )
  99 #define BITS_LBUSMON2_CHN_SEL(_X_)                        ( (_X_) << 12 & (BIT(12)|BIT(13)) )
 100 #define BITS_LBUSMON1_CHN_SEL(_X_)                        ( (_X_) << 10 & (BIT(10)|BIT(11)) )
 101 #define BITS_LBUSMON0_CHN_SEL(_X_)                        ( (_X_) << 8 & (BIT(8)|BIT(9)) )
 102 #define BITS_DSPAPB_DIV_DES(_X_)                          ( (_X_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
 103 #define BITS_DSPAHB_DIV_DES(_X_)                          ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) )
 104 #define BITS_CX_DSPPLL_SEL(_X_)                           ( (_X_) & (BIT(0)|BIT(1)) )
 105
 106 /* bits definitions for register REG_LTE_CEVAX_PMU_XPCLK_DIV */
 107 #define BIT_PMU_DMA_FRC_EB                                ( BIT(24) )
 108 #define BIT_ZBUS_32ACCESS                                 ( BIT(0) )
 109
 110 /* bits definitions for register REG_LTE_CEVAX_PMU_CXPMOD */
 111 #define BIT_MCU_FORCE_DEEP_SLEEP                          ( BIT(31) )
 112 #define BIT_LDSP_DEEP_SLP_CTRL                            ( BIT(30) )
 113 #define BIT_EMC_LIGHT_SLEEP_EN_M6                         ( BIT(29) )
 114 #define BIT_EMC_DEEP_SLEEP_EN_M6                          ( BIT(28) )
 115 #define BIT_EMC_LIGHT_SLEEP_EN_M7                         ( BIT(27) )
 116 #define BIT_EMC_DEEP_SLEEP_EN_M7                          ( BIT(26) )
 117 #define BIT_EMC_LIGHT_SLEEP_EN_M8                         ( BIT(25) )
 118 #define BIT_EMC_DEEP_SLEEP_EN_M8                          ( BIT(24) )
 119 #define BIT_LDSP2PUB_ACCESS_EN                            ( BIT(8) )
 120 #define BIT_LDSP_WAKEUP_XTL_EN                            ( BIT(7) )
 121 #define BIT_DMA_LSLP_EN                                   ( BIT(4) )
 122 #define BIT_DSP_LIGHT_SLEEP_EN                            ( BIT(3) )
 123 #define BIT_DSP_DEEP_SLEEP_EN                             ( BIT(2) )
 124 #define BIT_DSP_SYS_SLEEP_EN                              ( BIT(1) )
 125 #define BIT_DSP_CORE_SLEEP                                ( BIT(0) )
 126
 127 /* bits definitions for register REG_LTE_CEVAX_PMU_XHPMOD */
 128 #define BIT_BUSMON2_EB                                    ( BIT(31) )
 129 #define BIT_BUSMON1_EB                                    ( BIT(30) )
 130 #define BIT_BUSMON0_EB                                    ( BIT(29) )
 131 #define BIT_LACCX_AUTO_GATE_EN                            ( BIT(14) )
 132 #define BIT_LDSPX_AUTO_GATE_EN                            ( BIT(13) )
 133 #define BIT_CXDMA_CLK_AUTO_EN                             ( BIT(12) )
 134 #define BIT_CXAPB_AUTO_GATE_EN                            ( BIT(11) )
 135 #define BIT_CXAHB_AUTO_GATE_EN                            ( BIT(10) )
 136 #define BIT_CXDSP_AUTO_GATE_EN                            ( BIT(9) )
 137 #define BIT_CXCORE_AUTO_GATE_EN                           ( BIT(8) )
 138 #define BIT_CXMTX_AUTO_GATE_EN                            ( BIT(7) )
 139 #define BIT_DSP_MAHB_SLEEP_EN                             ( BIT(6) )
 140 #define BIT_ACCZ_ARCH_EB                                  ( BIT(5) )
 141 #define BIT_CXBUS_ARCH_EB                                 ( BIT(4) )
 142 #define BIT_LTEPROC_ARCH_EB                               ( BIT(3) )
 143 #define BIT_PMU_DLCH_SLEEP_R                              ( BIT(1) )
 144 #define BIT_PMU_ULCH_SLEEP_R                              ( BIT(0) )
 145
 146 /* bits definitions for register REG_LTE_CEVAX_PMU_XAPBMOD */
 147 #define BITS_HPROTDMAW(_X_)                               ( (_X_) << 20 & (BIT(20)|BIT(21)|BIT(22)|BIT(23)) )
 148 #define BITS_HPROTDMAR(_X_)                               ( (_X_) << 16 & (BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
 149 #define BITS_PMU_XPSLEEP_P_R(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 150
 151 /* bits definitions for register REG_LTE_CEVAX_PMU_VERSION_CR */
 152 #define BITS_VERSION_CR(_X_)                              (_X_)
 153
 154 /* bits definitions for register REG_LTE_CEVAX_PMU_SLEEP_STATUS */
 155 #define BITS_PMU_SLEEP_STATUS(_X_)                        (_X_)
 156
 157 /* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL0 */
 158 #define BITS_LTE_ISO_ON_NUM(_X_)                          ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
 159 #define BITS_LTE_ISO_OFF_NUM(_X_)                         ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 160
 161 /* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL1 */
 162 #define BIT_CLK_PWR_LTE_SEL                               ( BIT(10) )
 163 #define BIT_LTE_SLP_POWOFF_AUTO_EN                        ( BIT(9) )
 164 #define BIT_LTE_POW_FORCE_PD                              ( BIT(8) )
 165 #define BITS_DSP_MEM_PD_REG(_X_)                          ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 166
 167 /* bits definitions for register REG_LTE_CEVAX_PMU_POW_CTL2 */
 168 #define BITS_DSP_MEM_PD_EN(_X_)                           ( (_X_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)|BIT(20)|BIT(21)|BIT(22)|BIT(23)|BIT(24)|BIT(25)|BIT(26)) )
 169 #define BITS_PD_LTE_STATUS(_X_)                           ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
 170
 171 /* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN0 */
 172 #define BIT_FFT_OFFLN_HCLKEN                              ( BIT(30) )
 173 #define BIT_FFT_OFFLN_CLKEN                               ( BIT(29) )
 174 #define BIT_FFT_ONLN_HCLKEN                               ( BIT(28) )
 175 #define BIT_FFT_ONLN_CLKEN                                ( BIT(27) )
 176 #define BIT_LTE_DRM_CLKEN                                 ( BIT(24) )
 177 #define BIT_MIMO_HCLKEN                                   ( BIT(23) )
 178 #define BIT_MIMO_CLKEN                                    ( BIT(22) )
 179 #define BIT_PBCH_ACLKEN                                   ( BIT(21) )
 180 #define BIT_PBCH_HCLKEN                                   ( BIT(20) )
 181 #define BIT_PBCH_CLKEN                                    ( BIT(19) )
 182 #define BIT_PCFICH_PHICH_HCLKEN                           ( BIT(18) )
 183 #define BIT_PCFICH_PHICH_CLKEN                            ( BIT(17) )
 184 #define BIT_PDCCH_ACLKEN                                  ( BIT(16) )
 185 #define BIT_PDCCH_HCLKEN                                  ( BIT(15) )
 186 #define BIT_PDCCH_CLKEN                                   ( BIT(14) )
 187 #define BIT_PDSCH_TB_CTL_HCLKEN                           ( BIT(13) )
 188 #define BIT_PDSCH_TB_CTL_CLKEN                            ( BIT(12) )
 189 #define BIT_RXDFE_HCLKEN                                  ( BIT(11) )
 190 #define BIT_SYNC_ACLKEN                                   ( BIT(10) )
 191 #define BIT_SYNC_HCLKEN                                   ( BIT(9) )
 192 #define BIT_SYNC_CLKEN                                    ( BIT(8) )
 193 #define BIT_TBUF_ACLKEN                                   ( BIT(7) )
 194 #define BIT_TBUF_HCLKEN                                   ( BIT(6) )
 195 #define BIT_TBUF_CLKEN                                    ( BIT(5) )
 196 #define BIT_VTB_CLKEN                                     ( BIT(4) )
 197 #define BIT_LTE_PROC_HCLKEN                               ( BIT(0) )
 198
 199 /* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN1 */
 200 #define BIT_LBUSMON2_EB                                   ( BIT(28) )
 201 #define BIT_LBUSMON1_EB                                   ( BIT(27) )
 202 #define BIT_LBUSMON0_EB                                   ( BIT(26) )
 203 #define BIT_HSDL_CLKEN                                    ( BIT(25) )
 204 #define BIT_ULMAC_HCLKEN                                  ( BIT(24) )
 205 #define BIT_TBE_HCLKEN                                    ( BIT(23) )
 206 #define BIT_TBE_CLKEN                                     ( BIT(22) )
 207 #define BIT_RM_HCLKEN                                     ( BIT(21) )
 208 #define BIT_RM_CLKEN                                      ( BIT(20) )
 209 #define BIT_PCM_HCLKEN                                    ( BIT(19) )
 210 #define BIT_PCM_CLKEN                                     ( BIT(18) )
 211 #define BIT_UCM_HCLKEN                                    ( BIT(17) )
 212 #define BIT_UCM_CLKEN                                     ( BIT(16) )
 213 #define BIT_CHE_ACLKEN                                    ( BIT(15) )
 214 #define BIT_CHE_HCLKEN                                    ( BIT(14) )
 215 #define BIT_CHE_SYS_CLKEN                                 ( BIT(13) )
 216 #define BIT_CHEPP_ACLKEN                                  ( BIT(12) )
 217 #define BIT_CHEPP_HCLKEN                                  ( BIT(11) )
 218 #define BIT_CHEPP_SYS_CLKEN                               ( BIT(10) )
 219 #define BIT_DBUF_ACLKEN                                   ( BIT(9) )
 220 #define BIT_DBUF_HCLKEN                                   ( BIT(8) )
 221 #define BIT_DBUF_CLKEN                                    ( BIT(7) )
 222 #define BIT_DFE_CLKEN                                     ( BIT(6) )
 223 #define BIT_FBUF_ACLKEN                                   ( BIT(5) )
 224 #define BIT_FBUF_HCLKEN                                   ( BIT(4) )
 225 #define BIT_FBUF_CLKEN                                    ( BIT(3) )
 226 #define BIT_FEC_ACLKEN                                    ( BIT(2) )
 227 #define BIT_FEC_HCLKEN                                    ( BIT(1) )
 228 #define BIT_FEC_CLKEN                                     ( BIT(0) )
 229
 230 /* bits definitions for register REG_LTE_CEVAX_PMU_ACCCLK_EN2 */
 231
 232 /* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST0 */
 233 #define BITS_SOFT_RST_R(_X_)                              (_X_)
 234
 235 /* bits definitions for register REG_LTE_CEVAX_PMU_SOFT_RST1 */
 236 #define BIT_LTE_PROC_SOFT_RST_RFT                         ( BIT(31) )
 237 #define BIT_HSDL_SOFT_RST                                 ( BIT(30) )
 238 #define BIT_RFSPI_SOFT_RST                                ( BIT(29) )
 239 #define BIT_LTE_PROC_SOFT_RST                             ( BIT(28) )
 240 #define BIT_ULMAC_SOFT_RST                                ( BIT(27) )
 241 #define BIT_PCM_SOFT_RST                                  ( BIT(26) )
 242 #define BIT_UCM_SOFT_RST                                  ( BIT(25) )
 243 #define BIT_TBE_SOFT_RST                                  ( BIT(24) )
 244 #define BIT_RM_SOFT_RST                                   ( BIT(23) )
 245 #define BIT_RFT_SOFT_RST                                  ( BIT(22) )
 246 #define BIT_DFE_SOFT_RST                                  ( BIT(21) )
 247 #define BIT_MIMO_SOFT_RST                                 ( BIT(20) )
 248 #define BIT_ON_LINE_FFT_SOFT_RST                          ( BIT(19) )
 249 #define BIT_OFF_LINE_FFT_SOFT_RST                         ( BIT(18) )
 250 #define BIT_PCFICH_SOFT_RST                               ( BIT(17) )
 251 #define BIT_PDSCH_SOFT_RST                                ( BIT(16) )
 252 #define BIT_DRM_SOFT_RST                                  ( BIT(15) )
 253 #define BIT_VTB_SOFT_RST                                  ( BIT(14) )
 254 #define BIT_FEC_SOFT_RST                                  ( BIT(13) )
 255 #define BIT_CHE_SOFT_RST                                  ( BIT(12) )
 256 #define BIT_CHEPP_SOFT_RST                                ( BIT(11) )
 257 #define BIT_SYNC_SOFT_RST                                 ( BIT(10) )
 258 #define BIT_TBUF_SOFT_RST                                 ( BIT(9) )
 259 #define BIT_DBUF_SOFT_RST                                 ( BIT(8) )
 260 #define BIT_FBUF_SOFT_RST                                 ( BIT(7) )
 261 #define BIT_PDCCH_SOFT_RST                                ( BIT(6) )
 262 #define BIT_PBCH_SOFT_RST                                 ( BIT(5) )
 263 #define BIT_RXADC_SOFT_RST                                ( BIT(4) )
 264 #define BIT_TXDAC_SOFT_RST                                ( BIT(3) )
 265 #define BIT_CAL_SOFT_RST                                  ( BIT(2) )
 266 #define BIT_RTC_SOFT_RST                                  ( BIT(1) )
 267 #define BIT_LTE_SPI_SOFT_RST                              ( BIT(0) )
 268
 269 /* bits definitions for register REG_LTE_CEVAX_PMU_DSP_CKG_SEL */
 270 #define BITS_DSP_CKG_SEL(_X_)                             ( (_X_) & (BIT(0)|BIT(1)) )
 271
 272 /* bits definitions for register REG_LTE_CEVAX_PMU_CLK_DLCH_SEL */
 273 #define BITS_CLK_DLCH_SEL(_X_)                            ( (_X_) & (BIT(0)|BIT(1)) )
 274
 275 /* bits definitions for register REG_LTE_CEVAX_PMU_CLK_ULCH_SEL */
 276 #define BITS_CLK_ULCH_SEL(_X_)                            ( (_X_) & (BIT(0)|BIT(1)) )
 277
 278 /* bits definitions for register REG_LTE_CEVAX_PMU_CLK_RATEM_SEL */
 279 #define BITS_CLK_RATEM_SEL(_X_)                           ( (_X_) & (BIT(0)|BIT(1)) )
 280
 281 /* bits definitions for register REG_LTE_CEVAX_PMU_CLK_LTE_SPI_DIV_SEL */
 282 #define BITS_CLK_LTE_SPI_DIV(_X_)                         ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) )
 283 #define BITS_CLK_LTE_SPI_SEL(_X_)                         ( (_X_) & (BIT(0)|BIT(1)) )
 284
 285 /* bits definitions for register REG_LTE_CEVAX_PMU_CX_CKG_DIV */
 286 #define BITS_CX_CKG_DIV(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
 287
 288 /* bits definitions for register REG_LTE_CEVAX_PMU_XH_CKG_DIV */
 289 #define BITS_XH_CKG_DIV(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
 290
 291 /* bits definitions for register REG_LTE_CEVAX_PMU_XP_CKG_DIV */
 292 #define BITS_XP_CKG_DIV(_X_)                              ( (_X_) & (BIT(0)|BIT(1)|BIT(2)) )
 293
 294 /* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CKG_EN */
 295 #define BIT_DSP_CKG_EN                                    ( BIT(8) )
 296 #define BIT_CX_CKG_EN                                     ( BIT(6) )
 297 #define BIT_XH_CKG_EN                                     ( BIT(5) )
 298 #define BIT_XP_CKG_EN                                     ( BIT(4) )
 299 #define BIT_DMA_CKG_EN                                    ( BIT(0) )
 300
 301 /* bits definitions for register REG_LTE_CEVAX_PMU_LTE_PMU_CLK_EN */
 302 #define BIT_LTE_CEVAX_PMU_CLK_LTE_ANA_4X_EN                   ( BIT(18) )
 303 #define BIT_CLK_LTE_SA_EN                                 ( BIT(17) )
 304 #define BIT_CLK_CXTMR2_EN                                 ( BIT(16) )
 305 #define BIT_CLK_CXTMR1_EN                                 ( BIT(15) )
 306 #define BIT_CLK_CXTMR0_EN                                 ( BIT(14) )
 307 #define BIT_CLK_AXI_EN                                    ( BIT(13) )
 308 #define BIT_CLK_AHB_EN                                    ( BIT(12) )
 309 #define BIT_CLK_DFE_EN                                    ( BIT(11) )
 310 #define BIT_CLK_RFT_EN                                    ( BIT(10) )
 311 #define BIT_CLK_DLCH_EN                                   ( BIT(9) )
 312 #define BIT_CLK_ULCH_EN                                   ( BIT(8) )
 313 #define BIT_CLK_RATEM_EN                                  ( BIT(7) )
 314 #define BIT_CLK_RXADC_EN                                  ( BIT(6) )
 315 #define BIT_CLK_TXDAC_EN                                  ( BIT(5) )
 316 #define BIT_CLK_LTE_ANA_2X_EN                             ( BIT(4) )
 317 #define BIT_CLK_LTE_ANA_1X_EN                             ( BIT(3) )
 318 #define BIT_CLK_CAL_EN                                    ( BIT(2) )
 319 #define BIT_CLK_RTC_EN                                    ( BIT(1) )
 320 #define BIT_CLK_LTE_SPI_EN                                ( BIT(0) )
 321
 322 /* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL0 */
 323 #define BITS_CLK_UART1_DIV(_X_)                           ( (_X_) << 7 & (BIT(7)|BIT(8)|BIT(9)) )
 324 #define BITS_CLK_UART1_SEL(_X_)                           ( (_X_) << 5 & (BIT(5)|BIT(6)) )
 325 #define BITS_CLK_UART0_DIV(_X_)                           ( (_X_) << 2 & (BIT(2)|BIT(3)|BIT(4)) )
 326 #define BITS_CLK_UART0_SEL(_X_)                           ( (_X_) & (BIT(0)|BIT(1)) )
 327
 328 /* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL1 */
 329
 330 /* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR0_SEL */
 331 #define BITS_CLK_CXTMR0_SEL(_X_)                          ( (_X_) & (BIT(0)|BIT(1)) )
 332
 333 /* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR1_SEL */
 334 #define BITS_CLK_CXTMR1_SEL(_X_)                          ( (_X_) & (BIT(0)|BIT(1)) )
 335
 336 /* bits definitions for register REG_LTE_CEVAX_PMU_CLK_CXTMR2_SEL */
 337 #define BITS_CLK_CXTMR2_SEL(_X_)                          ( (_X_) & (BIT(0)|BIT(1)) )
 338
 339 /* bits definitions for register REG_LTE_CEVAX_PMU_APB_CLK_SEL2 */
 340
 341 /* bits definitions for register REG_LTE_CEVAX_PMU_MEM_LP_CTRL */
 342 #define BITS_MEM_LP_CTRL(_X_)                             (_X_)
 343
 344 /* bits definitions for register REG_LTE_CEVAX_PMU_AXI_MON_CTRL */
 345 #define BIT_AXI_MON_WAIT_EB                               ( BIT(21) )
 346 #define BIT_AXI_MON_CLKEN_EB                              ( BIT(20) )
 347 #define BITS_AXI_MONITOR_STATUS(_X_)                      ( (_X_) & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)|BIT(16)|BIT(17)|BIT(18)|BIT(19)) )
 348
 349 /* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG0 */
 350 #define BITS_RES_REG0(_X_)                                (_X_)
 351
 352 /* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG1 */
 353 #define BITS_RES_REG1(_X_)                                (_X_)
 354
 355 /* bits definitions for register REG_LTE_CEVAX_PMU_RES_REG2 */
 356 #define BITS_RES_REG2(_X_)                                (_X_)
 357
 358 #endif