2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 *************************************************
15 * Automatically generated C header: do not edit *
16 *************************************************
19 #ifndef __ANA_REGS_GLB_H__
20 #define __ANA_REGS_GLB_H__
22 #ifndef __SCI_GLB_REGS_H__
23 #error "Don't include this file directly, include <mach/sci_glb_regs.h>"
28 /* registers definitions for controller ANA_REGS_GLB */
29 #define ANA_REG_GLB_ARM_MODULE_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0000)
30 #define ANA_REG_GLB_ARM_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0004)
31 #define ANA_REG_GLB_RTC_CLK_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0008)
32 #define ANA_REG_GLB_ARM_RST SCI_ADDR(ANA_REGS_GLB_BASE, 0x000C)
33 #define ANA_REG_GLB_LDO_DCDC_PD_RTCSET SCI_ADDR(ANA_REGS_GLB_BASE, 0x0010)
34 #define ANA_REG_GLB_LDO_DCDC_PD_RTCCLR SCI_ADDR(ANA_REGS_GLB_BASE, 0x0014)
35 #define ANA_REG_GLB_RTC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0018)
36 #define ANA_REG_GLB_LDO_PD_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x001C)
37 #define ANA_REG_GLB_LDO_V_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0020)
38 #define ANA_REG_GLB_LDO_V_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0024)
39 #define ANA_REG_GLB_LDO_V_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0028)
40 #define ANA_REG_GLB_LDO_CAL_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x002C)
41 #define ANA_REG_GLB_LDO_CAL_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0030)
42 #define ANA_REG_GLB_LDO_CAL_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0034)
43 #define ANA_REG_GLB_LDO_CAL_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0038)
44 #define ANA_REG_GLB_LDO_CAL_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x003C)
45 #define ANA_REG_GLB_LDO_CAL_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0040)
46 #define ANA_REG_GLB_LDO_CAL_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044)
47 #define ANA_REG_GLB_AUXAD_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0048)
48 #define ANA_REG_GLB_DCDC_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x004C)
49 #define ANA_REG_GLB_DCDC_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0050)
50 #define ANA_REG_GLB_DCDC_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0054)
51 #define ANA_REG_GLB_DCDC_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0058)
52 #define ANA_REG_GLB_DCDC_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x005C)
53 #define ANA_REG_GLB_DCDC_CTRL5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0060)
54 #define ANA_REG_GLB_DCDC_CTRL6 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0064)
55 #define ANA_REG_GLB_DDR2_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0068)
56 #define ANA_REG_GLB_SLP_WAIT_DCDCARM SCI_ADDR(ANA_REGS_GLB_BASE, 0x006C)
57 #define ANA_REG_GLB_LDO1828_XTL_CTL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0070)
58 #define ANA_REG_GLB_LDO_SLP_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0074)
59 #define ANA_REG_GLB_LDO_SLP_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0078)
60 #define ANA_REG_GLB_LDO_SLP_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x007C)
61 #define ANA_REG_GLB_LDO_SLP_CTRL3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0080)
62 #define ANA_REG_GLB_AUD_SLP_CTRL4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0084)
63 #define ANA_REG_GLB_DCDC_SLP_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0088)
64 #define ANA_REG_GLB_XTL_WAIT_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x008C)
65 #define ANA_REG_GLB_FLASH_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0090)
66 #define ANA_REG_GLB_WHTLED_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0094)
67 #define ANA_REG_GLB_WHTLED_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0098)
68 #define ANA_REG_GLB_WHTLED_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x009C)
69 #define ANA_REG_GLB_ANA_DRV_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A0)
70 #define ANA_REG_GLB_VIBR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A4)
71 #define ANA_REG_GLB_VIBR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00A8)
72 #define ANA_REG_GLB_VIBR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00AC)
73 #define ANA_REG_GLB_VIBR_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B0)
74 #define ANA_REG_GLB_AUDIO_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B4)
75 #define ANA_REG_GLB_CHGR_CTRL0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00B8)
76 #define ANA_REG_GLB_CHGR_CTRL1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00BC)
77 #define ANA_REG_GLB_CHGR_CTRL2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C0)
78 #define ANA_REG_GLB_CHGR_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C4)
79 #define ANA_REG_GLB_ANA_MIXED_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00C8)
80 #define ANA_REG_GLB_PWR_XTL_EN0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00CC)
81 #define ANA_REG_GLB_PWR_XTL_EN1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D0)
82 #define ANA_REG_GLB_PWR_XTL_EN2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D4)
83 #define ANA_REG_GLB_PWR_XTL_EN3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00D8)
84 #define ANA_REG_GLB_PWR_XTL_EN4 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00DC)
85 #define ANA_REG_GLB_PWR_XTL_EN5 SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E0)
86 #define ANA_REG_GLB_ANA_STATUS SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E4)
87 #define ANA_REG_GLB_POR_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00E8)
88 #define ANA_REG_GLB_WDG_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00EC)
89 #define ANA_REG_GLB_POR_PIN_RST_MONITOR SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F0)
90 #define ANA_REG_GLB_POR_SRC_FLAG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F4)
91 #define ANA_REG_GLB_POR_7S_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x00F8)
92 #define ANA_REG_GLB_INT_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x00FC)
93 #define ANA_REG_GLB_GPI_DEBUG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0100)
94 #define ANA_REG_GLB_HWRST_RTC SCI_ADDR(ANA_REGS_GLB_BASE, 0x0104)
95 #define ANA_REG_GLB_CHIP_ID_LOW SCI_ADDR(ANA_REGS_GLB_BASE, 0x0108)
96 #define ANA_REG_GLB_CHIP_ID_HIGH SCI_ADDR(ANA_REGS_GLB_BASE, 0x010C)
97 #define ANA_REG_GLB_ARM_MF_REG SCI_ADDR(ANA_REGS_GLB_BASE, 0x0110)
98 #define ANA_REG_GLB_AFUSE_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0114)
99 #define ANA_REG_GLB_AFUSE_OUT0 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0118)
100 #define ANA_REG_GLB_AFUSE_OUT1 SCI_ADDR(ANA_REGS_GLB_BASE, 0x011C)
101 #define ANA_REG_GLB_AFUSE_OUT2 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0120)
102 #define ANA_REG_GLB_AFUSE_OUT3 SCI_ADDR(ANA_REGS_GLB_BASE, 0x0124)
103 #define ANA_REG_GLB_ARCH_EN SCI_ADDR(ANA_REGS_GLB_BASE, 0x0128)
104 #define ANA_REG_GLB_MCU_WR_PROT_VALUE SCI_ADDR(ANA_REGS_GLB_BASE, 0x012C)
105 #define ANA_REG_GLB_MP_MISC_CTRL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0148)
106 #define ANA_REG_GLB_DCDC_CORE_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0160)
107 #define ANA_REG_GLB_DCDC_ARM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0164)
108 #define ANA_REG_GLB_DCDC_MEM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0168)
109 #define ANA_REG_GLB_DCDC_GEN_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x016C)
110 #define ANA_REG_GLB_DCDC_WRF_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0170)
111 #define ANA_REG_GLB_DCDC_WPA_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x0174)
112 #define ANA_REG_GLB_DCDC_WPA_DCM_ADI SCI_ADDR(ANA_REGS_GLB_BASE, 0x017C)
113 #define ANA_REG_GLB_LDO_CAL_SEL SCI_ADDR(ANA_REGS_GLB_BASE, 0x0044)
115 /* bits definitions for register ANA_REG_GLB_ARM_MODULE_EN */
116 #define BIT_ANA_THM_EN ( BIT(12) )
117 #define BIT_ANA_BLTC_EN ( BIT(10) )
118 #define BIT_ANA_PINREG_EN ( BIT(9) )
119 #define BIT_ANA_FGU_EN ( BIT(8) )
120 #define BIT_ANA_GPIO_EN ( BIT(7) )
121 #define BIT_ANA_ADC_EN ( BIT(6) )
122 #define BIT_ANA_HDT_EN ( BIT(5) )
123 #define BIT_ANA_AUD_EN ( BIT(4) )
124 #define BIT_ANA_EIC_EN ( BIT(3) )
125 #define BIT_ANA_WDG_EN ( BIT(2) )
126 #define BIT_ANA_RTC_EN ( BIT(1) )
128 /* bits definitions for register ANA_REG_GLB_ARM_CLK_EN */
129 #define BIT_CLK_AUXAD_EN ( BIT(9) )
130 #define BIT_CLK_AUXADC_EN ( BIT(8) )
131 #define BIT_CLK_AUD_HID_EN ( BIT(5) )
132 #define BIT_CLK_AUD_HBD_EN ( BIT(4) )
133 #define BIT_CLK_AUD_LOOP_EN ( BIT(3) )
134 #define BIT_CLK_AUD_6P5M_EN ( BIT(2) )
135 #define BIT_CLK_AUDIF_EN ( BIT(1) )
137 /* bits definitions for register ANA_REG_GLB_RTC_CLK_EN */
138 #define BIT_RTC_FLASH_EN ( BIT(13) )
139 #define BIT_RTC_THMA_AUTO_EN ( BIT(12) )
140 #define BIT_RTC_THMA_EN ( BIT(11) )
141 #define BIT_RTC_THM_EN ( BIT(10) )
142 #define BIT_RTC_BLTC_EN ( BIT(8) )
143 #define BIT_RTC_FGU_EN ( BIT(7) )
144 #define BIT_RTC_FGUA_EN ( BIT(6) )
145 #define BIT_RTC_VIBR_EN ( BIT(5) )
146 #define BIT_RTC_AUD_EN ( BIT(4) )
147 #define BIT_RTC_EIC_EN ( BIT(3) )
148 #define BIT_RTC_WDG_EN ( BIT(2) )
149 #define BIT_RTC_RTC_EN ( BIT(1) )
150 #define BIT_RTC_ARCH_EN ( BIT(0) )
152 /* bits definitions for register ANA_REG_GLB_ARM_RST */
153 #define BIT_ANA_THMA_SOFT_RST ( BIT(14) )
154 #define BIT_ANA_THM_SOFT_RST ( BIT(13) )
155 #define BIT_ANA_AUD_32K_SOFT_RST ( BIT(12) )
156 #define BIT_ANA_AUDTX_SOFT_RST ( BIT(11) )
157 #define BIT_ANA_AUDRX_SOFT_RST ( BIT(10) )
158 #define BIT_ANA_AUD_SOFT_RST ( BIT(9) )
159 #define BIT_ANA_AUD_HDT_SOFT_RST ( BIT(8) )
160 #define BIT_ANA_GPIO_SOFT_RST ( BIT(7) )
161 #define BIT_ANA_ADC_SOFT_RST ( BIT(6) )
162 #define BIT_ANA_PWM0_SOFT_RST ( BIT(5) )
163 #define BIT_ANA_FGU_SOFT_RST ( BIT(4) )
164 #define BIT_ANA_EIC_SOFT_RST ( BIT(3) )
165 #define BIT_ANA_WDG_SOFT_RST ( BIT(2) )
166 #define BIT_ANA_RTC_SOFT_RST ( BIT(1) )
167 #define BIT_ANA_BLTC_SOFT_RST ( BIT(0) )
169 /* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCSET */
170 #define BIT_DCDC_OTP_PD_RTCSET ( BIT(14) )
171 #define BIT_DCDC_WRF_PD_RTCSET ( BIT(13) )
172 #define BIT_DCDC_GEN_PD_RTCSET ( BIT(12) )
173 #define BIT_DCDC_MEM_PD_RTCSET ( BIT(11) )
174 #define BIT_DCDC_ARM_PD_RTCSET ( BIT(10) )
175 #define BIT_DCDC_CORE_PD_RTCSET ( BIT(9) )
176 #define BIT_LDO_EMMCCORE_PD_RTCSET ( BIT(8) )
177 #define BIT_LDO_EMMCIO_PD_RTCSET ( BIT(7) )
178 #define BIT_LDO_RF2_PD_RTCSET ( BIT(6) )
179 #define BIT_LDO_RF1_PD_RTCSET ( BIT(5) )
180 #define BIT_LDO_RF0_PD_RTCSET ( BIT(4) )
181 #define BIT_LDO_VDD25_PD_RTCSET ( BIT(3) )
182 #define BIT_LDO_VDD28_PD_RTCSET ( BIT(2) )
183 #define BIT_LDO_VDD18_PD_RTCSET ( BIT(1) )
184 #define BIT_BG_PD_RTCSET ( BIT(0) )
186 /* bits definitions for register ANA_REG_GLB_LDO_DCDC_PD_RTCCLR */
187 #define BIT_DCDC_OTP_PD_RTCCLR ( BIT(14) )
188 #define BIT_DCDC_WRF_PD_RTCCLR ( BIT(13) )
189 #define BIT_DCDC_GEN_PD_RTCCLR ( BIT(12) )
190 #define BIT_DCDC_MEM_PD_RTCCLR ( BIT(11) )
191 #define BIT_DCDC_ARM_PD_RTCCLR ( BIT(10) )
192 #define BIT_DCDC_CORE_PD_RTCCLR ( BIT(9) )
193 #define BIT_LDO_EMMCCORE_PD_RTCCLR ( BIT(8) )
194 #define BIT_LDO_EMMCIO_PD_RTCCLR ( BIT(7) )
195 #define BIT_LDO_RF2_PD_RTCCLR ( BIT(6) )
196 #define BIT_LDO_RF1_PD_RTCCLR ( BIT(5) )
197 #define BIT_LDO_RF0_PD_RTCCLR ( BIT(4) )
198 #define BIT_LDO_VDD25_PD_RTCCLR ( BIT(3) )
199 #define BIT_LDO_VDD28_PD_RTCCLR ( BIT(2) )
200 #define BIT_LDO_VDD18_PD_RTCCLR ( BIT(1) )
201 #define BIT_BG_PD_RTCCLR ( BIT(0) )
203 /* bits definitions for register ANA_REG_GLB_RTC_CTRL */
204 #define BITS_XOSC32K_CTL_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
205 #define BIT_XOSC32K_CTL_B3_RTCCLR ( BIT(7) )
206 #define BIT_XOSC32K_CTL_B2_RTCCLR ( BIT(6) )
207 #define BIT_XOSC32K_CTL_B1_RTCCLR ( BIT(5) )
208 #define BIT_XOSC32K_CTL_B0_RTCCLR ( BIT(4) )
209 #define BIT_XOSC32K_CTL_B3_RTCSET ( BIT(3) )
210 #define BIT_XOSC32K_CTL_B2_RTCSET ( BIT(2) )
211 #define BIT_XOSC32K_CTL_B1_RTCSET ( BIT(1) )
212 #define BIT_XOSC32K_CTL_B0_RTCSET ( BIT(0) )
214 /* bits definitions for register ANA_REG_GLB_LDO_PD_CTRL */
215 #define BIT_LDO_LPREF_PD_SW ( BIT(12) )
216 #define BIT_DCDC_WPA_PD ( BIT(11) )
217 #define BIT_LDO_CLSG_PD ( BIT(10) )
218 #define BIT_LDO_USB_PD ( BIT(9) )
219 #define BIT_LDO_CAMMOT_PD ( BIT(8) )
220 #define BIT_LDO_CAMIO_PD ( BIT(7) )
221 #define BIT_LDO_CAMD_PD ( BIT(6) )
222 #define BIT_LDO_CAMA_PD ( BIT(5) )
223 #define BIT_LDO_SIM2_PD ( BIT(4) )
224 #define BIT_LDO_SIM1_PD ( BIT(3) )
225 #define BIT_LDO_SIM0_PD ( BIT(2) )
226 #define BIT_LDO_SD_PD ( BIT(1) )
227 #define BIT_LDO_AVDD18_PD ( BIT(0) )
229 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL0 */
230 #define BITS_LDO_EMMCCORE_V(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
231 #define BITS_LDO_EMMCIO_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
232 #define BITS_LDO_RF2_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
233 #define BITS_LDO_RF1_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
234 #define BITS_LDO_RF0_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) )
235 #define BITS_LDO_VDD25_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
236 #define BITS_LDO_VDD28_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
237 #define BITS_LDO_VDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
239 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL1 */
240 #define BITS_LDO_SIM2_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
241 #define BITS_LDO_SIM1_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) )
242 #define BITS_LDO_SIM0_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
243 #define BITS_LDO_SD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
244 #define BITS_LDO_AVDD18_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
246 /* bits definitions for register ANA_REG_GLB_LDO_V_CTRL2 */
247 #define BITS_VBATBK_RES(_x_) ( (_x_) << 14 & (BIT(14)|BIT(15)) )
248 #define BITS_VBATBK_V(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)) )
249 #define BITS_LDO_CLSG_V(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)) )
250 #define BITS_LDO_USB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
251 #define BITS_LDO_CAMMOT_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)) )
252 #define BITS_LDO_CAMIO_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
253 #define BITS_LDO_CAMD_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
254 #define BITS_LDO_CAMA_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
256 /* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL0 */
257 #define BITS_LDO_VDD25_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
258 #define BITS_LDO_VDD28_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
259 #define BITS_LDO_VDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
261 /* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL1 */
262 #define BITS_LDO_RF2_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
263 #define BITS_LDO_RF1_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
264 #define BITS_LDO_RF0_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
266 /* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL2 */
267 #define BITS_LDO_USB_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
268 #define BITS_LDO_EMMCCORE_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
269 #define BITS_LDO_EMMCIO_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
271 /* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL3 */
272 #define BITS_LDO_SD_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
273 #define BITS_LDO_AVDD18_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
275 /* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL4 */
276 #define BITS_LDO_CAMA_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
277 #define BITS_LDO_SIM2_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
278 #define BITS_LDO_SIM_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
280 /* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL5 */
281 #define BITS_LDO_CAMMOT_CAL(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
282 #define BITS_LDO_CAMIO_CAL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
283 #define BITS_LDO_CAMD_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
285 /* bits definitions for register ANA_REG_GLB_LDO_CAL_CTRL6 */
286 #define BITS_LDOA_CAL_SEL(_x_) ( (_x_) << 11 & (BIT(11)|BIT(12)|BIT(13)) )
287 #define BITS_LDOD_CAL_SEL(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
288 #define BITS_LDODCDC_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
289 #define BITS_LDO_CLSG_CAL(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
291 /* bits definitions for register ANA_REG_GLB_AUXAD_CTL */
292 #define BIT_AUXAD_CURRENTSEN_EN ( BIT(6) )
293 #define BIT_AUXAD_CURRENTSEL ( BIT(5) )
294 #define BITS_AUXAD_CURRENT_IBS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
296 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL0 */
297 #define BIT_DCDC_CORE_LP_EN ( BIT(15) )
298 #define BIT_DCDC_CORE_CL_CTRL ( BIT(14) )
299 #define BITS_DCDC_CORE_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
300 #define BIT_DCDC_CORE_PFM ( BIT(9) )
301 #define BIT_DCDC_CORE_DCM ( BIT(8) )
302 #define BIT_DCDC_ARM_LP_EN ( BIT(7) )
303 #define BIT_DCDC_ARM_CL_CTRL ( BIT(6) )
304 #define BITS_DCDC_ARM_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
305 #define BIT_DCDC_ARM_PFM ( BIT(1) )
306 #define BIT_DCDC_ARM_DCM ( BIT(0) )
308 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL1 */
309 #define BIT_DCDC_MEM_LP_EN ( BIT(15) )
310 #define BIT_DCDC_MEM_CL_CTRL ( BIT(14) )
311 #define BITS_DCDC_MEM_PDRSLOW(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
312 #define BIT_DCDC_MEM_PFM ( BIT(9) )
313 #define BIT_DCDC_MEM_DCM ( BIT(8) )
314 #define BIT_DCDC_GEN_LP_EN ( BIT(7) )
315 #define BIT_DCDC_GEN_CL_CTRL ( BIT(6) )
316 #define BITS_DCDC_GEN_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
317 #define BIT_DCDC_GEN_PFM ( BIT(1) )
318 #define BIT_DCDC_GEN_DCM ( BIT(0) )
320 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL2 */
321 #define BIT_DCDC_BG_LP_EN ( BIT(15) )
322 #define BIT_DCDC_OTP_CHIP_PD_FLAG_CLR ( BIT(14) )
323 #define BIT_DCDC_OTP_CHIP_PD_FLAG ( BIT(13) )
324 #define BIT_DCDC_OTP_AUTO_PD_EN ( BIT(12) )
325 #define BIT_DCDC_OTP_VBEOP ( BIT(11) )
326 #define BITS_DCDC_OTP_S(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)) )
327 #define BIT_DCDC_WRF_LP_EN ( BIT(7) )
328 #define BIT_DCDC_WRF_CL_CTRL ( BIT(6) )
329 #define BITS_DCDC_WRF_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
330 #define BIT_DCDC_WRF_PFM ( BIT(1) )
331 #define BIT_DCDC_WRF_DCM ( BIT(0) )
333 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL3 */
334 #define BIT_DCDC_WPA_LP_EN ( BIT(8) )
335 #define BIT_DCDC_WPA_CL_CTRL ( BIT(7) )
336 #define BIT_DCDC_WPA_ZXOP ( BIT(6) )
337 #define BITS_DCDC_WPA_PDRSLOW(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
338 #define BIT_DCDC_WPA_PFM ( BIT(1) )
339 #define BIT_DCDC_WPA_APTEN ( BIT(0) )
341 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL4 */
342 #define BIT_DCDC_CORE_OSCSYCEN_SW ( BIT(15) )
343 #define BIT_DCDC_CORE_OSCSYCEN_HW_EN ( BIT(14) )
344 #define BIT_DCDC_CORE_OSCSYC_DIV_EN ( BIT(13) )
345 #define BITS_DCDC_CORE_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
346 #define BIT_DCDC_ARM_OSCSYCEN_SW ( BIT(7) )
347 #define BIT_DCDC_ARM_OSCSYCEN_HW_EN ( BIT(6) )
348 #define BIT_DCDC_ARM_OSCSYC_DIV_EN ( BIT(5) )
349 #define BITS_DCDC_ARM_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
351 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL5 */
352 #define BIT_DCDC_MEM_OSCSYCEN_SW ( BIT(15) )
353 #define BIT_DCDC_MEM_OSCSYCEN_HW_EN ( BIT(14) )
354 #define BIT_DCDC_MEM_OSCSYC_DIV_EN ( BIT(13) )
355 #define BITS_DCDC_MEM_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
356 #define BIT_DCDC_GEN_OSCSYCEN_SW ( BIT(7) )
357 #define BIT_DCDC_GEN_OSCSYCEN_HW_EN ( BIT(6) )
358 #define BIT_DCDC_GEN_OSCSYC_DIV_EN ( BIT(5) )
359 #define BITS_DCDC_GEN_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
361 /* bits definitions for register ANA_REG_GLB_DCDC_CTRL6 */
362 #define BIT_DCDC_WPA_OSCSYCEN_SW ( BIT(15) )
363 #define BIT_DCDC_WPA_OSCSYCEN_HW_EN ( BIT(14) )
364 #define BIT_DCDC_WPA_OSCSYC_DIV_EN ( BIT(13) )
365 #define BITS_DCDC_WPA_OSCSYC_DIV(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
366 #define BIT_DCDC_WRF_OSCSYCEN_SW ( BIT(7) )
367 #define BIT_DCDC_WRF_OSCSYCEN_HW_EN ( BIT(6) )
368 #define BIT_DCDC_WRF_OSCSYC_DIV_EN ( BIT(5) )
369 #define BITS_DCDC_WRF_OSCSYC_DIV(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
371 /* bits definitions for register ANA_REG_GLB_DDR2_CTRL */
372 #define BIT_DDR2_BUF_PD_HW ( BIT(9) )
373 #define BITS_DDR2_BUF_S_DS(_x_) ( (_x_) << 7 & (BIT(7)|BIT(8)) )
374 #define BITS_DDR2_BUF_CHNS_DS(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) )
375 #define BIT_DDR2_BUF_PD ( BIT(4) )
376 #define BITS_DDR2_BUF_S(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
377 #define BITS_DDR2_BUF_CHNS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
379 /* bits definitions for register ANA_REG_GLB_SLP_WAIT_DCDCARM */
380 #define BITS_SLP_IN_WAIT_DCDCARM(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
381 #define BITS_SLP_OUT_WAIT_DCDCARM(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
383 /* bits definitions for register ANA_REG_GLB_LDO1828_XTL_CTL */
384 #define BIT_LDO_VDD18_EXT_XTL2_EN ( BIT(11) )
385 #define BIT_LDO_VDD18_EXT_XTL1_EN ( BIT(10) )
386 #define BIT_LDO_VDD18_EXT_XTL0_EN ( BIT(9) )
387 #define BIT_LDO_VDD18_XTL2_EN ( BIT(8) )
388 #define BIT_LDO_VDD18_XTL1_EN ( BIT(7) )
389 #define BIT_LDO_VDD18_XTL0_EN ( BIT(6) )
390 #define BIT_LDO_VDD28_EXT_XTL2_EN ( BIT(5) )
391 #define BIT_LDO_VDD28_EXT_XTL1_EN ( BIT(4) )
392 #define BIT_LDO_VDD28_EXT_XTL0_EN ( BIT(3) )
393 #define BIT_LDO_VDD28_XTL2_EN ( BIT(2) )
394 #define BIT_LDO_VDD28_XTL1_EN ( BIT(1) )
395 #define BIT_LDO_VDD28_XTL0_EN ( BIT(0) )
397 /* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL0 */
398 #define BIT_SLP_IO_EN ( BIT(15) )
399 #define BIT_SLP_DCDC_OTP_PD_EN ( BIT(13) )
400 #define BIT_SLP_DCDCGEN_PD_EN ( BIT(12) )
401 #define BIT_SLP_DCDCWPA_PD_EN ( BIT(11) )
402 #define BIT_SLP_DCDCWRF_PD_EN ( BIT(10) )
403 #define BIT_SLP_DCDCARM_PD_EN ( BIT(9) )
404 #define BIT_SLP_LDOEMMCCORE_PD_EN ( BIT(7) )
405 #define BIT_SLP_LDOEMMCIO_PD_EN ( BIT(6) )
406 #define BIT_SLP_LDORF2_PD_EN ( BIT(5) )
407 #define BIT_SLP_LDORF1_PD_EN ( BIT(4) )
408 #define BIT_SLP_LDORF0_PD_EN ( BIT(3) )
409 #define BIT_SLP_LDOVDD25_PD_EN ( BIT(2) )
410 #define BIT_SLP_LDOVDD28_PD_EN ( BIT(1) )
411 #define BIT_SLP_LDOVDD18_PD_EN ( BIT(0) )
413 /* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL1 */
414 #define BIT_SLP_LDO_PD_EN ( BIT(12) )
415 #define BIT_SLP_LDOLPREF_PD_EN ( BIT(11) )
416 #define BIT_SLP_LDOCLSG_PD_EN ( BIT(10) )
417 #define BIT_SLP_LDOUSB_PD_EN ( BIT(9) )
418 #define BIT_SLP_LDOCAMMOT_PD_EN ( BIT(8) )
419 #define BIT_SLP_LDOCAMIO_PD_EN ( BIT(7) )
420 #define BIT_SLP_LDOCAMD_PD_EN ( BIT(6) )
421 #define BIT_SLP_LDOCAMA_PD_EN ( BIT(5) )
422 #define BIT_SLP_LDOSIM2_PD_EN ( BIT(4) )
423 #define BIT_SLP_LDOSIM1_PD_EN ( BIT(3) )
424 #define BIT_SLP_LDOSIM0_PD_EN ( BIT(2) )
425 #define BIT_SLP_LDOSD_PD_EN ( BIT(1) )
426 #define BIT_SLP_LDOAVDD18_PD_EN ( BIT(0) )
428 /* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL2 */
429 #define BIT_SLP_DCDC_BG_LP_EN ( BIT(15) )
430 #define BIT_SLP_DCDCCORE_LP_EN ( BIT(11) )
431 #define BIT_SLP_DCDCMEM_LP_EN ( BIT(10) )
432 #define BIT_SLP_DCDCARM_LP_EN ( BIT(9) )
433 #define BIT_SLP_DCDCGEN_LP_EN ( BIT(8) )
434 #define BIT_SLP_DCDCWPA_LP_EN ( BIT(6) )
435 #define BIT_SLP_DCDCWRF_LP_EN ( BIT(5) )
436 #define BIT_SLP_LDOEMMCCORE_LP_EN ( BIT(4) )
437 #define BIT_SLP_LDOEMMCIO_LP_EN ( BIT(3) )
438 #define BIT_SLP_LDORF2_LP_EN ( BIT(2) )
439 #define BIT_SLP_LDORF1_LP_EN ( BIT(1) )
440 #define BIT_SLP_LDORF0_LP_EN ( BIT(0) )
442 /* bits definitions for register ANA_REG_GLB_LDO_SLP_CTRL3 */
443 #define BIT_SLP_BG_LP_EN ( BIT(15) )
444 #define BIT_SLP_LDOVDD25_LP_EN ( BIT(13) )
445 #define BIT_SLP_LDOVDD28_LP_EN ( BIT(12) )
446 #define BIT_SLP_LDOVDD18_LP_EN ( BIT(11) )
447 #define BIT_SLP_LDOCLSG_LP_EN ( BIT(10) )
448 #define BIT_SLP_LDOUSB_LP_EN ( BIT(9) )
449 #define BIT_SLP_LDOCAMMOT_LP_EN ( BIT(8) )
450 #define BIT_SLP_LDOCAMIO_LP_EN ( BIT(7) )
451 #define BIT_SLP_LDOCAMD_LP_EN ( BIT(6) )
452 #define BIT_SLP_LDOCAMA_LP_EN ( BIT(5) )
453 #define BIT_SLP_LDOSIM2_LP_EN ( BIT(4) )
454 #define BIT_SLP_LDOSIM1_LP_EN ( BIT(3) )
455 #define BIT_SLP_LDOSIM0_LP_EN ( BIT(2) )
456 #define BIT_SLP_LDOSD_LP_EN ( BIT(1) )
457 #define BIT_SLP_LDOAVDD18_LP_EN ( BIT(0) )
459 /* bits definitions for register ANA_REG_GLB_AUD_SLP_CTRL4 */
460 #define BIT_SLP_AUD_PA_SW_PD_EN ( BIT(15) )
461 #define BIT_SLP_AUD_PA_LDO_PD_EN ( BIT(14) )
462 #define BIT_SLP_AUD_PA_PD_EN ( BIT(13) )
463 #define BIT_SLP_AUD_OVP_PD_PD_EN ( BIT(9) )
464 #define BIT_SLP_AUD_OVP_LDO_PD_EN ( BIT(8) )
465 #define BIT_SLP_AUD_VB_PD_EN ( BIT(7) )
466 #define BIT_SLP_AUD_VBO_PD_EN ( BIT(6) )
467 #define BIT_SLP_AUD_HEADMICBIAS_PD_EN ( BIT(5) )
468 #define BIT_SLP_AUD_MICBIAS_HV_PD_EN ( BIT(2) )
469 #define BIT_SLP_AUD_HEADMIC_PD_EN ( BIT(1) )
470 #define BIT_SLP_AUD_PMUR1_PD_EN ( BIT(0) )
472 /* bits definitions for register ANA_REG_GLB_DCDC_SLP_CTRL */
473 #define BITS_SLP_DCDCCORE_VOL_DROP_CNT(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
474 #define BITS_DCDC_CORE_CTL_DS(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
476 /* bits definitions for register ANA_REG_GLB_XTL_WAIT_CTRL */
477 #define BIT_SLP_XTLBUF_PD_EN ( BIT(9) )
478 #define BIT_XTL_EN ( BIT(8) )
479 #define BITS_XTL_WAIT(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
481 /* bits definitions for register ANA_REG_GLB_FLASH_CTRL */
482 #define BIT_FLASH_PON ( BIT(15) )
483 #define BIT_FLASH_V_HW_EN ( BIT(6) )
484 #define BITS_FLASH_V_HW_STEP(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
485 #define BITS_FLASH_V_SW(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)) )
487 /* bits definitions for register ANA_REG_GLB_WHTLED_CTRL0 */
488 #define BIT_WHTLED_PD_STS ( BIT(15) )
489 #define BITS_WHTLED_DC(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
490 #define BIT_WHTLED_BOOST_EN ( BIT(8) )
491 #define BIT_WHTLED_SERIES_EN ( BIT(7) )
492 #define BITS_WHTLED_V(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
493 #define BIT_WHTLED_PD ( BIT(0) )
495 /* bits definitions for register ANA_REG_GLB_WHTLED_CTRL1 */
496 #define BIT_LCM_CABC_PWM_SEL ( BIT(15) )
497 #define BIT_RTC_PWM0_EN ( BIT(14) )
498 #define BIT_PWM0_EN ( BIT(13) )
499 #define BITS_WHTLED_ISET(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
500 #define BITS_WHTLED_FRE_AD(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)|BIT(4)) )
501 #define BITS_WHTLED_CLMIT_OP(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)) )
503 /* bits definitions for register ANA_REG_GLB_WHTLED_CTRL2 */
504 #define BIT_WHTLED_DIMMING_SEL ( BIT(15) )
505 #define BIT_WHTLED_PD_SEL ( BIT(14) )
506 #define BIT_WHTLED_DIS_OVST ( BIT(13) )
507 #define BIT_WHTLED_DIM_SEL ( BIT(12) )
508 #define BIT_WHTLED_DE_BIAS ( BIT(11) )
509 #define BIT_WHTLED_BUFF_SHT ( BIT(10) )
510 #define BITS_WHTLED_STB_OP(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)) )
511 #define BIT_WHTLED_CAP_OPTION ( BIT(7) )
512 #define BIT_WHTLED_OVP_DIS ( BIT(6) )
513 #define BITS_WHTLED_REF_DC(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
515 /* bits definitions for register ANA_REG_GLB_ANA_DRV_CTRL */
516 #define BIT_SLP_RGB_PD_EN ( BIT(14) )
517 #define BIT_RGB_PD_HW_EN ( BIT(13) )
518 #define BITS_RGB_V(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)) )
519 #define BITS_KPLED_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
520 #define BIT_RGB_PD_SW ( BIT(2) )
521 #define BIT_KPLED_PD ( BIT(1) )
522 #define BIT_KPLED_PD_STS ( BIT(0) )
524 /* bits definitions for register ANA_REG_GLB_VIBR_CTRL0 */
525 #define BITS_VIBR_STABLE_V_HW(_x_) ( (_x_) << 12 & (BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
526 #define BITS_VIBR_INIT_V_HW(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
527 #define BITS_VIBR_V_SW(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
528 #define BIT_VIBR_PON ( BIT(2) )
529 #define BIT_VIBR_SW_EN ( BIT(1) )
531 /* bits definitions for register ANA_REG_GLB_VIBR_CTRL1 */
532 #define BITS_VIBR_V_CONVERT_CNT_HW(_x_) ( (_x_) << 0 )
534 /* bits definitions for register ANA_REG_GLB_VIBR_CTRL2 */
535 #define BIT_VIBR_PWR_ON_STS ( BIT(15) )
536 #define BIT_VIBR_HW_FLOW_ERR1 ( BIT(14) )
537 #define BIT_VIBR_HW_FLOW_ERR1_CLR ( BIT(0) )
539 /* bits definitions for register ANA_REG_GLB_VIBR_WR_PROT_VALUE */
540 #define BIT_VIBR_WR_PROT ( BIT(15) )
541 #define BITS_VIBR_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
543 /* bits definitions for register ANA_REG_GLB_AUDIO_CTRL */
544 #define BIT_AUD_SLP_APP_RST_EN ( BIT(10) )
545 #define BITS_CLK_AUD_HBD_DIV(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
546 #define BIT_CLK_AUD_LOOP_INV_EN ( BIT(4) )
547 #define BIT_CLK_AUDIF_TX_INV_EN ( BIT(3) )
548 #define BIT_CLK_AUDIF_RX_INV_EN ( BIT(2) )
549 #define BIT_CLK_AUD_6P5M_TX_INV_EN ( BIT(1) )
550 #define BIT_CLK_AUD_6P5M_RX_INV_EN ( BIT(0) )
552 /* bits definitions for register ANA_REG_GLB_CHGR_CTRL0 */
553 #define BIT_CHGR_PD_STS ( BIT(15) )
554 #define BITS_CHGR_CV_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)) )
555 #define BITS_CHGR_END_V(_x_) ( (_x_) << 4 & (BIT(4)|BIT(5)) )
556 #define BITS_CHG_PUMP_V(_x_) ( (_x_) << 2 & (BIT(2)|BIT(3)) )
557 #define BIT_CHGR_PD_RTCCLR ( BIT(1) )
558 #define BIT_CHGR_PD_RTCSET ( BIT(0) )
560 /* bits definitions for register ANA_REG_GLB_CHGR_CTRL1 */
561 #define BIT_DP_DM_SW_EN ( BIT(15) )
562 #define BITS_CHGR_CC_I(_x_) ( (_x_) << 10 & (BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
563 #define BITS_VBAT_OVP_V(_x_) ( (_x_) << 6 & (BIT(6)|BIT(7)|BIT(8)|BIT(9)) )
564 #define BITS_VCHG_OVP_V(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)) )
566 /* bits definitions for register ANA_REG_GLB_CHGR_CTRL2 */
567 #define BITS_CHG_PUMP_CAL(_x_) ( (_x_) << 9 & (BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
568 #define BIT_CHG_PUMP_PD ( BIT(8) )
569 #define BIT_CHGR_CC_EN ( BIT(1) )
570 #define BIT_RECHG ( BIT(0) )
572 /* bits definitions for register ANA_REG_GLB_CHGR_STATUS */
573 #define BIT_CHG_DET_DONE ( BIT(11) )
574 #define BIT_DP_LOW ( BIT(10) )
575 #define BIT_DCP_DET ( BIT(9) )
576 #define BIT_CHG_DET ( BIT(8) )
577 #define BIT_SDP_INT ( BIT(7) )
578 #define BIT_DCP_INT ( BIT(6) )
579 #define BIT_CDP_INT ( BIT(5) )
580 #define BIT_CHGR_CV_STATUS ( BIT(4) )
581 #define BIT_CHGR_ON ( BIT(3) )
582 #define BIT_CHGR_INT ( BIT(2) )
583 #define BIT_VBAT_OVI ( BIT(1) )
584 #define BIT_VCHG_OVI ( BIT(0) )
586 /* bits definitions for register ANA_REG_GLB_ANA_MIXED_CTRL */
587 #define BIT_PTEST_PD_RTCSET ( BIT(15) )
588 #define BIT_THM_CHIP_PD_FLAG ( BIT(8) )
589 #define BIT_THM_CHIP_PD_FLAG_CLR ( BIT(7) )
590 #define BITS_THM_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) )
591 #define BIT_THM_AUTO_PD_EN ( BIT(4) )
592 #define BIT_BG_LP_EN ( BIT(3) )
593 #define BITS_UVHO_T(_x_) ( (_x_) << 1 & (BIT(1)|BIT(2)) )
594 #define BIT_UVHO_EN ( BIT(0) )
596 /* bits definitions for register ANA_REG_GLB_PWR_XTL_EN0 */
597 #define BIT_LDO_XTL_EN ( BIT(15) )
598 #define BIT_LDO_RF1_EXT_XTL2_EN ( BIT(11) )
599 #define BIT_LDO_RF1_EXT_XTL1_EN ( BIT(10) )
600 #define BIT_LDO_RF1_EXT_XTL0_EN ( BIT(9) )
601 #define BIT_LDO_RF1_XTL2_EN ( BIT(8) )
602 #define BIT_LDO_RF1_XTL1_EN ( BIT(7) )
603 #define BIT_LDO_RF1_XTL0_EN ( BIT(6) )
604 #define BIT_LDO_RF0_EXT_XTL2_EN ( BIT(5) )
605 #define BIT_LDO_RF0_EXT_XTL1_EN ( BIT(4) )
606 #define BIT_LDO_RF0_EXT_XTL0_EN ( BIT(3) )
607 #define BIT_LDO_RF0_XTL2_EN ( BIT(2) )
608 #define BIT_LDO_RF0_XTL1_EN ( BIT(1) )
609 #define BIT_LDO_RF0_XTL0_EN ( BIT(0) )
611 /* bits definitions for register ANA_REG_GLB_PWR_XTL_EN1 */
612 #define BIT_LDO_VDD25_EXT_XTL2_EN ( BIT(11) )
613 #define BIT_LDO_VDD25_EXT_XTL1_EN ( BIT(10) )
614 #define BIT_LDO_VDD25_EXT_XTL0_EN ( BIT(9) )
615 #define BIT_LDO_VDD25_XTL2_EN ( BIT(8) )
616 #define BIT_LDO_VDD25_XTL1_EN ( BIT(7) )
617 #define BIT_LDO_VDD25_XTL0_EN ( BIT(6) )
618 #define BIT_LDO_RF2_EXT_XTL2_EN ( BIT(5) )
619 #define BIT_LDO_RF2_EXT_XTL1_EN ( BIT(4) )
620 #define BIT_LDO_RF2_EXT_XTL0_EN ( BIT(3) )
621 #define BIT_LDO_RF2_XTL2_EN ( BIT(2) )
622 #define BIT_LDO_RF2_XTL1_EN ( BIT(1) )
623 #define BIT_LDO_RF2_XTL0_EN ( BIT(0) )
625 /* bits definitions for register ANA_REG_GLB_PWR_XTL_EN2 */
626 #define BIT_LDO_AVDD18_EXT_XTL2_EN ( BIT(11) )
627 #define BIT_LDO_AVDD18_EXT_XTL1_EN ( BIT(10) )
628 #define BIT_LDO_AVDD18_EXT_XTL0_EN ( BIT(9) )
629 #define BIT_LDO_AVDD18_XTL2_EN ( BIT(8) )
630 #define BIT_LDO_AVDD18_XTL1_EN ( BIT(7) )
631 #define BIT_LDO_AVDD18_XTL0_EN ( BIT(6) )
632 #define BIT_LDO_SIM2_EXT_XTL2_EN ( BIT(5) )
633 #define BIT_LDO_SIM2_EXT_XTL1_EN ( BIT(4) )
634 #define BIT_LDO_SIM2_EXT_XTL0_EN ( BIT(3) )
635 #define BIT_LDO_SIM2_XTL2_EN ( BIT(2) )
636 #define BIT_LDO_SIM2_XTL1_EN ( BIT(1) )
637 #define BIT_LDO_SIM2_XTL0_EN ( BIT(0) )
639 /* bits definitions for register ANA_REG_GLB_PWR_XTL_EN3 */
640 #define BIT_DCDC_BG_EXT_XTL2_EN ( BIT(11) )
641 #define BIT_DCDC_BG_EXT_XTL1_EN ( BIT(10) )
642 #define BIT_DCDC_BG_EXT_XTL0_EN ( BIT(9) )
643 #define BIT_DCDC_BG_XTL2_EN ( BIT(8) )
644 #define BIT_DCDC_BG_XTL1_EN ( BIT(7) )
645 #define BIT_DCDC_BG_XTL0_EN ( BIT(6) )
646 #define BIT_BG_EXT_XTL2_EN ( BIT(5) )
647 #define BIT_BG_EXT_XTL1_EN ( BIT(4) )
648 #define BIT_BG_EXT_XTL0_EN ( BIT(3) )
649 #define BIT_BG_XTL2_EN ( BIT(2) )
650 #define BIT_BG_XTL1_EN ( BIT(1) )
651 #define BIT_BG_XTL0_EN ( BIT(0) )
653 /* bits definitions for register ANA_REG_GLB_PWR_XTL_EN4 */
654 #define BIT_DCDC_WRF_XTL2_EN ( BIT(14) )
655 #define BIT_DCDC_WRF_XTL1_EN ( BIT(13) )
656 #define BIT_DCDC_WRF_XTL0_EN ( BIT(12) )
657 #define BIT_DCDC_WPA_XTL2_EN ( BIT(11) )
658 #define BIT_DCDC_WPA_XTL1_EN ( BIT(10) )
659 #define BIT_DCDC_WPA_XTL0_EN ( BIT(9) )
660 #define BIT_DCDC_MEM_XTL2_EN ( BIT(8) )
661 #define BIT_DCDC_MEM_XTL1_EN ( BIT(7) )
662 #define BIT_DCDC_MEM_XTL0_EN ( BIT(6) )
663 #define BIT_DCDC_GEN_XTL2_EN ( BIT(5) )
664 #define BIT_DCDC_GEN_XTL1_EN ( BIT(4) )
665 #define BIT_DCDC_GEN_XTL0_EN ( BIT(3) )
666 #define BIT_DCDC_CORE_XTL2_EN ( BIT(2) )
667 #define BIT_DCDC_CORE_XTL1_EN ( BIT(1) )
668 #define BIT_DCDC_CORE_XTL0_EN ( BIT(0) )
670 /* bits definitions for register ANA_REG_GLB_PWR_XTL_EN5 */
671 #define BIT_DCDC_WRF_EXT_XTL2_EN ( BIT(14) )
672 #define BIT_DCDC_WRF_EXT_XTL1_EN ( BIT(13) )
673 #define BIT_DCDC_WRF_EXT_XTL0_EN ( BIT(12) )
674 #define BIT_DCDC_WPA_EXT_XTL2_EN ( BIT(11) )
675 #define BIT_DCDC_WPA_EXT_XTL1_EN ( BIT(10) )
676 #define BIT_DCDC_WPA_EXT_XTL0_EN ( BIT(9) )
677 #define BIT_DCDC_MEM_EXT_XTL2_EN ( BIT(8) )
678 #define BIT_DCDC_MEM_EXT_XTL1_EN ( BIT(7) )
679 #define BIT_DCDC_MEM_EXT_XTL0_EN ( BIT(6) )
680 #define BIT_DCDC_GEN_EXT_XTL2_EN ( BIT(5) )
681 #define BIT_DCDC_GEN_EXT_XTL1_EN ( BIT(4) )
682 #define BIT_DCDC_GEN_EXT_XTL0_EN ( BIT(3) )
683 #define BIT_DCDC_CORE_EXT_XTL2_EN ( BIT(2) )
684 #define BIT_DCDC_CORE_EXT_XTL1_EN ( BIT(1) )
685 #define BIT_DCDC_CORE_EXT_XTL0_EN ( BIT(0) )
687 /* bits definitions for register ANA_REG_GLB_ANA_STATUS */
688 #define BIT_BONDOPT5 ( BIT(5) )
689 #define BIT_BONDOPT4 ( BIT(4) )
690 #define BIT_BONDOPT3 ( BIT(3) )
691 #define BIT_BONDOPT2 ( BIT(2) )
692 #define BIT_BONDOPT1 ( BIT(1) )
693 #define BIT_BONDOPT0 ( BIT(0) )
695 /* bits definitions for register ANA_REG_GLB_POR_RST_MONITOR */
696 #define BITS_POR_RST_MONITOR(_x_) ( (_x_) << 0 )
698 /* bits definitions for register ANA_REG_GLB_WDG_RST_MONITOR */
699 #define BITS_WDG_RST_MONITOR(_x_) ( (_x_) << 0 )
701 /* bits definitions for register ANA_REG_GLB_POR_PIN_RST_MONITOR */
702 #define BITS_POR_PIN_RST_MONITOR(_x_) ( (_x_) << 0 )
704 /* bits definitions for register ANA_REG_GLB_POR_SRC_FLAG */
705 #define BIT_POR_SW_FORCE_ON ( BIT(15) )
706 #define BITS_POR_SRC_FLAG(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
708 /* bits definitions for register ANA_REG_GLB_POR_7S_CTRL */
709 #define BIT_PBINT_7S_FLAG_CLR ( BIT(15) )
710 #define BIT_EXT_RSTN_FLAG_CLR ( BIT(14) )
711 #define BIT_CHGR_INT_FLAG_CLR ( BIT(13) )
712 #define BIT_PBINT2_FLAG_CLR ( BIT(12) )
713 #define BIT_PBINT_FLAG_CLR ( BIT(11) )
714 #define BIT_PBINT_7S_RST_SWMODE_RTCSTS ( BIT(10) )
715 #define BIT_PBINT_7S_RST_SWMODE_RTCCLR ( BIT(9) )
716 #define BIT_PBINT_7S_RST_SWMODE_RTCSET ( BIT(8) )
717 #define BITS_PBINT_7S_RST_THRESHOLD(_x_)( (_x_) << 4 & (BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
718 #define BIT_PBINT_7S_RST_DISABLE ( BIT(3) )
719 #define BIT_PBINT_7S_RST_MODE_RTCSTS ( BIT(2) )
720 #define BIT_PBINT_7S_RST_MODE_RTCCLR ( BIT(1) )
721 #define BIT_PBINT_7S_RST_MODE_RTCSET ( BIT(0) )
723 /* bits definitions for register ANA_REG_GLB_INT_DEBUG */
724 #define BIT_OTP_INT_DEB ( BIT(10) )
725 #define BIT_THM_INT_DEB ( BIT(9) )
726 #define BIT_AUD_PROT_INT_DEB ( BIT(8) )
727 #define BIT_AUD_HEADBTN_INT_DEB ( BIT(7) )
728 #define BIT_EIC_INT_DEB ( BIT(6) )
729 #define BIT_FGU_INT_DEB ( BIT(5) )
730 #define BIT_WDG_INT_DEB ( BIT(4) )
731 #define BIT_RTC_INT_DEB ( BIT(3) )
732 #define BIT_GPIO_INT_DEB ( BIT(2) )
733 #define BIT_ADC_INT_DEB ( BIT(1) )
734 #define BIT_INT_DEBUG_EN ( BIT(0) )
736 /* bits definitions for register ANA_REG_GLB_GPI_DEBUG */
737 #define BIT_HEAD_INSERT2_DEB ( BIT(9) )
738 #define BIT_HEAD_INSERT_DEB ( BIT(8) )
739 #define BIT_HEAD_BUTTON_DEB ( BIT(7) )
740 #define BIT_PBINT2_DEB ( BIT(6) )
741 #define BIT_PBINT_DEB ( BIT(5) )
742 #define BIT_VCHG_OVI_DEB ( BIT(4) )
743 #define BIT_VBAT_OVI_DEB ( BIT(3) )
744 #define BIT_CHGR_INT_DEB ( BIT(2) )
745 #define BIT_GPI_DEBUG_EN ( BIT(0) )
747 /* bits definitions for register ANA_REG_GLB_HWRST_RTC */
748 #define BITS_HWRST_RTC_REG_STS(_x_) ( (_x_) << 8 & (BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)|BIT(15)) )
749 #define BITS_HWRST_RTC_REG_SET(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)) )
751 /* bits definitions for register ANA_REG_GLB_CHIP_ID_LOW */
752 #define BITS_CHIP_ID_LOW(_x_) ( (_x_) << 0 )
754 /* bits definitions for register ANA_REG_GLB_CHIP_ID_HIGH */
755 #define BITS_CHIP_ID_HIGH(_x_) ( (_x_) << 0 )
757 /* bits definitions for register ANA_REG_GLB_ARM_MF_REG */
758 #define BITS_ARM_MF_REG(_x_) ( (_x_) << 0 )
760 /* bits definitions for register ANA_REG_GLB_AFUSE_CTRL */
761 #define BIT_AFUSE_READ_REQ ( BIT(7) )
762 #define BITS_AFUSE_READ_DLY(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)) )
764 /* bits definitions for register ANA_REG_GLB_AFUSE_OUT0 */
765 #define BITS_AFUSE_OUT0(_x_) ( (_x_) << 0 )
767 /* bits definitions for register ANA_REG_GLB_AFUSE_OUT1 */
768 #define BITS_AFUSE_OUT1(_x_) ( (_x_) << 0 )
770 /* bits definitions for register ANA_REG_GLB_AFUSE_OUT2 */
771 #define BITS_AFUSE_OUT2(_x_) ( (_x_) << 0 )
773 /* bits definitions for register ANA_REG_GLB_AFUSE_OUT3 */
774 #define BITS_AFUSE_OUT3(_x_) ( (_x_) << 0 )
776 /* bits definitions for register ANA_REG_GLB_ARCH_EN */
777 #define BIT_ARCH_EN ( BIT(0) )
779 /* bits definitions for register ANA_REG_GLB_MCU_WR_PROT_VALUE */
780 #define BIT_MCU_WR_PROT ( BIT(15) )
781 #define BITS_MCU_WR_PROT_VALUE(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)|BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)|BIT(14)) )
783 /* bits definitions for register ANA_REG_GLB_DCDC_CORE_ADI */
784 #define BITS_DCDC_CORE_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
785 #define BITS_DCDC_CORE_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
787 /* bits definitions for register ANA_REG_GLB_DCDC_ARM_ADI */
788 #define BITS_DCDC_ARM_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
789 #define BITS_DCDC_ARM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
791 /* bits definitions for register ANA_REG_GLB_DCDC_MEM_ADI */
792 #define BIT_DCDC_MEM_CTL_ADI ( BIT(5) )
793 #define BITS_DCDC_MEM_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
795 /* bits definitions for register ANA_REG_GLB_DCDC_GEN_ADI */
796 #define BITS_DCDC_GEN_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)) )
797 #define BITS_DCDC_GEN_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
799 /* bits definitions for register ANA_REG_GLB_DCDC_WRF_ADI */
800 #define BITS_DCDC_WRF_CTL_ADI(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)) )
801 #define BITS_DCDC_WRF_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)|BIT(3)|BIT(4)) )
803 /* bits definitions for register ANA_REG_GLB_DCDC_WPA_ADI */
804 #define BITS_DCDC_WPA_CAL_ADI(_x_) ( (_x_) << 0 & (BIT(0)|BIT(1)|BIT(2)) )
806 /* bits definitions for register ANA_REG_GLB_DCDC_WPA_DCM_ADI */
807 #define BIT_DCDC_WPA_DCM_ADI ( BIT(0) )
809 /* bits definitions for register ANA_REG_GLB_LDO_CAL_SEL */
810 #define BIT_LDO_CAMIO_CAL_EN ( BIT(5) )
811 #define BIT_LDO_CLSG_CAL_EN ( BIT(6) )
812 #define BITS_LDO_CAMD_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(6)) )
813 #define BIT_LDO_EMMCIO_CAL_EN ( BIT(7) )
814 #define BITS_LDO_AVDD18_CAL_EN(_x_) ( (_x_) & (BIT(5)|BIT(7)) )
815 #define BITS_LDO_VDD18_CAL_EN(_x_) ( (_x_) & (BIT(6)|BIT(7)) )
816 #define BIT_LDO_SIM0_CAL_EN ( BIT(9) )
817 #define BIT_LDO_SIM1_CAL_EN ( BIT(9) )
818 #define BITS_LDO_SIM2_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)) )
819 #define BIT_LDO_EMMCCORE_CAL_EN ( BIT(10) )
820 #define BITS_LDO_VDD28_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(10)) )
821 #define BITS_LDO_VDD25_CAL_EN(_x_) ( (_x_) & (BIT(9)|BIT(10)) )
822 #define BITS_LDO_USB_CAL_EN(_x_) ( (_x_) & (BIT(8)|BIT(9)|BIT(10)) )
823 #define BIT_LDO_SD_CAL_EN ( BIT(11) )
824 #define BIT_LDO_CAMA_CAL_EN ( BIT(12) )
825 #define BITS_LDO_RF2_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(12)) )
826 #define BIT_LDO_RF1_CAL_EN ( BIT(13) )
827 #define BITS_LDO_RF0_CAL_EN(_x_) ( (_x_) & (BIT(11)|BIT(13)) )
828 #define BITS_LDO_CAMMOT_CAL_EN(_x_) ( (_x_) & (BIT(12)|BIT(13)) )
829 #define BITS_LDO_CAL_SEL(_x_) ( (_x_) << 5 & (BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13)) )
831 #define SHFT_LDO_CAL_SEL ( 5 )
832 #define MASK_LDO_CAL_SEL ( BIT(5)|BIT(6)|BIT(7)|BIT(8)|BIT(9)|BIT(10)|BIT(11)|BIT(12)|BIT(13) )
834 /* vars definitions for controller ANA_REGS_GLB */
836 #endif //__ANA_REGS_GLB_H__
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