include/soc/sprd/chip_x20/__regs_pinmap.h

   1 #ifndef __ASM_ARM_ARCH_PINMAP_H
   2 #error  "Don't include this file directly, Pls include pinmap.h"
   3 #endif
   4
   5 #ifndef _REGS_PINMAP_H_
   6 #define _REGS_PINMAP_H_
   7
   8 #define CTL_PIN_BASE                    (SPRD_PIN_BASE)
   9
  10 /* registers definitions for controller CTL_PIN */
  11 #define REG_PIN_CTRL0                   ( 0x0000 )
  12 #define REG_PIN_CTRL1                   ( 0x0004 )
  13 #define REG_PIN_CTRL2                   ( 0x0008 )
  14 #define REG_PIN_CTRL3                   ( 0x000c )
  15 #define REG_PIN_CTRL4                   ( 0x0010 )
  16 #define REG_PIN_CTRL5                   ( 0x0014 )
  17
  18 #define REG_PIN_TRACECLK                ( 0x0020 )
  19 #define REG_PIN_TRACECTRL               ( 0x0024 )
  20 #define REG_PIN_TRACEDAT0               ( 0x0028 )
  21 #define REG_PIN_TRACEDAT1               ( 0x002c )
  22 #define REG_PIN_TRACEDAT2               ( 0x0030 )
  23 #define REG_PIN_TRACEDAT3               ( 0x0034 )
  24 #define REG_PIN_TRACEDAT4               ( 0x0038 )
  25 #define REG_PIN_TRACEDAT5               ( 0x003c )
  26 #define REG_PIN_TRACEDAT6               ( 0x0040 )
  27 #define REG_PIN_TRACEDAT7               ( 0x0044 )
  28 #define REG_PIN_U0TXD                   ( 0x0048 )
  29 #define REG_PIN_U0RXD                   ( 0x004c )
  30 #define REG_PIN_U0CTS                   ( 0x0050 )
  31 #define REG_PIN_U0RTS                   ( 0x0054 )
  32 #define REG_PIN_U1TXD                   ( 0x0058 )
  33 #define REG_PIN_U1RXD                   ( 0x005c )
  34 #define REG_PIN_U2TXD                   ( 0x0060 )
  35 #define REG_PIN_U2RXD                   ( 0x0064 )
  36 #define REG_PIN_U3TXD                   ( 0x0068 )
  37 #define REG_PIN_U3RXD                   ( 0x006c )
  38 #define REG_PIN_U3CTS                   ( 0x0070 )
  39 #define REG_PIN_U3RTS                   ( 0x0074 )
  40 #define REG_PIN_CP2_RFCTL0              ( 0x0078 )
  41 #define REG_PIN_CP2_RFCTL1              ( 0x007c )
  42 #define REG_PIN_CP2_RFCTL2              ( 0x0080 )
  43 #define REG_PIN_WIFI_AGCGAIN3           ( 0x0084 )
  44 #define REG_PIN_WIFI_AGCGAIN4           ( 0x0088 )
  45 #define REG_PIN_WIFI_AGCGAIN5           ( 0x008c )
  46 #define REG_PIN_WIFI_AGCGAIN6           ( 0x0090 )
  47 #define REG_PIN_RFSDA0                  ( 0x0094 )
  48 #define REG_PIN_RFSCK0                  ( 0x0098 )
  49 #define REG_PIN_RFSEN0                  ( 0x009c )
  50 #define REG_PIN_RFSDA1                  ( 0x00a0 )
  51 #define REG_PIN_RFSCK1                  ( 0x00a4 )
  52 #define REG_PIN_RFSEN1                  ( 0x00a8 )
  53 #define REG_PIN_CP1_RFCTL0              ( 0x00ac )
  54 #define REG_PIN_CP1_RFCTL1              ( 0x00b0 )
  55 #define REG_PIN_CP1_RFCTL2              ( 0x00b4 )
  56 #define REG_PIN_CP1_RFCTL3              ( 0x00b8 )
  57 #define REG_PIN_CP1_RFCTL4              ( 0x00bc )
  58 #define REG_PIN_CP1_RFCTL5              ( 0x00c0 )
  59 #define REG_PIN_CP1_RFCTL6              ( 0x00c4 )
  60 #define REG_PIN_CP1_RFCTL7              ( 0x00c8 )
  61 #define REG_PIN_CP1_RFCTL8              ( 0x00cc )
  62 #define REG_PIN_CP1_RFCTL9              ( 0x00d0 )
  63 #define REG_PIN_CP1_RFCTL10             ( 0x00d4 )
  64 #define REG_PIN_CP1_RFCTL11             ( 0x00d8 )
  65 #define REG_PIN_CP1_RFCTL12             ( 0x00dc )
  66 #define REG_PIN_CP1_RFCTL13             ( 0x00e0 )
  67 #define REG_PIN_CP1_RFCTL14             ( 0x00e4 )
  68 #define REG_PIN_CP1_RFCTL15             ( 0x00e8 )
  69 #define REG_PIN_CP0_RFCTL0              ( 0x00ec )
  70 #define REG_PIN_CP0_RFCTL1              ( 0x00f0 )
  71 #define REG_PIN_CP0_RFCTL2              ( 0x00f4 )
  72 #define REG_PIN_CP0_RFCTL3              ( 0x00f8 )
  73 #define REG_PIN_CP0_RFCTL4              ( 0x00fc )
  74 #define REG_PIN_CP0_RFCTL5              ( 0x0100 )
  75 #define REG_PIN_CP0_RFCTL6              ( 0x0104 )
  76 #define REG_PIN_CP0_RFCTL7              ( 0x0108 )
  77 #define REG_PIN_XTLEN                   ( 0x010c )
  78 #define REG_PIN_SCL3                    ( 0x0110 )
  79 #define REG_PIN_SDA3                    ( 0x0114 )
  80 #define REG_PIN_SPI0_CSN                ( 0x0118 )
  81 #define REG_PIN_SPI0_DO                 ( 0x011c )
  82 #define REG_PIN_SPI0_DI                 ( 0x0120 )
  83 #define REG_PIN_SPI0_CLK                ( 0x0124 )
  84 #define REG_PIN_EXTINT0                 ( 0x0128 )
  85 #define REG_PIN_EXTINT1                 ( 0x012c )
  86 #define REG_PIN_SCL1                    ( 0x0130 )
  87 #define REG_PIN_SDA1                    ( 0x0134 )
  88 #define REG_PIN_SIMCLK0                 ( 0x0138 )
  89 #define REG_PIN_SIMDA0                  ( 0x013c )
  90 #define REG_PIN_SIMRST0                 ( 0x0140 )
  91 #define REG_PIN_SIMCLK1                 ( 0x0144 )
  92 #define REG_PIN_SIMDA1                  ( 0x0148 )
  93 #define REG_PIN_SIMRST1                 ( 0x014c )
  94 #define REG_PIN_SIMCLK2                 ( 0x0150 )
  95 #define REG_PIN_SIMDA2                  ( 0x0154 )
  96 #define REG_PIN_SIMRST2                 ( 0x0158 )
  97 #define REG_PIN_MEMS_MIC_CLK0           ( 0x015c )
  98 #define REG_PIN_MEMS_MIC_DATA0          ( 0x0160 )
  99 #define REG_PIN_MEMS_MIC_CLK1           ( 0x0164 )
 100 #define REG_PIN_MEMS_MIC_DATA1          ( 0x0168 )
 101 #define REG_PIN_SD1_CLK                 ( 0x016c )
 102 #define REG_PIN_SD1_CMD                 ( 0x0170 )
 103 #define REG_PIN_SD1_D0                  ( 0x0174 )
 104 #define REG_PIN_SD1_D1                  ( 0x0178 )
 105 #define REG_PIN_SD1_D2                  ( 0x017c )
 106 #define REG_PIN_SD1_D3                  ( 0x0180 )
 107 #define REG_PIN_SD0_D3                  ( 0x0184 )
 108 #define REG_PIN_SD0_D2                  ( 0x0188 )
 109 #define REG_PIN_SD0_CMD                 ( 0x018c )
 110 #define REG_PIN_SD0_D0                  ( 0x0190 )
 111 #define REG_PIN_SD0_D1                  ( 0x0194 )
 112 #define REG_PIN_SD0_CLK1                ( 0x0198 )
 113 #define REG_PIN_SD0_CLK0                ( 0x019c )
 114 #define REG_PIN_PTEST                   ( 0x01a0 )
 115 #define REG_PIN_ANA_INT                 ( 0x01a4 )
 116 #define REG_PIN_EXT_RST_B               ( 0x01a8 )
 117 #define REG_PIN_CHIP_SLEEP              ( 0x01ac )
 118 #define REG_PIN_XTL_BUF_EN0             ( 0x01b0 )
 119 #define REG_PIN_XTL_BUF_EN1             ( 0x01b4 )
 120 #define REG_PIN_XTL_BUF_EN2             ( 0x01b8 )
 121 #define REG_PIN_CLK_32K                 ( 0x01bc )
 122 #define REG_PIN_AUD_SCLK                ( 0x01c0 )
 123 #define REG_PIN_AUD_DANGL               ( 0x01c4 )
 124 #define REG_PIN_AUD_DANGR               ( 0x01c8 )
 125 #define REG_PIN_AUD_ADD0                ( 0x01cc )
 126 #define REG_PIN_AUD_ADSYNC              ( 0x01d0 )
 127 #define REG_PIN_AUD_DAD1                ( 0x01d4 )
 128 #define REG_PIN_AUD_DAD0                ( 0x01d8 )
 129 #define REG_PIN_AUD_DASYNC              ( 0x01dc )
 130 #define REG_PIN_ADI_D                   ( 0x01e0 )
 131 #define REG_PIN_ADI_SYNC                ( 0x01e4 )
 132 #define REG_PIN_ADI_SCLK                ( 0x01e8 )
 133 #define REG_PIN_LCD_CSN1                ( 0x01ec )
 134 #define REG_PIN_LCD_CSN0                ( 0x01f0 )
 135 #define REG_PIN_LCD_RSTN                ( 0x01f4 )
 136 #define REG_PIN_LCD_CD                  ( 0x01f8 )
 137 #define REG_PIN_LCD_FMARK               ( 0x01fc )
 138 #define REG_PIN_LCD_WRN                 ( 0x0200 )
 139 #define REG_PIN_LCD_RDN                 ( 0x0204 )
 140 #define REG_PIN_LCD_D0                  ( 0x0208 )
 141 #define REG_PIN_LCD_D1                  ( 0x020c )
 142 #define REG_PIN_LCD_D2                  ( 0x0210 )
 143 #define REG_PIN_LCD_D3                  ( 0x0214 )
 144 #define REG_PIN_LCD_D4                  ( 0x0218 )
 145 #define REG_PIN_LCD_D5                  ( 0x021c )
 146 #define REG_PIN_LCD_D6                  ( 0x0220 )
 147 #define REG_PIN_LCD_D7                  ( 0x0224 )
 148 #define REG_PIN_LCD_D8                  ( 0x0228 )
 149 #define REG_PIN_LCD_D9                  ( 0x022c )
 150 #define REG_PIN_LCD_D10                 ( 0x0230 )
 151 #define REG_PIN_LCD_D11                 ( 0x0234 )
 152 #define REG_PIN_LCD_D12                 ( 0x0238 )
 153 #define REG_PIN_LCD_D13                 ( 0x023c )
 154 #define REG_PIN_LCD_D14                 ( 0x0240 )
 155 #define REG_PIN_LCD_D15                 ( 0x0244 )
 156 #define REG_PIN_LCD_D16                 ( 0x0248 )
 157 #define REG_PIN_LCD_D17                 ( 0x024c )
 158 #define REG_PIN_LCD_D18                 ( 0x0250 )
 159 #define REG_PIN_LCD_D19                 ( 0x0254 )
 160 #define REG_PIN_LCD_D20                 ( 0x0258 )
 161 #define REG_PIN_LCD_D21                 ( 0x025c )
 162 #define REG_PIN_LCD_D22                 ( 0x0260 )
 163 #define REG_PIN_LCD_D23                 ( 0x0264 )
 164 #define REG_PIN_SPI2_CSN                ( 0x0268 )
 165 #define REG_PIN_SPI2_DO                 ( 0x026c )
 166 #define REG_PIN_SPI2_DI                 ( 0x0270 )
 167 #define REG_PIN_SPI2_CLK                ( 0x0274 )
 168 #define REG_PIN_EMMC_CLK                ( 0x0278 )
 169 #define REG_PIN_EMMC_CMD                ( 0x027c )
 170 #define REG_PIN_EMMC_D0                 ( 0x0280 )
 171 #define REG_PIN_EMMC_D1                 ( 0x0284 )
 172 #define REG_PIN_EMMC_D2                 ( 0x0288 )
 173 #define REG_PIN_EMMC_D3                 ( 0x028c )
 174 #define REG_PIN_EMMC_D4                 ( 0x0290 )
 175 #define REG_PIN_EMMC_D5                 ( 0x0294 )
 176 #define REG_PIN_EMMC_D6                 ( 0x0298 )
 177 #define REG_PIN_EMMC_D7                 ( 0x029c )
 178 #define REG_PIN_EMMC_RST                ( 0x02a0 )
 179 #define REG_PIN_NFWPN                   ( 0x02a4 )
 180 #define REG_PIN_NFRB                    ( 0x02a8 )
 181 #define REG_PIN_NFCLE                   ( 0x02ac )
 182 #define REG_PIN_NFALE                   ( 0x02b0 )
 183 #define REG_PIN_NFCEN0                  ( 0x02b4 )
 184 #define REG_PIN_NFCEN1                  ( 0x02b8 )
 185 #define REG_PIN_NFREN                   ( 0x02bc )
 186 #define REG_PIN_NFWEN                   ( 0x02c0 )
 187 #define REG_PIN_NFD0                    ( 0x02c4 )
 188 #define REG_PIN_NFD1                    ( 0x02c8 )
 189 #define REG_PIN_NFD2                    ( 0x02cc )
 190 #define REG_PIN_NFD3                    ( 0x02d0 )
 191 #define REG_PIN_NFD4                    ( 0x02d4 )
 192 #define REG_PIN_NFD5                    ( 0x02d8 )
 193 #define REG_PIN_NFD6                    ( 0x02dc )
 194 #define REG_PIN_NFD7                    ( 0x02e0 )
 195 #define REG_PIN_NFD8                    ( 0x02e4 )
 196 #define REG_PIN_NFD9                    ( 0x02e8 )
 197 #define REG_PIN_NFD10                   ( 0x02ec )
 198 #define REG_PIN_NFD11                   ( 0x02f0 )
 199 #define REG_PIN_NFD12                   ( 0x02f4 )
 200 #define REG_PIN_NFD13                   ( 0x02f8 )
 201 #define REG_PIN_NFD14                   ( 0x02fc )
 202 #define REG_PIN_NFD15                   ( 0x0300 )
 203 #define REG_PIN_CCIRCK0                 ( 0x0304 )
 204 #define REG_PIN_CCIRCK1                 ( 0x0308 )
 205 #define REG_PIN_CCIRMCLK                ( 0x030c )
 206 #define REG_PIN_CCIRHS                  ( 0x0310 )
 207 #define REG_PIN_CCIRVS                  ( 0x0314 )
 208 #define REG_PIN_CCIRD0                  ( 0x0318 )
 209 #define REG_PIN_CCIRD1                  ( 0x031c )
 210 #define REG_PIN_CCIRD2                  ( 0x0320 )
 211 #define REG_PIN_CCIRD3                  ( 0x0324 )
 212 #define REG_PIN_CCIRD4                  ( 0x0328 )
 213 #define REG_PIN_CCIRD5                  ( 0x032c )
 214 #define REG_PIN_CCIRD6                  ( 0x0330 )
 215 #define REG_PIN_CCIRD7                  ( 0x0334 )
 216 #define REG_PIN_CCIRD8                  ( 0x0338 )
 217 #define REG_PIN_CCIRD9                  ( 0x033c )
 218 #define REG_PIN_CCIRRST                 ( 0x0340 )
 219 #define REG_PIN_CCIRPD1                 ( 0x0344 )
 220 #define REG_PIN_CCIRPD0                 ( 0x0348 )
 221 #define REG_PIN_SCL0                    ( 0x034c )
 222 #define REG_PIN_SDA0                    ( 0x0350 )
 223 #define REG_PIN_KEYOUT0                 ( 0x0354 )
 224 #define REG_PIN_KEYOUT1                 ( 0x0358 )
 225 #define REG_PIN_KEYOUT2                 ( 0x035c )
 226 #define REG_PIN_KEYIN0                  ( 0x0360 )
 227 #define REG_PIN_KEYIN1                  ( 0x0364 )
 228 #define REG_PIN_KEYIN2                  ( 0x0368 )
 229 #define REG_PIN_SCL2                    ( 0x036c )
 230 #define REG_PIN_SDA2                    ( 0x0370 )
 231 #define REG_PIN_CLK_AUX0                ( 0x0374 )
 232 #define REG_PIN_IIS0DI                  ( 0x0378 )
 233 #define REG_PIN_IIS0DO                  ( 0x037c )
 234 #define REG_PIN_IIS0CLK                 ( 0x0380 )
 235 #define REG_PIN_IIS0LRCK                ( 0x0384 )
 236 #define REG_PIN_IIS0MCK                 ( 0x0388 )
 237 #define REG_PIN_IIS1DI                  ( 0x038c )
 238 #define REG_PIN_IIS1DO                  ( 0x0390 )
 239 #define REG_PIN_IIS1CLK                 ( 0x0394 )
 240 #define REG_PIN_IIS1LRCK                ( 0x0398 )
 241 #define REG_PIN_IIS1MCK                 ( 0x039c )
 242 #define REG_PIN_MTDO                    ( 0x03a0 )
 243 #define REG_PIN_MTDI                    ( 0x03a4 )
 244 #define REG_PIN_MTCK                    ( 0x03a8 )
 245 #define REG_PIN_MTMS                    ( 0x03ac )
 246 #define REG_PIN_MTRST_N                 ( 0x03b0 )
 247
 248
 249
 250 /* bits definitions for register REG_PIN_XXX */
 251 #define BITS_PIN_DS(_x_)                ( ((_x_) << 18) & (BIT_18|BIT_19|BIT_20|BIT_21) )
 252 #define BIT_PIN_SLP_AP                  ( BIT_13 )
 253 #define BIT_PIN_SLP_CP0                 ( BIT_14 )
 254 #define BIT_PIN_SLP_CP1                 ( BIT_15 )
 255 #define BIT_PIN_SLP_CP2                 ( BIT_16 )
 256 #define BITS_PIN_SLP(_x_)               ( ((_x_) << 13) & (BIT_13|BIT_14|BIT_15|BIT_16) )
 257 #define BIT_PIN_WPU_SEL                 ( BIT_12 )
 258 #define BIT_PIN_WPU                     ( BIT_7 )
 259 #define BIT_PIN_WPD                     ( BIT_6 )
 260 #define BITS_PIN_AF(_x_)                ( ((_x_) << 4) & (BIT_4|BIT_5) )
 261 #define BIT_PIN_SLP_WPU                 ( BIT_3 )
 262 #define BIT_PIN_SLP_WPD                 ( BIT_2 )
 263 #define BIT_PIN_SLP_IE                  ( BIT_1 )
 264 #define BIT_PIN_SLP_OE                  ( BIT_0 )
 265
 266 /* vars definitions for controller CTL_PIN */
 267 #define BIT_PIN_NUL                     ( 0 )
 268 #define BIT_PIN_SLP_NUL                 ( 0 )
 269 #define BIT_PIN_SLP_Z                   ( 0 )
 270 #define BIT_PIN_WPU_SEL                 ( BIT_12 )
 271 #define BIT_PIN_WPUS                    ( BIT_12 )
 272 #define BIT_PIN_NULL                    ( 0 )
 273
 274 #endif