2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #ifndef __ASM_ARCH_AUDIO_GLB_SCX35L_H
15 #define __ASM_ARCH_AUDIO_GLB_SCX35L_H
17 #ifndef __ASM_ARCH_AUDIO_GLB_H
18 #error "Don't include this file directly, include <mach/sprd-audio.h>"
21 #include <linux/delay.h>
23 #include <soc/sprd/hardware.h>
24 #include <soc/sprd/sci.h>
25 #include <soc/sprd/sci_glb_regs.h>
26 #include <soc/sprd/adi.h>
27 #include <soc/sprd/irqs.h>
28 #ifndef CONFIG_SND_SOC_SPRD_AUDIO_DMA_ENGINE
29 #include <soc/sprd/dma.h>
31 #include <../../../drivers/dma/sprd_dma.h>
34 /* OKAY, this is for other else owner
35 if you do not care the audio config
36 you can set FIXED_AUDIO to 0
44 AUDIO_TO_CP0_DSP_CTRL,
45 AUDIO_TO_CP1_DSP_CTRL,
47 AUDIO_TO_ARM_CTRL = AUDIO_TO_AP_ARM_CTRL,
48 AUDIO_TO_CP0_ARM_CTRL,
49 AUDIO_TO_CP1_ARM_CTRL,
50 AUDIO_TO_CP2_ARM_CTRL,
56 #define CODEC_DP_BASE (0x1000)
57 #define VBC_BASE (0x1000)
58 #define CODEC_AP_BASE (0x2000)
59 #define CODEC_AP_OFFSET (0)
61 #define CODEC_DP_BASE_DEFAULT 0x40000000
62 #define CODEC_DP_SIZE_DEFAULT SZ_8K
64 #define VBC_BASE_DEFAULT 0x40020000
65 #define VBC_BASE_SIZE_DEFAULT SZ_4K + SZ_8K
67 #define VBC_PHY_BASE 0
69 #define VBC_BASE (SPRD_VBC_BASE)
70 #define CODEC_DP_BASE SPRD_AUDIO_BASE
71 #define VBC_PHY_BASE SPRD_VBC_PHYS
73 /* CODEC_AP_BASE: the bit15 cann't be 1 for asoc reg.*/
74 #if (ANA_AUDCFGA_INT_BASE & BIT(15))
75 #define CODEC_AP_BASE (ANA_AUDCFGA_INT_BASE & ~(BIT(15)))
76 #define CODEC_AP_OFFSET (0x8000)
78 #define CODEC_AP_BASE (ANA_AUDCFGA_INT_BASE)
79 #define CODEC_AP_OFFSET (0)
83 #define VBC_CP2_PHY_BASE (0x02020000)
84 #define CP2_PHYS_VBDA0 (VBC_CP2_PHY_BASE + 0x0000)
85 #define CP2_PHYS_VBDA1 (VBC_CP2_PHY_BASE + 0x0004)
87 #define CODEC_DP_PHY_BASE SPRD_AUDIO_PHYS
88 #define CODEC_AP_PHY_BASE (SPRD_ADISLAVE_PHYS + 0x0600)
89 #define CODEC_AP_IRQ (IRQ_ANA_AUD_INT)
90 #define CODEC_DP_IRQ (IRQ_REQ_AUD_INT)
92 #define SPRD_IRAM_ALL_PHYS (SPRD_IRAM2_PHYS)
93 #define SPRD_IRAM_ALL_SIZE (SPRD_IRAM2_SIZE)
95 #define CLASS_G_LDO_ID "vddclsg"
98 /* ------------------------------------------------------------------------- */
100 /* NOTE: all function maybe will call by atomic funtion
101 don NOT any complex oprations. Just register.
109 static inline int arch_audio_vbc_reg_enable(void)
114 sci_glb_set(REG_AON_APB_APB_EB0, BIT_VBC_EB);
120 static inline int arch_audio_vbc_reg_disable(void)
125 sci_glb_clr(REG_AON_APB_APB_EB0, BIT_VBC_EB);
131 static inline int arch_audio_vbc_enable(void)
141 static inline int arch_audio_vbc_disable(void)
151 static inline int arch_audio_vbc_reset(void);
152 static inline int arch_audio_vbc_switch(int master)
158 BITS_VBC_AFIFO_INT_SYS_SEL(3) | BITS_VBC_DA01_INT_SYS_SEL(3) |
159 BITS_VBC_AD01_INT_SYS_SEL(3)
160 | BITS_VBC_AD23_INT_SYS_SEL(3) | BITS_VBC_DA01_DMA_SYS_SEL(3) |
161 BITS_VBC_AD01_DMA_SYS_SEL(3)
162 | BITS_VBC_AD23_DMA_SYS_SEL(3);
164 if (master != AUDIO_NO_CHANGE) {
165 sci_glb_set(REG_AON_APB_CP0_WPROT_EN0, BIT(6));
166 sci_glb_set(REG_AON_APB_CP1_WPROT_EN0, BIT(6));
167 //changed by jian.chen
168 //sci_glb_set(REG_AON_APB_CP2_WPROT_EN, BIT(6));
171 case AUDIO_TO_AP_ARM_CTRL:
173 BITS_VBC_AFIFO_INT_SYS_SEL(0) | BITS_VBC_DA01_INT_SYS_SEL(0)
174 | BITS_VBC_AD01_INT_SYS_SEL(0)
175 | BITS_VBC_AD23_INT_SYS_SEL(0);
176 #ifndef CONFIG_SND_SOC_SPRD_AUDIO_USE_AON_DMA
178 (BITS_VBC_DA01_DMA_SYS_SEL(0) | BITS_VBC_AD01_DMA_SYS_SEL(0)
179 | BITS_VBC_AD23_DMA_SYS_SEL(0));
181 /* Capture will only use AP DMA for the limitation of IRAM size */
183 (BITS_VBC_DA01_DMA_SYS_SEL(2) | BITS_VBC_AD01_DMA_SYS_SEL(0)
184 | BITS_VBC_AD23_DMA_SYS_SEL(0));
186 sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask);
187 sci_glb_clr(REG_AON_APB_AP_WPROT_EN0, BIT(6));
188 arch_audio_vbc_reset();
189 arch_audio_vbc_reg_disable();
191 case AUDIO_TO_CP0_DSP_CTRL:
192 arch_audio_vbc_reset();
193 arch_audio_vbc_reg_enable();
194 sci_glb_clr(REG_AON_APB_CP0_WPROT_EN0, BIT(6));
196 BITS_VBC_AFIFO_INT_SYS_SEL(1) | BITS_VBC_DA01_INT_SYS_SEL(1)
197 | BITS_VBC_AD01_INT_SYS_SEL(1)
198 | BITS_VBC_AD23_INT_SYS_SEL(1) |
199 BITS_VBC_DA01_DMA_SYS_SEL(1) | BITS_VBC_AD01_DMA_SYS_SEL(1)
200 | BITS_VBC_AD23_DMA_SYS_SEL(1);
201 sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask);
202 #ifndef CONFIG_ARCH_SCX20L
203 sci_glb_write(REG_AON_APB_VBC_CTRL, 0,
204 (BIT_VBC_DMA_CP0_ARM_SEL |
205 BIT_VBC_DMA_CP0_ARM_SEL));
208 case AUDIO_TO_CP1_DSP_CTRL:
209 arch_audio_vbc_reset();
210 arch_audio_vbc_reg_enable();
211 sci_glb_clr(REG_AON_APB_CP1_WPROT_EN0, BIT(6));
213 BITS_VBC_AFIFO_INT_SYS_SEL(2) | BITS_VBC_DA01_INT_SYS_SEL(2)
214 | BITS_VBC_AD01_INT_SYS_SEL(2)
215 | BITS_VBC_AD23_INT_SYS_SEL(2) |
216 BITS_VBC_DA01_DMA_SYS_SEL(2) | BITS_VBC_AD01_DMA_SYS_SEL(2)
217 | BITS_VBC_AD23_DMA_SYS_SEL(2);
218 sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask);
219 #ifndef CONFIG_ARCH_SCX20L
220 sci_glb_write(REG_AON_APB_VBC_CTRL, 0,
221 (BIT_VBC_DMA_CP1_ARM_SEL |
222 BIT_VBC_DMA_CP1_ARM_SEL));
225 case AUDIO_TO_CP0_ARM_CTRL:
226 arch_audio_vbc_reset();
227 arch_audio_vbc_reg_enable();
228 sci_glb_clr(REG_AON_APB_CP0_WPROT_EN0, BIT(6));
230 BITS_VBC_AFIFO_INT_SYS_SEL(1) | BITS_VBC_DA01_INT_SYS_SEL(1)
231 | BITS_VBC_AD01_INT_SYS_SEL(1)
232 | BITS_VBC_AD23_INT_SYS_SEL(1) |
233 BITS_VBC_DA01_DMA_SYS_SEL(1) | BITS_VBC_AD01_DMA_SYS_SEL(1)
234 | BITS_VBC_AD23_DMA_SYS_SEL(1);
235 #ifndef CONFIG_ARCH_SCX20L
236 sci_glb_write(REG_AON_APB_VBC_CTRL,
237 (val | BIT_VBC_INT_CP0_ARM_SEL |
238 BIT_VBC_DMA_CP0_ARM_SEL),
239 (mask | BIT_VBC_INT_CP0_ARM_SEL |
240 BIT_VBC_DMA_CP0_ARM_SEL));
243 case AUDIO_TO_CP1_ARM_CTRL:
244 arch_audio_vbc_reset();
245 arch_audio_vbc_reg_enable();
246 sci_glb_clr(REG_AON_APB_CP1_WPROT_EN0, BIT(6));
248 BITS_VBC_AFIFO_INT_SYS_SEL(2) | BITS_VBC_DA01_INT_SYS_SEL(2)
249 | BITS_VBC_AD01_INT_SYS_SEL(2)
250 | BITS_VBC_AD23_INT_SYS_SEL(2) |
251 BITS_VBC_DA01_DMA_SYS_SEL(2) | BITS_VBC_AD01_DMA_SYS_SEL(2)
252 | BITS_VBC_AD23_DMA_SYS_SEL(2);
253 #ifndef CONFIG_ARCH_SCX20L
254 sci_glb_write(REG_AON_APB_VBC_CTRL,
255 (val | BIT_VBC_INT_CP1_ARM_SEL |
256 BIT_VBC_DMA_CP1_ARM_SEL),
257 (mask | BIT_VBC_INT_CP1_ARM_SEL |
258 BIT_VBC_DMA_CP1_ARM_SEL));
261 //changed by jian.chen
263 case AUDIO_TO_CP2_ARM_CTRL:
264 sci_glb_clr(REG_AON_APB_CP2_WPROT_EN, BIT(6));
266 BITS_VBC_AFIFO_INT_SYS_SEL(3) | BITS_VBC_DA01_INT_SYS_SEL(3)
267 | BITS_VBC_AD01_INT_SYS_SEL(3)
268 | BITS_VBC_AD23_INT_SYS_SEL(3) |
269 BITS_VBC_DA01_DMA_SYS_SEL(3) | BITS_VBC_AD01_DMA_SYS_SEL(3)
270 | BITS_VBC_AD23_DMA_SYS_SEL(3);
271 sci_glb_write(REG_AON_APB_VBC_CTRL, val, mask);
274 case AUDIO_NO_CHANGE:
276 sci_glb_read(REG_AON_APB_VBC_CTRL,
277 BITS_VBC_DA01_INT_SYS_SEL(3));
278 if (ret == BITS_VBC_DA01_INT_SYS_SEL(0)) {
279 ret = AUDIO_TO_AP_ARM_CTRL;
280 } else if (ret == BITS_VBC_DA01_INT_SYS_SEL(1)) {
281 #ifndef CONFIG_ARCH_SCX20L
283 sci_glb_read(REG_AON_APB_VBC_CTRL,
284 BIT_VBC_INT_CP0_ARM_SEL);
286 ret = AUDIO_TO_CP0_ARM_CTRL;
289 ret = AUDIO_TO_CP0_DSP_CTRL;
290 } else if (ret == BITS_VBC_DA01_INT_SYS_SEL(2)) {
291 #ifndef CONFIG_ARCH_SCX20L
293 sci_glb_read(REG_AON_APB_VBC_CTRL,
294 BIT_VBC_INT_CP1_ARM_SEL);
296 ret = AUDIO_TO_CP1_ARM_CTRL;
299 ret = AUDIO_TO_CP1_DSP_CTRL;
300 } else if (ret == BITS_VBC_DA01_INT_SYS_SEL(3)) {
301 ret = AUDIO_TO_CP2_ARM_CTRL;
313 static inline int arch_audio_vbc_da_dma_info(int chan)
334 static inline int arch_audio_vbc_ad_dma_info(int chan)
355 static inline int arch_audio_vbc_ad23_dma_info(int chan)
376 static inline int arch_audio_vbc_reset(void)
381 sci_glb_set(REG_AON_APB_APB_RST0, BIT_VBC_SOFT_RST);
383 sci_glb_clr(REG_AON_APB_APB_RST0, BIT_VBC_SOFT_RST);
390 /* some SOC will move this into vbc module */
391 static inline int arch_audio_vbc_ad_int_clr(void)
399 static inline int arch_audio_vbc_ad23_int_clr(void)
407 /* some SOC will move this into vbc module */
408 static inline int arch_audio_vbc_da_int_clr(void)
416 /* some SOC will move this into vbc module */
417 static inline int arch_audio_vbc_is_ad_int(void)
425 /* some SOC will move this into vbc module */
426 static inline int arch_audio_vbc_is_ad23_int(void)
434 /* some SOC will move this into vbc module */
435 static inline int arch_audio_vbc_is_da_int(void)
443 /* ------------------------------------------------------------------------- */
446 static inline int arch_audio_codec_write_mask(int reg, int val, int mask)
451 ret = sci_adi_write((reg + CODEC_AP_OFFSET + ANA_AUDCFGA_INT_BASE - CODEC_AP_BASE), val, mask);
457 static inline int arch_audio_codec_write(int reg, int val)
462 ret = sci_adi_write((reg + CODEC_AP_OFFSET + ANA_AUDCFGA_INT_BASE - CODEC_AP_BASE), val, 0xFFFF);
468 static inline int arch_audio_codec_read(int reg)
473 ret = sci_adi_read(reg + CODEC_AP_OFFSET + ANA_AUDCFGA_INT_BASE - CODEC_AP_BASE);
479 static inline int arch_audio_codec_audif_enable(int auto_clk)
485 sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUDIF_EB);
486 sci_glb_set(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN);
488 sci_glb_set(REG_AON_APB_APB_EB0, BIT_AUDIF_EB);
489 sci_glb_clr(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN);
496 static inline int arch_audio_codec_audif_disable(void)
501 sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUDIF_EB);
502 sci_glb_clr(REG_AON_APB_VBC_CTRL, BIT_AUDIF_CKG_AUTO_EN);
508 static inline int arch_audio_codec_digital_reg_enable(void)
513 ret = sci_glb_set(REG_AON_APB_APB_EB0, BIT_AUD_EB);
515 arch_audio_codec_audif_enable(0);
521 static inline int arch_audio_codec_digital_reg_disable(void)
526 arch_audio_codec_audif_disable();
527 sci_glb_clr(REG_AON_APB_APB_EB0, BIT_AUD_EB);
533 static inline int arch_audio_codec_analog_reg_enable(void)
539 sci_adi_write(ANA_REG_GLB_ARM_MODULE_EN, BIT_ANA_AUD_EN,
542 /* Disable Sleep Control Audio Power */
543 ret = sci_adi_write(ANA_REG_GLB_AUD_SLP_CTRL, 0, 0xFFFF);
550 static inline int arch_audio_codec_analog_reg_disable(void)
555 ret = sci_adi_write(ANA_REG_GLB_ARM_MODULE_EN, 0, BIT_ANA_AUD_EN);
561 static inline int arch_audio_codec_analog_enable(void)
567 int mask = BIT_CLK_AUD_6P5M_EN | BIT_CLK_AUDIF_EN;
568 sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, mask, mask);
569 sci_adi_write(ANA_REG_GLB_AUDIO_CTRL0, BIT_CLK_AUD_6P5M_TX_INV_EN,
570 BIT_CLK_AUD_6P5M_TX_INV_EN);
572 sci_adi_write(ANA_REG_GLB_RTC_CLK_EN, BIT_RTC_AUD_EN, BIT_RTC_AUD_EN);
574 sci_adi_write(ANA_REG_GLB_XTL_WAIT_CTRL, BIT_XTL_EN, BIT_XTL_EN);
576 /* FIXME: disable deepsleep force power off audio ldo */
577 sci_adi_write(ANA_REG_GLB_AUD_SLP_CTRL, 0, 0xFFFF);
582 static inline int arch_audio_codec_digital_enable(void)
587 /* internal digital 26M enable */
588 sci_glb_write(REG_AON_APB_SINDRV_CTRL, BIT_SINDRV_ENA, BIT_SINDRV_ENA);
594 static inline int arch_audio_codec_analog_disable(void)
600 int mask = BIT_CLK_AUD_6P5M_EN | BIT_CLK_AUDIF_EN;
601 sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, 0, mask);
602 sci_adi_write(ANA_REG_GLB_AUDIO_CTRL0, BIT_CLK_AUD_6P5M_TX_INV_EN,
603 BIT_CLK_AUD_6P5M_TX_INV_EN);
605 sci_adi_write(ANA_REG_GLB_RTC_CLK_EN, 0, BIT_RTC_AUD_EN);
606 /* 26M this is shared with adc, so we cann't close it */
607 /* sci_adi_write(ANA_REG_GLB_XTL_WAIT_CTRL, 0, BIT_XTL_EN); */
613 static inline int arch_audio_codec_digital_disable(void)
618 /* internal digital 26M disable */
619 sci_glb_write(REG_AON_APB_SINDRV_CTRL, 0, BIT_SINDRV_ENA);
626 static inline int arch_audio_codec_switch(int master)
632 case AUDIO_TO_AP_ARM_CTRL:
633 sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(0),
634 BITS_AUD_INT_SYS_SEL(3));
636 case AUDIO_TO_CP0_ARM_CTRL:
637 sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(1),
638 BITS_AUD_INT_SYS_SEL(3));
640 case AUDIO_TO_CP1_ARM_CTRL:
641 sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(2),
642 BITS_AUD_INT_SYS_SEL(3));
644 case AUDIO_TO_CP2_ARM_CTRL:
645 sci_glb_write(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(3),
646 BITS_AUD_INT_SYS_SEL(3));
648 case AUDIO_NO_CHANGE:
650 sci_glb_read(REG_AON_APB_VBC_CTRL, BITS_AUD_INT_SYS_SEL(3));
652 ret = AUDIO_TO_AP_ARM_CTRL;
653 } else if (ret == 1) {
654 ret = AUDIO_TO_CP0_ARM_CTRL;
655 } else if (ret == 2) {
656 ret = AUDIO_TO_CP1_ARM_CTRL;
657 } else if (ret == 3) {
658 ret = AUDIO_TO_CP2_ARM_CTRL;
670 static inline int arch_audio_codec_reset(void)
676 BIT_ANA_AUD_SOFT_RST | BIT_ANA_AUDTX_SOFT_RST |
677 BIT_ANA_AUDRX_SOFT_RST;
678 sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST);
679 sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST);
680 ret = sci_adi_write(ANA_REG_GLB_ARM_RST, mask, mask);
682 sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST);
683 sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST);
685 ret = sci_adi_write(ANA_REG_GLB_ARM_RST, 0, mask);
691 static inline int arch_audio_codec_digital_reset(void)
696 sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST);
697 sci_glb_set(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST);
699 sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUD_SOFT_RST);
700 sci_glb_clr(REG_AON_APB_APB_RST0, BIT_AUDIF_SOFT_RST);
706 static inline int arch_audio_codec_analog_reset(void)
712 BIT_ANA_AUD_SOFT_RST | BIT_ANA_AUDTX_SOFT_RST |
713 BIT_ANA_AUDRX_SOFT_RST;
714 ret = sci_adi_write(ANA_REG_GLB_ARM_RST, mask, mask);
717 ret = sci_adi_write(ANA_REG_GLB_ARM_RST, 0, mask);
723 static inline int arch_audio_sleep_xtl_enable(void)
727 sci_glb_set(REG_PMU_APB_SLEEP_XTLON_CTRL, BIT_AP_SLEEP_XTL_ON);
731 static inline int arch_audio_sleep_xtl_disable(void)
735 sci_glb_clr(REG_PMU_APB_SLEEP_XTLON_CTRL, BIT_AP_SLEEP_XTL_ON);
740 static inline int arch_audio_memory_sleep_enable(void)
744 sci_glb_clr(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_VBC(3));
745 sci_glb_clr(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_AUD(3));
751 static inline int arch_audio_memory_sleep_disable(void)
755 sci_glb_set(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_VBC(1));
756 sci_glb_set(REG_PMU_APB_MEM_PD_CFG0, BITS_AON_MEM_PD_CFG_AUD(1));
762 static inline int arch_audio_codec_adie_loop_clk_en(int on)
766 ret = sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, BIT_CLK_AUD_LOOP_EN, BIT_CLK_AUD_LOOP_EN);
768 ret = sci_adi_write(ANA_REG_GLB_ARM_CLK_EN, 0, BIT_CLK_AUD_LOOP_EN);
772 /* ------------------------------------------------------------------------- */
775 static inline const char *arch_audio_i2s_clk_name(int id)
798 static inline int arch_audio_i2s_enable(int id)
805 sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS0_EB);
808 sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS1_EB);
811 sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS2_EB);
814 sci_glb_set(REG_AP_APB_APB_EB, BIT_IIS3_EB);
825 static inline int arch_audio_i2s_disable(int id)
832 sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS0_EB);
835 sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS1_EB);
838 sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS2_EB);
841 sci_glb_clr(REG_AP_APB_APB_EB, BIT_IIS3_EB);
852 static inline int arch_audio_i2s_tx_dma_info(int id)
879 static inline int arch_audio_i2s_rx_dma_info(int id)
907 static inline int arch_audio_i2s_reset(int id)
914 sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS0_SOFT_RST);
916 sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS0_SOFT_RST);
919 sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS1_SOFT_RST);
921 sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS1_SOFT_RST);
924 sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS2_SOFT_RST);
926 sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS2_SOFT_RST);
929 sci_glb_set(REG_AP_APB_APB_RST, BIT_IIS3_SOFT_RST);
931 sci_glb_clr(REG_AP_APB_APB_RST, BIT_IIS3_SOFT_RST);
942 /* sc8830 AP IIS and CP IIS are different. AP IIS cann't switch to other master*/
943 static inline int arch_audio_i2s_switch(int id, int master)
949 case AUDIO_TO_AP_ARM_CTRL:
951 case AUDIO_NO_CHANGE:
952 ret = AUDIO_TO_AP_ARM_CTRL;