2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #ifndef __ASM_ARCH_HARDWARE_SCX35_H
15 #define __ASM_ARCH_HARDWARE_SCX35_H
17 #ifndef __ASM_ARCH_SCI_HARDWARE_H
18 #error "Don't include this file directly, include <mach/hardware.h>"
22 * 8830 internal I/O mappings
23 * 0x30000000-0x50000000 AON.
24 * We have the following mapping according to asic spec.
25 * We have set some trap gaps in the vaddr.
27 #define SCI_IOMAP_BASE 0xF5000000
29 #define SCI_IOMAP(x) (SCI_IOMAP_BASE + (x))
31 #define SCI_IOMEMMAP_BASE 0xcc800000
33 #define SCI_IOMEMMAP(x) (SCI_IOMEMMAP_BASE + (x))
36 #define SCI_ADDR(_b_, _o_) ( (u32)(_b_) + (_o_) )
39 #define LL_DEBUG_UART_PHYS SPRD_UART1_PHYS
40 #define LL_DEBUG_UART_BASE SPRD_UART1_BASE
42 //8830 mapping begin. From [0xEB000000 -- ]
43 #define SPRD_CORESIGHT_BASE SCI_IOMAP(0x0)
44 #define SPRD_CORESIGHT_PHYS 0x10000000
45 #define SPRD_CORESIGHT_SIZE SZ_64K
47 #define SPRD_CORE_BASE SCI_IOMAP(0x10000)
48 #define SPRD_CORE_PHYS 0x12000000
49 #define SPRD_CORE_SIZE SZ_64K
51 #define SPRD_DMA0_BASE SCI_IOMAP(0x112000)
52 #define SPRD_DMA0_PHYS 0X20100000
53 #define SPRD_DMA0_SIZE SZ_16K
55 #define SPRD_USB_BASE SCI_IOMAP(0x116000)
56 #define SPRD_USB_PHYS 0X20200000
57 #define SPRD_USB_SIZE SZ_4K
59 #define SPRD_SDIO0_BASE SCI_IOMAP(0x117000)
60 #define SPRD_SDIO0_PHYS 0X20300000
61 #define SPRD_SDIO0_SIZE SZ_4K
63 #define SPRD_SDIO1_BASE SCI_IOMAP(0x118000)
64 #define SPRD_SDIO1_PHYS 0X20400000
65 #define SPRD_SDIO1_SIZE SZ_4K
67 #define SPRD_MEMNAND_SYSTEM_BASE SCI_IOMEMMAP(0x00000)
68 #define SPRD_MEMNAND_SYSTEM_PHYS 0x8c800000
69 #define SPRD_MEMNAND_SYSTEM_SIZE (0xaa00000)
72 #define SPRD_MEMNAND_USERDATA_BASE SCI_IOMEMMAP(0xaa00000)
73 #define SPRD_MEMNAND_USERDATA_PHYS 0X97200000
74 #define SPRD_MEMNAND_USERDATA_SIZE (0x6a00000)
77 #define SPRD_MEMNAND_CACHE_BASE SCI_IOMEMMAP(0x6a00000+0xaa00000)
78 #define SPRD_MEMNAND_CACHE_PHYS (0X97200000+0x6a00000)
79 #define SPRD_MEMNAND_CACHE_SIZE (0x2400000)
81 #define SPRD_SDIO2_BASE SCI_IOMAP(0x11a000)
82 #define SPRD_SDIO2_PHYS 0X20500000
83 #define SPRD_SDIO2_SIZE SZ_4K
85 #define SPRD_EMMC_BASE SCI_IOMAP(0x11c000)
86 #define SPRD_EMMC_PHYS 0X20600000
87 #define SPRD_EMMC_SIZE SZ_4K
89 #define SPRD_DRM_BASE SCI_IOMAP(0x120000)
90 #define SPRD_DRM_PHYS 0X20700000
91 #define SPRD_DRM_SIZE SZ_4K
93 #define SPRD_LCDC_BASE SCI_IOMAP(0x122000)
94 #define SPRD_LCDC_PHYS 0X20800000
95 #define SPRD_LCDC_SIZE SZ_4K
97 #define SPRD_LCDC1_BASE SCI_IOMAP(0x124000)
98 #define SPRD_LCDC1_PHYS 0X20900000
99 #define SPRD_LCDC1_SIZE SZ_4K
101 #define SPRD_GSP_BASE SCI_IOMAP(0x126000)
102 #define SPRD_GSP_PHYS 0X20A00000
103 #define SPRD_GSP_SIZE SZ_4K
105 #define SPRD_NFC_BASE SCI_IOMAP(0x128000)
106 #define SPRD_NFC_PHYS 0X20B00000
107 #define SPRD_NFC_SIZE SZ_4K
109 #define SPRD_HWLOCK0_BASE SCI_IOMAP(0x12a000)
110 #define SPRD_HWLOCK0_PHYS 0X20c00000
111 #define SPRD_HWLOCK0_SIZE SZ_4K
113 #define SPRD_AHB_BASE SCI_IOMAP(0x130000)
114 #define SPRD_AHB_PHYS 0X20D00000
115 #define SPRD_AHB_SIZE SZ_64K
117 #define SPRD_BM0_BASE SCI_IOMAP(0x140000)
118 #define SPRD_BM0_PHYS 0X20E00000
119 #define SPRD_BM0_SIZE SZ_4K
121 #define SPRD_BM1_BASE SCI_IOMAP(0x142000)
122 #define SPRD_BM1_PHYS 0X20F00000
123 #define SPRD_BM1_SIZE SZ_4K
125 #define SPRD_BM2_BASE SCI_IOMAP(0x144000)
126 #define SPRD_BM2_PHYS 0X21000000
127 #define SPRD_BM2_SIZE SZ_4K
129 #define SPRD_DSI_BASE SCI_IOMAP(0x146000)
130 #define SPRD_DSI_PHYS 0X21800000
131 #define SPRD_DSI_SIZE SZ_4K
133 #define SPRD_GPS_BASE SCI_IOMAP(0x150000)
134 #define SPRD_GPS_PHYS 0X21C00000
135 #define SPRD_GPS_SIZE SZ_4K
137 #define SPRD_LPDDR2_BASE SCI_IOMAP(0x160000)
138 #define SPRD_LPDDR2_PHYS 0X30000000
139 #define SPRD_LPDDR2_SIZE SZ_4K
141 #define SPRD_LPDDR2_PHY_BASE SCI_IOMAP(0x170000)
142 #define SPRD_LPDDR2_PHY_PHYS 0X30010000
143 #define SPRD_LPDDR2_PHY_SIZE SZ_4K
145 #define SPRD_PUB_BASE SCI_IOMAP(0x180000)
146 #define SPRD_PUB_PHYS 0X30020000
147 #define SPRD_PUB_SIZE SZ_64K
149 #define SPRD_AXIBM0_BASE SCI_IOMAP(0x19e000)
150 #define SPRD_AXIBM0_PHYS 0X30040000
151 #define SPRD_AXIBM0_SIZE SZ_4K
153 #define SPRD_AXIBM1_BASE SCI_IOMAP(0x1a0000)
154 #define SPRD_AXIBM1_PHYS 0X30050000
155 #define SPRD_AXIBM1_SIZE (SZ_4K)
157 #define SPRD_AXIBM2_BASE SCI_IOMAP(0x1a2000)
158 #define SPRD_AXIBM2_PHYS 0X30060000
159 #define SPRD_AXIBM2_SIZE (SZ_4K)
161 #define SPRD_AXIBM3_BASE SCI_IOMAP(0x1a4000)
162 #define SPRD_AXIBM3_PHYS 0X30070000
163 #define SPRD_AXIBM3_SIZE (SZ_4K)
165 #define SPRD_AXIBM4_BASE SCI_IOMAP(0x1a6000)
166 #define SPRD_AXIBM4_PHYS 0X30080000
167 #define SPRD_AXIBM4_SIZE (SZ_4K)
169 #define SPRD_AXIBM5_BASE SCI_IOMAP(0x1a8000)
170 #define SPRD_AXIBM5_PHYS 0X30090000
171 #define SPRD_AXIBM5_SIZE (SZ_4K)
173 #define SPRD_AXIBM6_BASE SCI_IOMAP(0x1aa000)
174 #define SPRD_AXIBM6_PHYS 0X300A0000
175 #define SPRD_AXIBM6_SIZE (SZ_4K)
177 #define SPRD_AXIBM7_BASE SCI_IOMAP(0x1ac000)
178 #define SPRD_AXIBM7_PHYS 0X300B0000
179 #define SPRD_AXIBM7_SIZE (SZ_4K)
181 #define SPRD_AXIBM8_BASE SCI_IOMAP(0x1ae000)
182 #define SPRD_AXIBM8_PHYS 0X300C0000
183 #define SPRD_AXIBM8_SIZE (SZ_4K)
185 #define SPRD_AXIBM9_BASE SCI_IOMAP(0x1b0000)
186 #define SPRD_AXIBM9_PHYS 0X300D0000
187 #define SPRD_AXIBM9_SIZE (SZ_4K)
189 #define SPRD_AUDIO_BASE SCI_IOMAP(0x1c0000)
190 #define SPRD_AUDIO_PHYS 0X40000000
191 #define SPRD_AUDIO_SIZE SZ_8K
193 #define SPRD_AUDIO_IF_BASE SCI_IOMAP(0x1d0000)
194 #define SPRD_AUDIO_IF_PHYS 0X40010000
195 #define SPRD_AUDIO_IF_SIZE SZ_4K
197 #define SPRD_VBC_BASE SCI_IOMAP(0x1e0000)
198 #define SPRD_VBC_PHYS 0X40020000
199 #define SPRD_VBC_SIZE SZ_4K + SZ_8K
201 #define SPRD_SYSTIMER_CMP_BASE SCI_IOMAP(0x1f2000)
202 #define SPRD_SYSTIMER_CMP_PHYS 0X40040000
203 #define SPRD_SYSTIMER_CMP_SIZE SZ_4K
205 #define SPRD_GPTIMER0_BASE SCI_IOMAP(0x1f4000)
206 #define SPRD_GPTIMER0_PHYS 0X40050000
207 #define SPRD_GPTIMER0_SIZE SZ_4K
209 #define SPRD_HWLOCK1_BASE SCI_IOMAP(0x1f6000)
210 #define SPRD_HWLOCK1_PHYS 0X40060000
211 #define SPRD_HWLOCK1_SIZE SZ_4K
213 #define SPRD_RFSPI_BASE SCI_IOMAP(0x1f8000)
214 #define SPRD_RFSPI_PHYS 0X40070000
215 #define SPRD_RFSPI_SIZE SZ_4K
217 #define SPRD_I2C_BASE SCI_IOMAP(0x1fa000)
218 #define SPRD_I2C_PHYS 0X40080000
219 #define SPRD_I2C_SIZE SZ_4K
221 #define SPRD_INT_BASE SCI_IOMAP(0x1fc000)
222 #define SPRD_INT_PHYS 0X40200000
223 #define SPRD_INT_SIZE SZ_4K
225 #define SPRD_EIC_BASE SCI_IOMAP(0x200000)
226 #define SPRD_EIC_PHYS 0X40210000
227 #define SPRD_EIC_SIZE SZ_4K
229 #define SPRD_APTIMER0_BASE SCI_IOMAP(0x202000)
230 #define SPRD_APTIMER0_PHYS 0X40220000
231 #define SPRD_APTIMER0_SIZE SZ_4K
233 #define SPRD_SYSCNT_BASE SCI_IOMAP(0x204000)
234 #define SPRD_SYSCNT_PHYS 0X40230000
235 #define SPRD_SYSCNT_SIZE SZ_4K
237 #define SPRD_UIDEFUSE_BASE SCI_IOMAP(0x206000)
238 #define SPRD_UIDEFUSE_PHYS 0X40240000
239 #define SPRD_UIDEFUSE_SIZE SZ_4K
241 #define SPRD_KPD_BASE SCI_IOMAP(0x208000)
242 #define SPRD_KPD_PHYS 0X40250000
243 #define SPRD_KPD_SIZE SZ_4K
245 #define SPRD_PWM_BASE SCI_IOMAP(0x20a000)
246 #define SPRD_PWM_PHYS 0X40260000
247 #define SPRD_PWM_SIZE SZ_4K
249 #define SPRD_FM_BASE SCI_IOMAP(0x210000)
250 #define SPRD_FM_PHYS 0X40270000
251 #define SPRD_FM_SIZE SZ_4K
253 #define SPRD_GPIO_BASE SCI_IOMAP(0x220000)
254 #define SPRD_GPIO_PHYS 0X40280000
255 #define SPRD_GPIO_SIZE SZ_4K
257 #define SPRD_WDG_BASE SCI_IOMAP(0x222000)
258 #define SPRD_WDG_PHYS 0X40290000
259 #define SPRD_WDG_SIZE SZ_4K
261 #define SPRD_PIN_BASE SCI_IOMAP(0x224000)
262 #define SPRD_PIN_PHYS 0X402A0000
263 #define SPRD_PIN_SIZE SZ_4K
265 #define SPRD_PMU_BASE SCI_IOMAP(0x230000)
266 #define SPRD_PMU_PHYS 0X402B0000
267 #define SPRD_PMU_SIZE SZ_64K
269 #define SPRD_IPI_BASE SCI_IOMAP(0x240000)
270 #define SPRD_IPI_PHYS 0X402C0000
271 #define SPRD_IPI_SIZE SZ_4K
273 #define SPRD_AONCKG_BASE SCI_IOMAP(0x242000)
274 #define SPRD_AONCKG_PHYS 0X402D0000
275 #define SPRD_AONCKG_SIZE SZ_4K
277 #define SPRD_AONAPB_BASE SCI_IOMAP(0x250000)
278 #define SPRD_AONAPB_PHYS 0X402E0000
279 #define SPRD_AONAPB_SIZE SZ_64K
281 #define SPRD_THM_BASE SCI_IOMAP(0x260000)
282 #define SPRD_THM_PHYS 0X402F0000
283 #define SPRD_THM_SIZE SZ_4K
285 #define SPRD_AVSCA7_BASE SCI_IOMAP(0x270000)
286 #define SPRD_AVSCA7_PHYS 0X40300000
287 #define SPRD_AVSCA7_SIZE SZ_4K
289 #define SPRD_AVSTOP_BASE SCI_IOMAP(0x280000)
290 #define SPRD_AVSTOP_PHYS 0X40310000
291 #define SPRD_AVSTOP_SIZE SZ_4K
294 #define SPRD_CA7WDG_BASE SCI_IOMAP(0x290000)
295 #define SPRD_CA7WDG_PHYS 0X40320000
296 #define SPRD_CA7WDG_SIZE SZ_4K
298 #define SPRD_APTIMER1_BASE SCI_IOMAP(0x292000)
299 #define SPRD_APTIMER1_PHYS 0X40330000
300 #define SPRD_APTIMER1_SIZE SZ_4K
302 #define SPRD_APTIMER2_BASE SCI_IOMAP(0x294000)
303 #define SPRD_APTIMER2_PHYS 0X40340000
304 #define SPRD_APTIMER2_SIZE SZ_4K
307 #define SPRD_CA7TS0_BASE SCI_IOMAP(0x2a0000)
308 #define SPRD_CA7TS0_PHYS 0X40400000
309 #define SPRD_CA7TS0_SIZE SZ_4K
311 #define SPRD_CA7TS1_BASE SCI_IOMAP(0x2b0000)
312 #define SPRD_CA7TS1_PHYS 0X40410000
313 #define SPRD_CA7TS1_SIZE SZ_4K
315 #define SPRD_MALI_BASE SCI_IOMAP(0x2c0000)
316 #define SPRD_MALI_PHYS 0X60000000
317 #define SPRD_MALI_SIZE SZ_4K
319 #define SPRD_GPUAPB_BASE SCI_IOMAP(0x2d0000)
320 #define SPRD_GPUAPB_PHYS 0X60100000
321 #define SPRD_GPUAPB_SIZE SZ_4K
323 #define SPRD_GPUCKG_BASE SCI_IOMAP(0x2e0000)
324 #define SPRD_GPUCKG_PHYS 0X60200000
325 #define SPRD_GPUCKG_SIZE SZ_4K
327 #define SPRD_DCAM_BASE SCI_IOMAP(0x2f0000)
328 #define SPRD_DCAM_PHYS 0X60800000
329 #define SPRD_DCAM_SIZE SZ_64K
331 #define SPRD_VSP_BASE SCI_IOMAP(0x300000)
332 #define SPRD_VSP_PHYS 0X60900000
333 #define SPRD_VSP_SIZE (SZ_32K + SZ_16K)
335 #define SPRD_ISP_BASE SCI_IOMAP(0x310000)
336 #define SPRD_ISP_PHYS 0X60A00000
337 #define SPRD_ISP_SIZE SZ_32K
339 #define SPRD_JPG_BASE SCI_IOMAP(0x320000)
340 #define SPRD_JPG_PHYS 0X60B00000
341 #define SPRD_JPG_SIZE SZ_32K
343 #define SPRD_CSI2_BASE SCI_IOMAP(0x330000)
344 #define SPRD_CSI2_PHYS 0X60C00000
345 #define SPRD_CSI2_SIZE SZ_4K
347 #define SPRD_MMAHB_BASE SCI_IOMAP(0x340000)
348 #define SPRD_MMAHB_PHYS 0X60D00000
349 #define SPRD_MMAHB_SIZE SZ_16K
351 #define SPRD_MMCKG_BASE SCI_IOMAP(0x350000)
352 #define SPRD_MMCKG_PHYS 0X60E00000
353 #define SPRD_MMCKG_SIZE SZ_4K
355 #define SPRD_UART0_BASE SCI_IOMAP(0x360000)
356 #define SPRD_UART0_PHYS 0X70000000
357 #define SPRD_UART0_SIZE SZ_4K
359 #define SPRD_UART1_BASE SCI_IOMAP(0x362000)
360 #define SPRD_UART1_PHYS 0X70100000
361 #define SPRD_UART1_SIZE SZ_4K
363 #define SPRD_UART2_BASE SCI_IOMAP(0x364000)
364 #define SPRD_UART2_PHYS 0X70200000
365 #define SPRD_UART2_SIZE SZ_4K
367 #define SPRD_UART3_BASE SCI_IOMAP(0x366000)
368 #define SPRD_UART3_PHYS 0X70300000
369 #define SPRD_UART3_SIZE SZ_4K
371 #define SPRD_UART4_BASE SCI_IOMAP(0x368000)
372 #define SPRD_UART4_PHYS 0X70400000
373 #define SPRD_UART4_SIZE SZ_4K
375 #define SPRD_I2C0_BASE SCI_IOMAP(0x36a000)
376 #define SPRD_I2C0_PHYS 0X70500000
377 #define SPRD_I2C0_SIZE SZ_4K
379 #define SPRD_I2C1_BASE SCI_IOMAP(0x36c000)
380 #define SPRD_I2C1_PHYS 0X70600000
381 #define SPRD_I2C1_SIZE SZ_4K
383 #define SPRD_I2C2_BASE SCI_IOMAP(0x370000)
384 #define SPRD_I2C2_PHYS 0X70700000
385 #define SPRD_I2C2_SIZE SZ_4K
387 #define SPRD_I2C3_BASE SCI_IOMAP(0x372000)
388 #define SPRD_I2C3_PHYS 0X70800000
389 #define SPRD_I2C3_SIZE SZ_4K
391 #define SPRD_I2C4_BASE SCI_IOMAP(0x374000)
392 #define SPRD_I2C4_PHYS 0X70900000
393 #define SPRD_I2C4_SIZE SZ_4K
395 #define SPRD_SPI0_BASE SCI_IOMAP(0x376000)
396 #define SPRD_SPI0_PHYS 0X70A00000
397 #define SPRD_SPI0_SIZE SZ_4K
399 #define SPRD_SPI1_BASE SCI_IOMAP(0x378000)
400 #define SPRD_SPI1_PHYS 0X70B00000
401 #define SPRD_SPI1_SIZE SZ_4K
403 #define SPRD_SPI2_BASE SCI_IOMAP(0x37a000)
404 #define SPRD_SPI2_PHYS 0X70C00000
405 #define SPRD_SPI2_SIZE SZ_4K
407 #define SPRD_IIS0_BASE SCI_IOMAP(0x37c000)
408 #define SPRD_IIS0_PHYS 0X70D00000
409 #define SPRD_IIS0_SIZE SZ_4K
411 #define SPRD_IIS1_BASE SCI_IOMAP(0x380000)
412 #define SPRD_IIS1_PHYS 0X70E00000
413 #define SPRD_IIS1_SIZE SZ_4K
415 #define SPRD_IIS2_BASE SCI_IOMAP(0x382000)
416 #define SPRD_IIS2_PHYS 0X70F00000
417 #define SPRD_IIS2_SIZE SZ_4K
419 #define SPRD_IIS3_BASE SCI_IOMAP(0x384000)
420 #define SPRD_IIS3_PHYS 0X71000000
421 #define SPRD_IIS3_SIZE SZ_4K
423 #define SPRD_SIM0_BASE SCI_IOMAP(0x390000)
424 #define SPRD_SIM0_PHYS 0X71100000
425 #define SPRD_SIM0_SIZE SZ_4K
427 #define SPRD_APBCKG_BASE SCI_IOMAP(0x3a0000)
428 #define SPRD_APBCKG_PHYS 0X71200000
429 #define SPRD_APBCKG_SIZE SZ_4K
431 #define SPRD_APBREG_BASE SCI_IOMAP(0x3b0000)
432 #define SPRD_APBREG_PHYS 0X71300000
433 #define SPRD_APBREG_SIZE SZ_64K
435 #define SPRD_INTC0_BASE SCI_IOMAP(0x3c0000)
436 #define SPRD_INTC0_PHYS 0X71400000
437 #define SPRD_INTC0_SIZE SZ_4K
439 #define SPRD_INTC1_BASE SCI_IOMAP(0x3c2000)
440 #define SPRD_INTC1_PHYS 0X71500000
441 #define SPRD_INTC1_SIZE SZ_4K
443 #define SPRD_INTC2_BASE SCI_IOMAP(0x3c4000)
444 #define SPRD_INTC2_PHYS 0X71600000
445 #define SPRD_INTC2_SIZE SZ_4K
447 #define SPRD_INTC3_BASE SCI_IOMAP(0x3c6000)
448 #define SPRD_INTC3_PHYS 0X71700000
449 #define SPRD_INTC3_SIZE SZ_4K
451 #define SPRD_IRAM0_BASE SCI_IOMAP(0x3d0000)
452 #define SPRD_IRAM0_PHYS 0X0
453 #define SPRD_IRAM0_SIZE SZ_4K
455 #define SPRD_IRAM0H_BASE SCI_IOMAP(0x3d1000)
456 #define SPRD_IRAM0H_PHYS 0X1000
457 #define SPRD_IRAM0H_SIZE SZ_4K
460 #define SPRD_IRAM1_BASE SCI_IOMAP(0x3e0000)
461 #define SPRD_IRAM1_PHYS 0X50000000
462 #define SPRD_IRAM1_SIZE (SZ_32K + SZ_16K + SZ_4K)
464 #define SPRD_IRAM1_BASE SCI_IOMAP(0x3d4000)
465 #define SPRD_IRAM1_PHYS 0x50000000
466 #define SPRD_IRAM1_SIZE (SZ_8K + SZ_4K)
468 #define SPRD_IRAM2_BASE SCI_IOMAP(0x3d7000)
469 #define SPRD_IRAM2_PHYS 0x50004000
470 #define SPRD_IRAM2_SIZE (SZ_32K + SZ_4K)
472 /*begin mapping adie master and slave address */
473 #define SPRD_ADI_BASE SCI_IOMAP(0x3f0000)
474 #define SPRD_ADI_PHYS 0X40030000
475 #define SPRD_ADI_SIZE (SZ_4K)
477 #define SPRD_ADISLAVE_BASE SCI_IOMAP(0x3f0000 + SZ_32K)
478 #define SPRD_ADISLAVE_PHYS 0X40038000
479 #define SPRD_ADISLAVE_SIZE (SZ_4K)
481 #if defined(CONFIG_ARCH_SCX15)
482 #define SPRD_ZIPENC_BASE SCI_IOMAP(0x3fc000)
483 #define SPRD_ZIPENC_PHYS 0X21200000
484 #define SPRD_ZIPENC_SIZE (SZ_4K)
485 #define SPRD_ZIPDEC_BASE SCI_IOMAP(0x400000)
486 #define SPRD_ZIPDEC_PHYS 0X21300000
487 #define SPRD_ZIPDEC_SIZE (SZ_4K)
489 #define SPRD_GSPMMU_BASE SCI_IOMAP(0x410000)
490 #define SPRD_GSPMMU_PHYS 0X21400000
491 #define SPRD_GSPMMU_SIZE (SZ_64K + SZ_4K)
493 #define SPRD_MMMMU_BASE SCI_IOMAP(0x430000)
494 #define SPRD_MMMMU_PHYS 0X60F00000
495 #define SPRD_MMMMU_SIZE (SZ_64K + SZ_4K)
498 #if defined(CONFIG_ARCH_SCX30G)
499 #define SPRD_ZIPENC_BASE SCI_IOMAP(0x3fc000)
500 #define SPRD_ZIPENC_PHYS 0X21200000
501 #define SPRD_ZIPENC_SIZE (SZ_4K)
503 #define SPRD_ZIPDEC_BASE SCI_IOMAP(0x400000)
504 #define SPRD_ZIPDEC_PHYS 0X21300000
505 #define SPRD_ZIPDEC_SIZE (SZ_4K)
507 #define SPRD_GSPMMU_BASE SCI_IOMAP(0x410000)
508 #define SPRD_GSPMMU_PHYS 0X21400000
509 #define SPRD_GSPMMU_SIZE (SZ_64K)
511 #define SPRD_MMMMU_BASE SCI_IOMAP(0x430000)
512 #define SPRD_MMMMU_PHYS 0X60F00000
513 #define SPRD_MMMMU_SIZE (SZ_128K + SZ_4K)
516 #define CORE_GIC_CPU_VA (SPRD_CORE_BASE + 0x2000)
517 #define CORE_GIC_DIS_VA (SPRD_CORE_BASE + 0x1000)
519 #ifdef CONFIG_ARCH_SCX30G
520 #define HOLDING_PEN_VADDR (SPRD_AHB_BASE + 0x14)
522 #define HOLDING_PEN_VADDR (SPRD_AHB_BASE + 0x4c)
524 #define CPU_JUMP_VADDR (HOLDING_PEN_VADDR + 0X4)
527 /* registers for watchdog ,RTC, touch panel, aux adc, analog die... */
528 #define SPRD_MISC_BASE ((unsigned int)SPRD_ADI_BASE)
529 #define SPRD_MISC_PHYS ((unsigned int)SPRD_ADI_PHYS)
531 #define ANA_PWM_BASE (SPRD_ADISLAVE_BASE + 0x20 )
532 #define ANA_WDG_BASE (SPRD_ADISLAVE_BASE + 0x40 )
533 #define ANA_RTC_BASE (SPRD_ADISLAVE_BASE + 0x80 )
534 #define ANA_EIC_BASE (SPRD_ADISLAVE_BASE + 0x100 )
535 #define ANA_PIN_BASE (SPRD_ADISLAVE_BASE + 0x180 )
536 #define ANA_THM_BASE (SPRD_ADISLAVE_BASE + 0x280 )
537 #define ADC_BASE (SPRD_ADISLAVE_BASE + 0x300 )
538 #define ANA_CTL_INT_BASE (SPRD_ADISLAVE_BASE + 0x380 )
539 #define ANA_BTLC_INT_BASE (SPRD_ADISLAVE_BASE + 0x3c0 )
540 #define ANA_AUDIFA_INT_BASE (SPRD_ADISLAVE_BASE + 0x400 )
541 #define ANA_GPIO_INT_BASE (SPRD_ADISLAVE_BASE + 0x480 )
542 #define ANA_FPU_INT_BASE (SPRD_ADISLAVE_BASE + 0x500 )
543 #define ANA_AUDCFGA_INT_BASE (SPRD_ADISLAVE_BASE + 0x600 )
544 #define ANA_HDT_INT_BASE (SPRD_ADISLAVE_BASE + 0x700 )
545 #define ANA_CTL_GLB_BASE (SPRD_ADISLAVE_BASE + 0x800 )
547 #define SPRD_ANA_PIN_BASE ((unsigned int)SPRD_ADI_BASE + 0x8180)
549 #ifndef REGS_AHB_BASE
550 #define REGS_AHB_BASE ( SPRD_AHB_BASE + 0x200)
553 #define SPRD_IRAM_BASE SPRD_IRAM0_BASE + 0x1000
554 #define SPRD_IRAM_PHYS SPRD_IRAM0_PHYS + 0x1000
555 #define SPRD_IRAM_SIZE SZ_4K
556 #define SPRD_GREG_BASE SPRD_AONAPB_BASE
557 #define SPRD_GREG_PHYS SPRD_AONAPB_PHYS
558 #define SPRD_GREG_SIZE SZ_64K
560 #ifndef REGS_GLB_BASE
561 #define REGS_GLB_BASE ( SPRD_GREG_BASE )
562 #define ANA_REGS_GLB_BASE ( ANA_CTL_GLB_BASE )
565 #define CHIP_ID_LOW_REG (SPRD_AHB_BASE + 0xfc)
567 #define SPRD_GPTIMER_BASE SPRD_GPTIMER0_BASE
568 //#define REG_GLB_GEN0 SPRD_AONAPB_BASE
569 #define SPRD_EFUSE_BASE SPRD_UIDEFUSE_BASE
571 #define REGS_AP_AHB_BASE SPRD_AHB_BASE
572 #define REGS_AP_APB_BASE SPRD_APBREG_BASE
573 #define REGS_AON_APB_BASE SPRD_AONAPB_BASE
574 #define REGS_GPU_APB_BASE SPRD_GPUAPB_BASE
575 #define REGS_MM_AHB_BASE SPRD_MMAHB_BASE
576 #define REGS_PMU_APB_BASE SPRD_PMU_BASE
577 #define REGS_AON_CLK_BASE SPRD_AONCKG_BASE
578 #define REGS_AP_CLK_BASE SPRD_APBCKG_BASE
579 #define REGS_GPU_CLK_BASE SPRD_GPUCKG_BASE
580 #define REGS_MM_CLK_BASE SPRD_MMCKG_BASE
581 #define REGS_PUB_APB_BASE SPRD_PUB_BASE
583 #if defined(CONFIG_ARCH_SCX15)
584 #if defined(CONFIG_SPRD_MODEM_TD)
585 #define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M)
586 #define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M)
587 #define CPT_TOTAL_SIZE (SZ_1M * 18)
588 #define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K)
589 #define CPT_RING_SIZE (SZ_4K)
590 #define CPT_SMEM_SIZE (SZ_1M + SZ_256K)
591 #define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 168 * SZ_1M)
592 #define WCN_TOTAL_SIZE 0x281000//(SZ_1M * 5)
593 #define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K)
594 #define WCN_RING_SIZE (SZ_4K)
595 #define WCN_SMEM_SIZE (SZ_512K + SZ_256K)
597 #define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M)
598 #define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M)
599 #define CPW_TOTAL_SIZE 0x18A0000 //(SZ_1M * 32)
600 #define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K)
601 #define CPW_RING_SIZE (SZ_4K)
602 #define CPW_SMEM_SIZE (SZ_1M + SZ_256K)
603 #define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 168 * SZ_1M)
604 #define WCN_TOTAL_SIZE 0x281000//(SZ_1M * 5)
605 #define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K)
606 #define WCN_RING_SIZE (SZ_4K)
607 #define WCN_SMEM_SIZE (SZ_512K + SZ_256K)
610 #define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M)
612 #define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M)
613 #define CPT_TOTAL_SIZE (SZ_1M * 18)
614 #define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K)
615 #define CPT_RING_SIZE (SZ_4K)
616 #define CPT_SMEM_SIZE (SZ_1M + SZ_256K)
618 #ifdef CONFIG_ARCH_SCX30G
619 #define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M)
621 #define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 256 * SZ_1M)
623 #if defined(CONFIG_MODEM_W_MEMCUT)
624 #define CPW_TOTAL_SIZE (SZ_1M * 28)
625 #elif defined CONFIG_ARCH_SCX30G
626 #define CPW_TOTAL_SIZE (SZ_1M * 27)
628 #define CPW_TOTAL_SIZE (SZ_1M * 33)
630 #define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K)
631 #define CPW_RING_SIZE (SZ_4K)
632 #define CPW_SMEM_SIZE (SZ_1M + SZ_256K)
634 #if defined(CONFIG_ARCH_SCX30G)
635 #define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 168 * SZ_1M)//Tshark moves cp2 to 168M
636 #define WCN_TOTAL_SIZE 0x201000//Tshark 8830gea memcut to 2M+4k
638 #define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M)
639 #define WCN_TOTAL_SIZE 0x281000//(SZ_1M * 5)
641 #define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K)
642 #define WCN_RING_SIZE (SZ_4K)
643 #define WCN_SMEM_SIZE (SZ_512K + SZ_256K)