2 * Copyright (C) 2012 Spreadtrum Communications Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #ifndef __GPIO_SC8810_H__
15 #define __GPIO_SC8810_H__
17 #ifndef __ASM_ARCH_BOARD_H
18 #error "Don't include this file directly, include <mach/board.h>"
21 #define GPIO_TOUCH_RESET 145
22 #define GPIO_TOUCH_IRQ 144
24 #define GPIO_MAIN_SENSOR_RESET 44
25 #define GPIO_MAIN_SENSOR_PWN 46
26 #define GPIO_SUB_SENSOR_RESET 45
27 #define GPIO_SUB_SENSOR_PWN 47
29 #define USB_OTG_CABLE_DETECT 126
31 #define SPRD_FLASH_OFST 0x890
32 #define SPRD_FLASH_CTRL_BIT 0x8000
33 #define SPRD_FLASH_LOW_VAL 0x3
34 #define SPRD_FLASH_HIGH_VAL 0xF
35 #define SPRD_FLASH_LOW_CUR 110
36 #define SPRD_FLASH_HIGH_CUR 470
38 #define GPIO_KEY_VOLUMEDOWN 124
39 #define GPIO_KEY_VOLUMEUP 125
41 #define EIC_CHARGER_DETECT (A_EIC_START + 0)
42 #define EIC_POWER_PBINT2 (A_EIC_START + 1)
43 #define EIC_POWER_PBINT (A_EIC_START + 2)
44 #define EIC_AUD_HEAD_BUTTON (A_EIC_START + 3)
45 #define EIC_CHG_CV_STATE (A_EIC_START + 4)
46 #define EIC_AUD_HEAD_INST (A_EIC_START + 5)
47 #define EIC_VCHG_OVI (A_EIC_START + 6)
48 #define EIC_VBAT_OVI (A_EIC_START + 7)
49 #define EIC_AUD_HEAD_INST2 (A_EIC_START + 8)
51 #define EIC_KEY_POWER (EIC_POWER_PBINT)
53 #define HEADSET_BUTTON_GPIO (EIC_AUD_HEAD_BUTTON)
54 #define HEADSET_DETECT_GPIO (EIC_AUD_HEAD_INST2)
55 #define HEADSET_SWITCH_GPIO 0
57 #define HEADSET_IRQ_TRIGGER_LEVEL_DETECT 1
58 #define HEADSET_IRQ_TRIGGER_LEVEL_BUTTON 1
60 #define HEADSET_ADC_MIN_KEY_MEDIA 0
61 #define HEADSET_ADC_MAX_KEY_MEDIA 170
62 #define HEADSET_ADC_MIN_KEY_VOLUMEUP 171
63 #define HEADSET_ADC_MAX_KEY_VOLUMEUP 430
64 #define HEADSET_ADC_MIN_KEY_VOLUMEDOWN 431
65 #define HEADSET_ADC_MAX_KEY_VOLUMEDOWN 760
66 #define HEADSET_ADC_THRESHOLD_3POLE_DETECT 100
67 #define HEADSET_ADC_THRESHOLD_4POLE_DETECT 3100
68 #define HEADSET_IRQ_THRESHOLD_BUTTON 1
69 #define HEADSET_HEADMICBIAS_VOLTAGE 3000000
71 #define SPI0_CMMB_CS_GPIO 32
72 #define SPI1_WIFI_CS_GPIO 44
75 #define MSENSOR_DRDY_GPIO 53
76 #define GPIO_PLSENSOR_IRQ 213
77 /*For bcm4343 power on/off and sleep/wake */
78 #define GPIO_BT_RESET 122
79 #define GPIO_BT_POWER 131
80 #define GPIO_BT2AP_WAKE 133
81 #define GPIO_AP2BT_WAKE 132
83 /*#define GPIO_BT_RESET 194 */
84 #define GPIO_WIFI_POWERON 189
85 #define GPIO_WIFI_SHUTDOWN 130
86 #define GPIO_WIFI_IRQ 97
88 #define GPIO_PROX_INT 140
89 #define GPIO_GPS_ONOFF 174
91 #define GPIO_SDIO_DETECT 75
93 #define SPRD_PIN_SDIO0_OFFSET 0x01E0
94 #define SPRD_PIN_SDIO0_SIZE 7
95 #define SPRD_PIN_SDIO0_D3_INDEX 0
96 #define SPRD_PIN_SDIO0_D3_GPIO 100
97 #define SPRD_PIN_SDIO0_SD_FUNC 0
98 #define SPRD_PIN_SDIO0_GPIO_FUNC 3
100 /*#define CP related featrue */
101 #define SIPC_SMEM_ADDR (CONFIG_PHYS_OFFSET + 120 * SZ_1M)
103 #define CPT_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M)
104 #define CPT_TOTAL_SIZE (SZ_1M * 18)
105 #define CPT_RING_ADDR (CPT_START_ADDR + CPT_TOTAL_SIZE - SZ_4K)
106 #define CPT_RING_SIZE (SZ_4K)
107 #define CPT_SMEM_SIZE (SZ_1M * 2)
109 #define CPW_START_ADDR (CONFIG_PHYS_OFFSET + 150* SZ_1M)
110 #define CPW_TOTAL_SIZE (SZ_1M * 33)
111 #define CPW_RING_ADDR (CPW_START_ADDR + CPW_TOTAL_SIZE - SZ_4K)
112 #define CPW_RING_SIZE (SZ_4K)
113 #define CPW_SMEM_SIZE (SZ_1M * 2)
115 #define WCN_START_ADDR (CONFIG_PHYS_OFFSET + 320 * SZ_1M)
116 #define WCN_TOTAL_SIZE (SZ_1M * 5)
117 #define WCN_RING_ADDR (WCN_START_ADDR + WCN_TOTAL_SIZE - SZ_4K)
118 #define WCN_RING_SIZE (SZ_4K)
119 #define WCN_SMEM_SIZE (SZ_1M * 2)
121 #define GGE_START_ADDR (CONFIG_PHYS_OFFSET + 128 * SZ_1M)
122 #define GGE_TOTAL_SIZE (SZ_1M * 22)
123 #define GGE_RING_ADDR (GGE_START_ADDR + GGE_TOTAL_SIZE - SZ_4K)
124 #define GGE_RING_SIZE (SZ_4K)
125 #define GGE_SMEM_SIZE (SZ_1M * 2)
127 #define LTE_START_ADDR (CONFIG_PHYS_OFFSET + 150 * SZ_1M)
128 #define LTE_TOTAL_SIZE (SZ_1M * 83)
129 #define LTE_RING_ADDR (LTE_START_ADDR + LTE_TOTAL_SIZE - SZ_4K)
130 #define LTE_RING_SIZE (SZ_4K)
131 #define LTE_SMEM_SIZE (SZ_1M * 2)