1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 * Microsemi Ocelot Switch driver
3 * Copyright (c) 2019 Microsemi Corporation
6 #ifndef _OCELOT_VCAP_H_
7 #define _OCELOT_VCAP_H_
9 #include <soc/mscc/ocelot.h>
11 /* Cookie definitions for private VCAP filters installed by the driver.
12 * Must be unique per VCAP block.
14 #define OCELOT_VCAP_ES0_TAG_8021Q_RXVLAN(ocelot, port, upstream) ((upstream) << 16 | (port))
15 #define OCELOT_VCAP_IS1_TAG_8021Q_TXVLAN(ocelot, port) (port)
16 #define OCELOT_VCAP_IS2_TAG_8021Q_TXVLAN(ocelot, port) (port)
17 #define OCELOT_VCAP_IS2_MRP_REDIRECT(ocelot, port) ((ocelot)->num_phys_ports + (port))
18 #define OCELOT_VCAP_IS2_MRP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2)
19 #define OCELOT_VCAP_IS2_L2_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 1)
20 #define OCELOT_VCAP_IS2_IPV4_GEN_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 2)
21 #define OCELOT_VCAP_IS2_IPV4_EV_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 3)
22 #define OCELOT_VCAP_IS2_IPV6_GEN_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 4)
23 #define OCELOT_VCAP_IS2_IPV6_EV_PTP_TRAP(ocelot) ((ocelot)->num_phys_ports * 2 + 5)
25 /* =================================================================
27 * =================================================================
37 #define OCELOT_NUM_VCAP_BLOCKS __VCAP_COUNT
40 u16 tg_width; /* Type-group width (in bits) */
41 u16 sw_count; /* Sub word count */
42 u16 entry_count; /* Entry count */
43 u16 entry_words; /* Number of entry words */
44 u16 entry_width; /* Entry width (in bits) */
45 u16 action_count; /* Action count */
46 u16 action_words; /* Number of action words */
47 u16 action_width; /* Action width (in bits) */
48 u16 action_type_width; /* Action type width (in bits) */
50 u16 width; /* Action type width (in bits) */
51 u16 count; /* Action type sub word count */
53 u16 counter_words; /* Number of counter words */
54 u16 counter_width; /* Counter width (in bits) */
56 enum ocelot_target target;
58 const struct vcap_field *keys;
59 const struct vcap_field *actions;
62 /* VCAP Type-Group values */
63 #define VCAP_TG_NONE 0 /* Entry is invalid */
64 #define VCAP_TG_FULL 1 /* Full entry */
65 #define VCAP_TG_HALF 2 /* Half entry */
66 #define VCAP_TG_QUARTER 3 /* Quarter entry */
68 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD(x) (((x) << 22) & GENMASK(24, 22))
69 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_M GENMASK(24, 22)
70 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CMD_X(x) (((x) & GENMASK(24, 22)) >> 22)
71 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ENTRY_DIS BIT(21)
72 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ACTION_DIS BIT(20)
73 #define VCAP_CORE_UPDATE_CTRL_UPDATE_CNT_DIS BIT(19)
74 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR(x) (((x) << 3) & GENMASK(18, 3))
75 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_M GENMASK(18, 3)
76 #define VCAP_CORE_UPDATE_CTRL_UPDATE_ADDR_X(x) (((x) & GENMASK(18, 3)) >> 3)
77 #define VCAP_CORE_UPDATE_CTRL_UPDATE_SHOT BIT(2)
78 #define VCAP_CORE_UPDATE_CTRL_CLEAR_CACHE BIT(1)
79 #define VCAP_CORE_UPDATE_CTRL_MV_TRAFFIC_IGN BIT(0)
81 #define VCAP_CORE_MV_CFG_MV_NUM_POS(x) (((x) << 16) & GENMASK(31, 16))
82 #define VCAP_CORE_MV_CFG_MV_NUM_POS_M GENMASK(31, 16)
83 #define VCAP_CORE_MV_CFG_MV_NUM_POS_X(x) (((x) & GENMASK(31, 16)) >> 16)
84 #define VCAP_CORE_MV_CFG_MV_SIZE(x) ((x) & GENMASK(15, 0))
85 #define VCAP_CORE_MV_CFG_MV_SIZE_M GENMASK(15, 0)
87 #define VCAP_CACHE_ENTRY_DAT_RSZ 0x4
89 #define VCAP_CACHE_MASK_DAT_RSZ 0x4
91 #define VCAP_CACHE_ACTION_DAT_RSZ 0x4
93 #define VCAP_CACHE_CNT_DAT_RSZ 0x4
95 #define VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
97 #define TCAM_BIST_CTRL_TCAM_BIST BIT(1)
98 #define TCAM_BIST_CTRL_TCAM_INIT BIT(0)
100 #define TCAM_BIST_CFG_TCAM_BIST_SOE_ENA BIT(8)
101 #define TCAM_BIST_CFG_TCAM_HCG_DIS BIT(7)
102 #define TCAM_BIST_CFG_TCAM_CG_DIS BIT(6)
103 #define TCAM_BIST_CFG_TCAM_BIAS(x) ((x) & GENMASK(5, 0))
104 #define TCAM_BIST_CFG_TCAM_BIAS_M GENMASK(5, 0)
106 #define TCAM_BIST_STAT_BIST_RT_ERR BIT(15)
107 #define TCAM_BIST_STAT_BIST_PENC_ERR BIT(14)
108 #define TCAM_BIST_STAT_BIST_COMP_ERR BIT(13)
109 #define TCAM_BIST_STAT_BIST_ADDR_ERR BIT(12)
110 #define TCAM_BIST_STAT_BIST_BL1E_ERR BIT(11)
111 #define TCAM_BIST_STAT_BIST_BL1_ERR BIT(10)
112 #define TCAM_BIST_STAT_BIST_BL0E_ERR BIT(9)
113 #define TCAM_BIST_STAT_BIST_BL0_ERR BIT(8)
114 #define TCAM_BIST_STAT_BIST_PH1_ERR BIT(7)
115 #define TCAM_BIST_STAT_BIST_PH0_ERR BIT(6)
116 #define TCAM_BIST_STAT_BIST_PV1_ERR BIT(5)
117 #define TCAM_BIST_STAT_BIST_PV0_ERR BIT(4)
118 #define TCAM_BIST_STAT_BIST_RUN BIT(3)
119 #define TCAM_BIST_STAT_BIST_ERR BIT(2)
120 #define TCAM_BIST_STAT_BIST_BUSY BIT(1)
121 #define TCAM_BIST_STAT_TCAM_RDY BIT(0)
123 /* =================================================================
125 * =================================================================
128 /* IS2 half key types */
129 #define IS2_TYPE_ETYPE 0
130 #define IS2_TYPE_LLC 1
131 #define IS2_TYPE_SNAP 2
132 #define IS2_TYPE_ARP 3
133 #define IS2_TYPE_IP_UDP_TCP 4
134 #define IS2_TYPE_IP_OTHER 5
135 #define IS2_TYPE_IPV6 6
136 #define IS2_TYPE_OAM 7
137 #define IS2_TYPE_SMAC_SIP6 8
138 #define IS2_TYPE_ANY 100 /* Pseudo type */
140 /* IS2 half key type mask for matching any IP */
141 #define IS2_TYPE_MASK_IP_ANY 0xe
144 IS2_ACTION_TYPE_NORMAL,
145 IS2_ACTION_TYPE_SMAC_SIP,
149 /* IS2 MASK_MODE values */
150 #define IS2_ACT_MASK_MODE_NONE 0
151 #define IS2_ACT_MASK_MODE_FILTER 1
152 #define IS2_ACT_MASK_MODE_POLICY 2
153 #define IS2_ACT_MASK_MODE_REDIR 3
155 /* IS2 REW_OP values */
156 #define IS2_ACT_REW_OP_NONE 0
157 #define IS2_ACT_REW_OP_PTP_ONE 2
158 #define IS2_ACT_REW_OP_PTP_TWO 3
159 #define IS2_ACT_REW_OP_SPECIAL 8
160 #define IS2_ACT_REW_OP_PTP_ORG 9
161 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_1 (IS2_ACT_REW_OP_PTP_ONE | (1 << 3))
162 #define IS2_ACT_REW_OP_PTP_ONE_SUB_DELAY_2 (IS2_ACT_REW_OP_PTP_ONE | (2 << 3))
163 #define IS2_ACT_REW_OP_PTP_ONE_ADD_DELAY (IS2_ACT_REW_OP_PTP_ONE | (1 << 5))
164 #define IS2_ACT_REW_OP_PTP_ONE_ADD_SUB BIT(7)
166 #define VCAP_PORT_WIDTH 4
168 /* IS2 quarter key - SMAC_SIP4 */
169 #define IS2_QKO_IGR_PORT 0
170 #define IS2_QKL_IGR_PORT VCAP_PORT_WIDTH
171 #define IS2_QKO_L2_SMAC (IS2_QKO_IGR_PORT + IS2_QKL_IGR_PORT)
172 #define IS2_QKL_L2_SMAC 48
173 #define IS2_QKO_L3_IP4_SIP (IS2_QKO_L2_SMAC + IS2_QKL_L2_SMAC)
174 #define IS2_QKL_L3_IP4_SIP 32
176 enum vcap_is2_half_key_field {
182 VCAP_IS2_HK_IGR_PORT_MASK,
184 VCAP_IS2_HK_HOST_MATCH,
187 VCAP_IS2_HK_VLAN_TAGGED,
191 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */
194 /* MAC_ETYPE (TYPE=000) */
195 VCAP_IS2_HK_MAC_ETYPE_ETYPE,
196 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0,
197 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1,
198 VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2,
199 /* MAC_LLC (TYPE=001) */
200 VCAP_IS2_HK_MAC_LLC_DMAC,
201 VCAP_IS2_HK_MAC_LLC_SMAC,
202 VCAP_IS2_HK_MAC_LLC_L2_LLC,
203 /* MAC_SNAP (TYPE=010) */
204 VCAP_IS2_HK_MAC_SNAP_SMAC,
205 VCAP_IS2_HK_MAC_SNAP_DMAC,
206 VCAP_IS2_HK_MAC_SNAP_L2_SNAP,
207 /* MAC_ARP (TYPE=011) */
208 VCAP_IS2_HK_MAC_ARP_SMAC,
209 VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK,
210 VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK,
211 VCAP_IS2_HK_MAC_ARP_LEN_OK,
212 VCAP_IS2_HK_MAC_ARP_TARGET_MATCH,
213 VCAP_IS2_HK_MAC_ARP_SENDER_MATCH,
214 VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN,
215 VCAP_IS2_HK_MAC_ARP_OPCODE,
216 VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP,
217 VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP,
218 VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP,
219 /* IP4_TCP_UDP / IP4_OTHER common */
221 VCAP_IS2_HK_L3_FRAGMENT,
222 VCAP_IS2_HK_L3_FRAG_OFS_GT0,
223 VCAP_IS2_HK_L3_OPTIONS,
224 VCAP_IS2_HK_IP4_L3_TTL_GT0,
226 VCAP_IS2_HK_L3_IP4_DIP,
227 VCAP_IS2_HK_L3_IP4_SIP,
228 VCAP_IS2_HK_DIP_EQ_SIP,
229 /* IP4_TCP_UDP (TYPE=100) */
231 VCAP_IS2_HK_L4_SPORT,
232 VCAP_IS2_HK_L4_DPORT,
234 VCAP_IS2_HK_L4_SPORT_EQ_DPORT,
235 VCAP_IS2_HK_L4_SEQUENCE_EQ0,
242 VCAP_IS2_HK_L4_1588_DOM,
243 VCAP_IS2_HK_L4_1588_VER,
244 /* IP4_OTHER (TYPE=101) */
245 VCAP_IS2_HK_IP4_L3_PROTO,
246 VCAP_IS2_HK_L3_PAYLOAD,
247 /* IP6_STD (TYPE=110) */
248 VCAP_IS2_HK_IP6_L3_TTL_GT0,
249 VCAP_IS2_HK_IP6_L3_PROTO,
250 VCAP_IS2_HK_L3_IP6_SIP,
252 VCAP_IS2_HK_OAM_MEL_FLAGS,
254 VCAP_IS2_HK_OAM_OPCODE,
255 VCAP_IS2_HK_OAM_FLAGS,
256 VCAP_IS2_HK_OAM_MEPID,
257 VCAP_IS2_HK_OAM_CCM_CNTS_EQ0,
258 VCAP_IS2_HK_OAM_IS_Y1731,
266 enum vcap_is2_action_field {
267 VCAP_IS2_ACT_HIT_ME_ONCE,
268 VCAP_IS2_ACT_CPU_COPY_ENA,
269 VCAP_IS2_ACT_CPU_QU_NUM,
270 VCAP_IS2_ACT_MASK_MODE,
271 VCAP_IS2_ACT_MIRROR_ENA,
272 VCAP_IS2_ACT_LRN_DIS,
273 VCAP_IS2_ACT_POLICE_ENA,
274 VCAP_IS2_ACT_POLICE_IDX,
275 VCAP_IS2_ACT_POLICE_VCAP_ONLY,
276 VCAP_IS2_ACT_PORT_MASK,
278 VCAP_IS2_ACT_SMAC_REPLACE_ENA,
281 VCAP_IS2_ACT_HIT_CNT,
284 /* =================================================================
286 * =================================================================
289 /* IS1 half key types */
290 #define IS1_TYPE_S1_NORMAL 0
291 #define IS1_TYPE_S1_5TUPLE_IP4 1
293 /* IS1 full key types */
294 #define IS1_TYPE_S1_NORMAL_IP6 0
295 #define IS1_TYPE_S1_7TUPLE 1
296 #define IS2_TYPE_S1_5TUPLE_IP6 2
299 IS1_ACTION_TYPE_NORMAL,
303 enum vcap_is1_half_key_field {
306 VCAP_IS1_HK_IGR_PORT_MASK,
308 VCAP_IS1_HK_OAM_Y1731,
312 VCAP_IS1_HK_VLAN_TAGGED,
313 VCAP_IS1_HK_VLAN_DBL_TAGGED,
318 /* Specific Fields for IS1 Half Key S1_NORMAL */
320 VCAP_IS1_HK_ETYPE_LEN,
324 VCAP_IS1_HK_L3_FRAGMENT,
325 VCAP_IS1_HK_L3_FRAG_OFS_GT0,
326 VCAP_IS1_HK_L3_OPTIONS,
328 VCAP_IS1_HK_L3_IP4_SIP,
331 VCAP_IS1_HK_L4_SPORT,
333 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */
334 VCAP_IS1_HK_IP4_INNER_TPID,
335 VCAP_IS1_HK_IP4_INNER_VID,
336 VCAP_IS1_HK_IP4_INNER_DEI,
337 VCAP_IS1_HK_IP4_INNER_PCP,
339 VCAP_IS1_HK_IP4_L3_FRAGMENT,
340 VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0,
341 VCAP_IS1_HK_IP4_L3_OPTIONS,
342 VCAP_IS1_HK_IP4_L3_DSCP,
343 VCAP_IS1_HK_IP4_L3_IP4_DIP,
344 VCAP_IS1_HK_IP4_L3_IP4_SIP,
345 VCAP_IS1_HK_IP4_L3_PROTO,
346 VCAP_IS1_HK_IP4_TCP_UDP,
348 VCAP_IS1_HK_IP4_L4_RNG,
349 VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE,
352 enum vcap_is1_action_field {
353 VCAP_IS1_ACT_DSCP_ENA,
354 VCAP_IS1_ACT_DSCP_VAL,
355 VCAP_IS1_ACT_QOS_ENA,
356 VCAP_IS1_ACT_QOS_VAL,
359 VCAP_IS1_ACT_PAG_OVERRIDE_MASK,
360 VCAP_IS1_ACT_PAG_VAL,
362 VCAP_IS1_ACT_VID_REPLACE_ENA,
363 VCAP_IS1_ACT_VID_ADD_VAL,
364 VCAP_IS1_ACT_FID_SEL,
365 VCAP_IS1_ACT_FID_VAL,
366 VCAP_IS1_ACT_PCP_DEI_ENA,
367 VCAP_IS1_ACT_PCP_VAL,
368 VCAP_IS1_ACT_DEI_VAL,
369 VCAP_IS1_ACT_VLAN_POP_CNT_ENA,
370 VCAP_IS1_ACT_VLAN_POP_CNT,
371 VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA,
372 VCAP_IS1_ACT_HIT_STICKY,
375 /* =================================================================
377 * =================================================================
381 ES0_ACTION_TYPE_NORMAL,
385 enum vcap_es0_key_field {
396 enum vcap_es0_action_field {
397 VCAP_ES0_ACT_PUSH_OUTER_TAG,
398 VCAP_ES0_ACT_PUSH_INNER_TAG,
399 VCAP_ES0_ACT_TAG_A_TPID_SEL,
400 VCAP_ES0_ACT_TAG_A_VID_SEL,
401 VCAP_ES0_ACT_TAG_A_PCP_SEL,
402 VCAP_ES0_ACT_TAG_A_DEI_SEL,
403 VCAP_ES0_ACT_TAG_B_TPID_SEL,
404 VCAP_ES0_ACT_TAG_B_VID_SEL,
405 VCAP_ES0_ACT_TAG_B_PCP_SEL,
406 VCAP_ES0_ACT_TAG_B_DEI_SEL,
407 VCAP_ES0_ACT_VID_A_VAL,
408 VCAP_ES0_ACT_PCP_A_VAL,
409 VCAP_ES0_ACT_DEI_A_VAL,
410 VCAP_ES0_ACT_VID_B_VAL,
411 VCAP_ES0_ACT_PCP_B_VAL,
412 VCAP_ES0_ACT_DEI_B_VAL,
414 VCAP_ES0_ACT_HIT_STICKY,
421 enum ocelot_vcap_bit {
427 struct ocelot_vcap_u8 {
432 struct ocelot_vcap_u16 {
437 struct ocelot_vcap_u24 {
442 struct ocelot_vcap_u32 {
447 struct ocelot_vcap_u40 {
452 struct ocelot_vcap_u48 {
457 struct ocelot_vcap_u64 {
462 struct ocelot_vcap_u128 {
467 struct ocelot_vcap_vid {
472 struct ocelot_vcap_ipv4 {
473 struct ocelot_ipv4 value;
474 struct ocelot_ipv4 mask;
477 struct ocelot_vcap_udp_tcp {
482 struct ocelot_vcap_port {
487 enum ocelot_vcap_key_type {
489 OCELOT_VCAP_KEY_ETYPE,
491 OCELOT_VCAP_KEY_SNAP,
493 OCELOT_VCAP_KEY_IPV4,
497 struct ocelot_vcap_key_vlan {
498 struct ocelot_vcap_vid vid; /* VLAN ID (12 bit) */
499 struct ocelot_vcap_u8 pcp; /* PCP (3 bit) */
500 enum ocelot_vcap_bit dei; /* DEI */
501 enum ocelot_vcap_bit tagged; /* Tagged/untagged frame */
504 struct ocelot_vcap_key_etype {
505 struct ocelot_vcap_u48 dmac;
506 struct ocelot_vcap_u48 smac;
507 struct ocelot_vcap_u16 etype;
508 struct ocelot_vcap_u16 data; /* MAC data */
511 struct ocelot_vcap_key_llc {
512 struct ocelot_vcap_u48 dmac;
513 struct ocelot_vcap_u48 smac;
515 /* LLC header: DSAP at byte 0, SSAP at byte 1, Control at byte 2 */
516 struct ocelot_vcap_u32 llc;
519 struct ocelot_vcap_key_snap {
520 struct ocelot_vcap_u48 dmac;
521 struct ocelot_vcap_u48 smac;
523 /* SNAP header: Organization Code at byte 0, Type at byte 3 */
524 struct ocelot_vcap_u40 snap;
527 struct ocelot_vcap_key_arp {
528 struct ocelot_vcap_u48 smac;
529 enum ocelot_vcap_bit arp; /* Opcode ARP/RARP */
530 enum ocelot_vcap_bit req; /* Opcode request/reply */
531 enum ocelot_vcap_bit unknown; /* Opcode unknown */
532 enum ocelot_vcap_bit smac_match; /* Sender MAC matches SMAC */
533 enum ocelot_vcap_bit dmac_match; /* Target MAC matches DMAC */
535 /**< Protocol addr. length 4, hardware length 6 */
536 enum ocelot_vcap_bit length;
538 enum ocelot_vcap_bit ip; /* Protocol address type IP */
539 enum ocelot_vcap_bit ethernet; /* Hardware address type Ethernet */
540 struct ocelot_vcap_ipv4 sip; /* Sender IP address */
541 struct ocelot_vcap_ipv4 dip; /* Target IP address */
544 struct ocelot_vcap_key_ipv4 {
545 enum ocelot_vcap_bit ttl; /* TTL zero */
546 enum ocelot_vcap_bit fragment; /* Fragment */
547 enum ocelot_vcap_bit options; /* Header options */
548 struct ocelot_vcap_u8 ds;
549 struct ocelot_vcap_u8 proto; /* Protocol */
550 struct ocelot_vcap_ipv4 sip; /* Source IP address */
551 struct ocelot_vcap_ipv4 dip; /* Destination IP address */
552 struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */
553 struct ocelot_vcap_udp_tcp sport; /* UDP/TCP: Source port */
554 struct ocelot_vcap_udp_tcp dport; /* UDP/TCP: Destination port */
555 enum ocelot_vcap_bit tcp_fin;
556 enum ocelot_vcap_bit tcp_syn;
557 enum ocelot_vcap_bit tcp_rst;
558 enum ocelot_vcap_bit tcp_psh;
559 enum ocelot_vcap_bit tcp_ack;
560 enum ocelot_vcap_bit tcp_urg;
561 enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */
562 enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */
563 enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */
566 struct ocelot_vcap_key_ipv6 {
567 struct ocelot_vcap_u8 proto; /* IPv6 protocol */
568 struct ocelot_vcap_u128 sip; /* IPv6 source (byte 0-7 ignored) */
569 struct ocelot_vcap_u128 dip; /* IPv6 destination (byte 0-7 ignored) */
570 enum ocelot_vcap_bit ttl; /* TTL zero */
571 struct ocelot_vcap_u8 ds;
572 struct ocelot_vcap_u48 data; /* Not UDP/TCP: IP data */
573 struct ocelot_vcap_udp_tcp sport;
574 struct ocelot_vcap_udp_tcp dport;
575 enum ocelot_vcap_bit tcp_fin;
576 enum ocelot_vcap_bit tcp_syn;
577 enum ocelot_vcap_bit tcp_rst;
578 enum ocelot_vcap_bit tcp_psh;
579 enum ocelot_vcap_bit tcp_ack;
580 enum ocelot_vcap_bit tcp_urg;
581 enum ocelot_vcap_bit sip_eq_dip; /* SIP equals DIP */
582 enum ocelot_vcap_bit sport_eq_dport; /* SPORT equals DPORT */
583 enum ocelot_vcap_bit seq_zero; /* TCP sequence number is zero */
586 enum ocelot_mask_mode {
587 OCELOT_MASK_MODE_NONE,
588 OCELOT_MASK_MODE_PERMIT_DENY,
589 OCELOT_MASK_MODE_POLICY,
590 OCELOT_MASK_MODE_REDIRECT,
593 enum ocelot_es0_vid_sel {
594 OCELOT_ES0_VID_PLUS_CLASSIFIED_VID = 0,
598 enum ocelot_es0_pcp_sel {
599 OCELOT_CLASSIFIED_PCP = 0,
603 enum ocelot_es0_tag {
606 OCELOT_FORCE_PORT_TAG,
610 enum ocelot_tag_tpid_sel {
611 OCELOT_TAG_TPID_SEL_8021Q,
612 OCELOT_TAG_TPID_SEL_8021AD,
615 struct ocelot_vcap_action {
619 enum ocelot_es0_tag push_outer_tag;
620 enum ocelot_es0_tag push_inner_tag;
621 enum ocelot_tag_tpid_sel tag_a_tpid_sel;
627 enum ocelot_tag_tpid_sel tag_b_tpid_sel;
637 bool vid_replace_ena;
639 bool vlan_pop_cnt_ena;
646 u8 pag_override_mask;
654 enum ocelot_mask_mode mask_mode;
655 unsigned long port_mask;
658 struct ocelot_policer pol;
664 struct ocelot_vcap_stats {
670 enum ocelot_vcap_filter_type {
671 OCELOT_VCAP_FILTER_DUMMY,
672 OCELOT_VCAP_FILTER_PAG,
673 OCELOT_VCAP_FILTER_OFFLOAD,
674 OCELOT_PSFP_FILTER_OFFLOAD,
677 struct ocelot_vcap_id {
678 unsigned long cookie;
682 struct ocelot_vcap_filter {
683 struct list_head list;
685 enum ocelot_vcap_filter_type type;
691 struct ocelot_vcap_id id;
693 struct ocelot_vcap_action action;
694 struct ocelot_vcap_stats stats;
695 /* For VCAP IS1 and IS2 */
698 unsigned long ingress_port_mask;
700 struct ocelot_vcap_port ingress_port;
701 /* For VCAP IS2 mirrors and ES0 */
702 struct ocelot_vcap_port egress_port;
704 enum ocelot_vcap_bit dmac_mc;
705 enum ocelot_vcap_bit dmac_bc;
706 struct ocelot_vcap_key_vlan vlan;
708 enum ocelot_vcap_key_type key_type;
710 /* OCELOT_VCAP_KEY_ANY: No specific fields */
711 struct ocelot_vcap_key_etype etype;
712 struct ocelot_vcap_key_llc llc;
713 struct ocelot_vcap_key_snap snap;
714 struct ocelot_vcap_key_arp arp;
715 struct ocelot_vcap_key_ipv4 ipv4;
716 struct ocelot_vcap_key_ipv6 ipv6;
720 int ocelot_vcap_filter_add(struct ocelot *ocelot,
721 struct ocelot_vcap_filter *rule,
722 struct netlink_ext_ack *extack);
723 int ocelot_vcap_filter_del(struct ocelot *ocelot,
724 struct ocelot_vcap_filter *rule);
725 int ocelot_vcap_filter_replace(struct ocelot *ocelot,
726 struct ocelot_vcap_filter *filter);
727 struct ocelot_vcap_filter *
728 ocelot_vcap_block_find_filter_by_id(struct ocelot_vcap_block *block,
729 unsigned long cookie, bool tc_offload);
731 #endif /* _OCELOT_VCAP_H_ */