1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2 /* Copyright (c) 2017 Microsemi Corporation
5 #ifndef _SOC_MSCC_OCELOT_H
6 #define _SOC_MSCC_OCELOT_H
8 #include <linux/ptp_clock_kernel.h>
9 #include <linux/net_tstamp.h>
10 #include <linux/if_vlan.h>
11 #include <linux/regmap.h>
14 struct tc_mqprio_qopt_offload;
16 /* Port Group IDs (PGID) are masks of destination ports.
18 * For L2 forwarding, the switch performs 3 lookups in the PGID table for each
19 * frame, and forwards the frame to the ports that are present in the logical
22 * These PGID lookups are:
23 * - In one of PGID[0-63]: for the destination masks. There are 2 paths by
24 * which the switch selects a destination PGID:
25 * - The {DMAC, VID} is present in the MAC table. In that case, the
26 * destination PGID is given by the DEST_IDX field of the MAC table entry
28 * - The {DMAC, VID} is not present in the MAC table (it is unknown). The
29 * frame is disseminated as being either unicast, multicast or broadcast,
30 * and according to that, the destination PGID is chosen as being the
31 * value contained by ANA_FLOODING_FLD_UNICAST,
32 * ANA_FLOODING_FLD_MULTICAST or ANA_FLOODING_FLD_BROADCAST.
33 * The destination PGID can be an unicast set: the first PGIDs, 0 to
34 * ocelot->num_phys_ports - 1, or a multicast set: the PGIDs from
35 * ocelot->num_phys_ports to 63. By convention, a unicast PGID corresponds to
36 * a physical port and has a single bit set in the destination ports mask:
37 * that corresponding to the port number itself. In contrast, a multicast
38 * PGID will have potentially more than one single bit set in the destination
40 * - In one of PGID[64-79]: for the aggregation mask. The switch classifier
41 * dissects each frame and generates a 4-bit Link Aggregation Code which is
42 * used for this second PGID table lookup. The goal of link aggregation is to
43 * hash multiple flows within the same LAG on to different destination ports.
44 * The first lookup will result in a PGID with all the LAG members present in
45 * the destination ports mask, and the second lookup, by Link Aggregation
46 * Code, will ensure that each flow gets forwarded only to a single port out
47 * of that mask (there are no duplicates).
48 * - In one of PGID[80-90]: for the source mask. The third time, the PGID table
49 * is indexed with the ingress port (plus 80). These PGIDs answer the
50 * question "is port i allowed to forward traffic to port j?" If yes, then
51 * BIT(j) of PGID 80+i will be found set. The third PGID lookup can be used
52 * to enforce the L2 forwarding matrix imposed by e.g. a Linux bridge.
55 /* Reserve some destination PGIDs at the end of the range:
56 * PGID_BLACKHOLE: used for not forwarding the frames
57 * PGID_CPU: used for whitelisting certain MAC addresses, such as the addresses
58 * of the switch port net devices, towards the CPU port module.
59 * PGID_UC: the flooding destinations for unknown unicast traffic.
60 * PGID_MC: the flooding destinations for non-IP multicast traffic.
61 * PGID_MCIPV4: the flooding destinations for IPv4 multicast traffic.
62 * PGID_MCIPV6: the flooding destinations for IPv6 multicast traffic.
63 * PGID_BC: the flooding destinations for broadcast traffic.
65 #define PGID_BLACKHOLE 57
69 #define PGID_MCIPV4 61
70 #define PGID_MCIPV6 62
73 #define for_each_unicast_dest_pgid(ocelot, pgid) \
75 (pgid) < (ocelot)->num_phys_ports; \
78 #define for_each_nonreserved_multicast_dest_pgid(ocelot, pgid) \
79 for ((pgid) = (ocelot)->num_phys_ports + 1; \
80 (pgid) < PGID_BLACKHOLE; \
83 #define for_each_aggr_pgid(ocelot, pgid) \
84 for ((pgid) = PGID_AGGR; \
88 /* Aggregation PGIDs, one per Link Aggregation Code */
91 /* Source PGIDs, one per physical port */
94 #define OCELOT_NUM_TC 8
96 #define OCELOT_SPEED_2500 0
97 #define OCELOT_SPEED_1000 1
98 #define OCELOT_SPEED_100 2
99 #define OCELOT_SPEED_10 3
101 #define OCELOT_PTP_PINS_NUM 4
103 #define TARGET_OFFSET 24
104 #define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
105 #define REG(reg, offset) [reg & REG_MASK] = offset
107 #define REG_RESERVED_ADDR 0xffffffff
108 #define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
128 ANA_ADVLEARN = ANA << TARGET_OFFSET,
133 ANA_STORMLIMIT_BURST,
152 ANA_TABLES_STREAMDATA,
153 ANA_TABLES_MACACCESS,
155 ANA_TABLES_VLANACCESS,
157 ANA_TABLES_ISDXACCESS,
160 ANA_TABLES_PTP_ID_HIGH,
161 ANA_TABLES_PTP_ID_LOW,
162 ANA_TABLES_STREAMACCESS,
163 ANA_TABLES_STREAMTIDX,
164 ANA_TABLES_SEQ_HISTORY,
166 ANA_TABLES_SFID_MASK,
167 ANA_TABLES_SFIDACCESS,
177 ANA_SG_GCL_GS_CONFIG,
178 ANA_SG_GCL_TI_CONFIG,
186 ANA_PORT_VCAP_S1_KEY_CFG,
187 ANA_PORT_VCAP_S2_CFG,
188 ANA_PORT_PCP_DEI_MAP,
189 ANA_PORT_CPU_FWD_CFG,
190 ANA_PORT_CPU_FWD_BPDU_CFG,
191 ANA_PORT_CPU_FWD_GARP_CFG,
192 ANA_PORT_CPU_FWD_CCM_CFG,
196 ANA_PORT_PTP_DLY1_CFG,
197 ANA_PORT_PTP_DLY2_CFG,
211 ANA_VCAP_RNG_TYPE_CFG,
212 ANA_VCAP_RNG_VAL_CFG,
227 QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
239 QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
240 QSYS_SWITCH_PORT_MODE,
252 QSYS_TIMED_FRAME_ENTRY,
255 QSYS_TFRM_TIMER_CFG_1,
256 QSYS_TFRM_TIMER_CFG_2,
257 QSYS_TFRM_TIMER_CFG_3,
258 QSYS_TFRM_TIMER_CFG_4,
259 QSYS_TFRM_TIMER_CFG_5,
260 QSYS_TFRM_TIMER_CFG_6,
261 QSYS_TFRM_TIMER_CFG_7,
262 QSYS_TFRM_TIMER_CFG_8,
290 QSYS_TAS_PARAM_CFG_CTRL,
292 QSYS_PARAM_CFG_REG_1,
293 QSYS_PARAM_CFG_REG_2,
294 QSYS_PARAM_CFG_REG_3,
295 QSYS_PARAM_CFG_REG_4,
296 QSYS_PARAM_CFG_REG_5,
299 QSYS_PARAM_STATUS_REG_1,
300 QSYS_PARAM_STATUS_REG_2,
301 QSYS_PARAM_STATUS_REG_3,
302 QSYS_PARAM_STATUS_REG_4,
303 QSYS_PARAM_STATUS_REG_5,
304 QSYS_PARAM_STATUS_REG_6,
305 QSYS_PARAM_STATUS_REG_7,
306 QSYS_PARAM_STATUS_REG_8,
307 QSYS_PARAM_STATUS_REG_9,
308 QSYS_GCL_STATUS_REG_1,
309 QSYS_GCL_STATUS_REG_2,
310 REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
314 REW_PCP_DEI_QOS_MAP_CFG,
318 REW_DSCP_REMAP_DP1_CFG,
323 SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
324 SYS_COUNT_RX_UNICAST,
325 SYS_COUNT_RX_MULTICAST,
326 SYS_COUNT_RX_BROADCAST,
328 SYS_COUNT_RX_FRAGMENTS,
329 SYS_COUNT_RX_JABBERS,
330 SYS_COUNT_RX_CRC_ALIGN_ERRS,
331 SYS_COUNT_RX_SYM_ERRS,
334 SYS_COUNT_RX_128_255,
335 SYS_COUNT_RX_256_511,
336 SYS_COUNT_RX_512_1023,
337 SYS_COUNT_RX_1024_1526,
338 SYS_COUNT_RX_1527_MAX,
340 SYS_COUNT_RX_CONTROL,
342 SYS_COUNT_RX_CLASSIFIED_DROPS,
343 SYS_COUNT_RX_RED_PRIO_0,
344 SYS_COUNT_RX_RED_PRIO_1,
345 SYS_COUNT_RX_RED_PRIO_2,
346 SYS_COUNT_RX_RED_PRIO_3,
347 SYS_COUNT_RX_RED_PRIO_4,
348 SYS_COUNT_RX_RED_PRIO_5,
349 SYS_COUNT_RX_RED_PRIO_6,
350 SYS_COUNT_RX_RED_PRIO_7,
351 SYS_COUNT_RX_YELLOW_PRIO_0,
352 SYS_COUNT_RX_YELLOW_PRIO_1,
353 SYS_COUNT_RX_YELLOW_PRIO_2,
354 SYS_COUNT_RX_YELLOW_PRIO_3,
355 SYS_COUNT_RX_YELLOW_PRIO_4,
356 SYS_COUNT_RX_YELLOW_PRIO_5,
357 SYS_COUNT_RX_YELLOW_PRIO_6,
358 SYS_COUNT_RX_YELLOW_PRIO_7,
359 SYS_COUNT_RX_GREEN_PRIO_0,
360 SYS_COUNT_RX_GREEN_PRIO_1,
361 SYS_COUNT_RX_GREEN_PRIO_2,
362 SYS_COUNT_RX_GREEN_PRIO_3,
363 SYS_COUNT_RX_GREEN_PRIO_4,
364 SYS_COUNT_RX_GREEN_PRIO_5,
365 SYS_COUNT_RX_GREEN_PRIO_6,
366 SYS_COUNT_RX_GREEN_PRIO_7,
367 SYS_COUNT_RX_ASSEMBLY_ERRS,
368 SYS_COUNT_RX_SMD_ERRS,
369 SYS_COUNT_RX_ASSEMBLY_OK,
370 SYS_COUNT_RX_MERGE_FRAGMENTS,
371 SYS_COUNT_RX_PMAC_OCTETS,
372 SYS_COUNT_RX_PMAC_UNICAST,
373 SYS_COUNT_RX_PMAC_MULTICAST,
374 SYS_COUNT_RX_PMAC_BROADCAST,
375 SYS_COUNT_RX_PMAC_SHORTS,
376 SYS_COUNT_RX_PMAC_FRAGMENTS,
377 SYS_COUNT_RX_PMAC_JABBERS,
378 SYS_COUNT_RX_PMAC_CRC_ALIGN_ERRS,
379 SYS_COUNT_RX_PMAC_SYM_ERRS,
380 SYS_COUNT_RX_PMAC_64,
381 SYS_COUNT_RX_PMAC_65_127,
382 SYS_COUNT_RX_PMAC_128_255,
383 SYS_COUNT_RX_PMAC_256_511,
384 SYS_COUNT_RX_PMAC_512_1023,
385 SYS_COUNT_RX_PMAC_1024_1526,
386 SYS_COUNT_RX_PMAC_1527_MAX,
387 SYS_COUNT_RX_PMAC_PAUSE,
388 SYS_COUNT_RX_PMAC_CONTROL,
389 SYS_COUNT_RX_PMAC_LONGS,
391 SYS_COUNT_TX_UNICAST,
392 SYS_COUNT_TX_MULTICAST,
393 SYS_COUNT_TX_BROADCAST,
394 SYS_COUNT_TX_COLLISION,
399 SYS_COUNT_TX_128_255,
400 SYS_COUNT_TX_256_511,
401 SYS_COUNT_TX_512_1023,
402 SYS_COUNT_TX_1024_1526,
403 SYS_COUNT_TX_1527_MAX,
404 SYS_COUNT_TX_YELLOW_PRIO_0,
405 SYS_COUNT_TX_YELLOW_PRIO_1,
406 SYS_COUNT_TX_YELLOW_PRIO_2,
407 SYS_COUNT_TX_YELLOW_PRIO_3,
408 SYS_COUNT_TX_YELLOW_PRIO_4,
409 SYS_COUNT_TX_YELLOW_PRIO_5,
410 SYS_COUNT_TX_YELLOW_PRIO_6,
411 SYS_COUNT_TX_YELLOW_PRIO_7,
412 SYS_COUNT_TX_GREEN_PRIO_0,
413 SYS_COUNT_TX_GREEN_PRIO_1,
414 SYS_COUNT_TX_GREEN_PRIO_2,
415 SYS_COUNT_TX_GREEN_PRIO_3,
416 SYS_COUNT_TX_GREEN_PRIO_4,
417 SYS_COUNT_TX_GREEN_PRIO_5,
418 SYS_COUNT_TX_GREEN_PRIO_6,
419 SYS_COUNT_TX_GREEN_PRIO_7,
421 SYS_COUNT_TX_MM_HOLD,
422 SYS_COUNT_TX_MERGE_FRAGMENTS,
423 SYS_COUNT_TX_PMAC_OCTETS,
424 SYS_COUNT_TX_PMAC_UNICAST,
425 SYS_COUNT_TX_PMAC_MULTICAST,
426 SYS_COUNT_TX_PMAC_BROADCAST,
427 SYS_COUNT_TX_PMAC_PAUSE,
428 SYS_COUNT_TX_PMAC_64,
429 SYS_COUNT_TX_PMAC_65_127,
430 SYS_COUNT_TX_PMAC_128_255,
431 SYS_COUNT_TX_PMAC_256_511,
432 SYS_COUNT_TX_PMAC_512_1023,
433 SYS_COUNT_TX_PMAC_1024_1526,
434 SYS_COUNT_TX_PMAC_1527_MAX,
435 SYS_COUNT_DROP_LOCAL,
437 SYS_COUNT_DROP_YELLOW_PRIO_0,
438 SYS_COUNT_DROP_YELLOW_PRIO_1,
439 SYS_COUNT_DROP_YELLOW_PRIO_2,
440 SYS_COUNT_DROP_YELLOW_PRIO_3,
441 SYS_COUNT_DROP_YELLOW_PRIO_4,
442 SYS_COUNT_DROP_YELLOW_PRIO_5,
443 SYS_COUNT_DROP_YELLOW_PRIO_6,
444 SYS_COUNT_DROP_YELLOW_PRIO_7,
445 SYS_COUNT_DROP_GREEN_PRIO_0,
446 SYS_COUNT_DROP_GREEN_PRIO_1,
447 SYS_COUNT_DROP_GREEN_PRIO_2,
448 SYS_COUNT_DROP_GREEN_PRIO_3,
449 SYS_COUNT_DROP_GREEN_PRIO_4,
450 SYS_COUNT_DROP_GREEN_PRIO_5,
451 SYS_COUNT_DROP_GREEN_PRIO_6,
452 SYS_COUNT_DROP_GREEN_PRIO_7,
453 SYS_COUNT_SF_MATCHING_FRAMES,
454 SYS_COUNT_SF_NOT_PASSING_FRAMES,
455 SYS_COUNT_SF_NOT_PASSING_SDU,
456 SYS_COUNT_SF_RED_FRAMES,
466 SYS_REW_MAC_HIGH_CFG,
468 SYS_TIMESTAMP_OFFSET,
489 PTP_PIN_CFG = PTP << TARGET_OFFSET,
493 PTP_PIN_WF_HIGH_PERIOD,
494 PTP_PIN_WF_LOW_PERIOD,
497 PTP_CLK_CFG_ADJ_FREQ,
498 GCB_SOFT_RST = GCB << TARGET_OFFSET,
502 DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
517 DEV_MAC_FC_MAC_LOW_CFG,
518 DEV_MAC_FC_MAC_HIGH_CFG,
520 DEV_MM_ENABLE_CONFIG,
532 PCS1G_ANEG_NP_STATUS,
538 PCS1G_LPI_WAKE_ERROR_CNT,
540 PCS1G_TSTPAT_MODE_CFG,
543 DEV_PCS_FX100_STATUS,
546 enum ocelot_regfield {
547 ANA_ADVLEARN_VLAN_CHK,
548 ANA_ADVLEARN_LEARN_MIRROR,
549 ANA_ANEVENTS_FLOOD_DISCARD,
550 ANA_ANEVENTS_MSTI_DROP,
551 ANA_ANEVENTS_ACLKILL,
552 ANA_ANEVENTS_ACLUSED,
553 ANA_ANEVENTS_AUTOAGE,
554 ANA_ANEVENTS_VS2TTL1,
555 ANA_ANEVENTS_STORM_DROP,
556 ANA_ANEVENTS_LEARN_DROP,
557 ANA_ANEVENTS_AGED_ENTRY,
558 ANA_ANEVENTS_CPU_LEARN_FAILED,
559 ANA_ANEVENTS_AUTO_LEARN_FAILED,
560 ANA_ANEVENTS_LEARN_REMOVE,
561 ANA_ANEVENTS_AUTO_LEARNED,
562 ANA_ANEVENTS_AUTO_MOVED,
563 ANA_ANEVENTS_DROPPED,
564 ANA_ANEVENTS_CLASSIFIED_DROP,
565 ANA_ANEVENTS_CLASSIFIED_COPY,
566 ANA_ANEVENTS_VLAN_DISCARD,
567 ANA_ANEVENTS_FWD_DISCARD,
568 ANA_ANEVENTS_MULTICAST_FLOOD,
569 ANA_ANEVENTS_UNICAST_FLOOD,
570 ANA_ANEVENTS_DEST_KNOWN,
571 ANA_ANEVENTS_BUCKET3_MATCH,
572 ANA_ANEVENTS_BUCKET2_MATCH,
573 ANA_ANEVENTS_BUCKET1_MATCH,
574 ANA_ANEVENTS_BUCKET0_MATCH,
575 ANA_ANEVENTS_CPU_OPERATION,
576 ANA_ANEVENTS_DMAC_LOOKUP,
577 ANA_ANEVENTS_SMAC_LOOKUP,
578 ANA_ANEVENTS_SEQ_GEN_ERR_0,
579 ANA_ANEVENTS_SEQ_GEN_ERR_1,
580 ANA_TABLES_MACACCESS_B_DOM,
581 ANA_TABLES_MACTINDX_BUCKET,
582 ANA_TABLES_MACTINDX_M_INDEX,
583 QSYS_SWITCH_PORT_MODE_PORT_ENA,
584 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG,
585 QSYS_SWITCH_PORT_MODE_YEL_RSRVD,
586 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE,
587 QSYS_SWITCH_PORT_MODE_TX_PFC_ENA,
588 QSYS_SWITCH_PORT_MODE_TX_PFC_MODE,
589 QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
590 QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
591 QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
592 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
593 QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
594 SYS_PORT_MODE_DATA_WO_TS,
595 SYS_PORT_MODE_INCL_INJ_HDR,
596 SYS_PORT_MODE_INCL_XTR_HDR,
597 SYS_PORT_MODE_INCL_HDR_ERR,
598 SYS_RESET_CFG_CORE_ENA,
599 SYS_RESET_CFG_MEM_ENA,
600 SYS_RESET_CFG_MEM_INIT,
601 GCB_SOFT_RST_SWC_RST,
602 GCB_MIIM_MII_STATUS_PENDING,
603 GCB_MIIM_MII_STATUS_BUSY,
604 SYS_PAUSE_CFG_PAUSE_START,
605 SYS_PAUSE_CFG_PAUSE_STOP,
606 SYS_PAUSE_CFG_PAUSE_ENA,
612 VCAP_CORE_UPDATE_CTRL,
614 /* VCAP_CORE_CACHE */
615 VCAP_CACHE_ENTRY_DAT,
617 VCAP_CACHE_ACTION_DAT,
622 VCAP_CONST_ENTRY_WIDTH,
623 VCAP_CONST_ENTRY_CNT,
624 VCAP_CONST_ENTRY_SWCNT,
625 VCAP_CONST_ENTRY_TG_WIDTH,
626 VCAP_CONST_ACTION_DEF_CNT,
627 VCAP_CONST_ACTION_WIDTH,
628 VCAP_CONST_CNT_WIDTH,
633 enum ocelot_ptp_pins {
641 enum ocelot_tag_prefix {
642 OCELOT_TAG_PREFIX_DISABLED = 0,
643 OCELOT_TAG_PREFIX_NONE,
644 OCELOT_TAG_PREFIX_SHORT,
645 OCELOT_TAG_PREFIX_LONG,
652 struct net_device *(*port_to_netdev)(struct ocelot *ocelot, int port);
653 int (*netdev_to_port)(struct net_device *dev);
654 int (*reset)(struct ocelot *ocelot);
655 u16 (*wm_enc)(u16 value);
656 u16 (*wm_dec)(u16 value);
657 void (*wm_stat)(u32 val, u32 *inuse, u32 *maxuse);
658 void (*psfp_init)(struct ocelot *ocelot);
659 int (*psfp_filter_add)(struct ocelot *ocelot, int port,
660 struct flow_cls_offload *f);
661 int (*psfp_filter_del)(struct ocelot *ocelot, struct flow_cls_offload *f);
662 int (*psfp_stats_get)(struct ocelot *ocelot, struct flow_cls_offload *f,
663 struct flow_stats *stats);
664 void (*cut_through_fwd)(struct ocelot *ocelot);
665 void (*tas_clock_adjust)(struct ocelot *ocelot);
666 void (*update_stats)(struct ocelot *ocelot);
669 struct ocelot_vcap_policer {
670 struct list_head pol_list;
677 struct ocelot_vcap_block {
678 struct list_head rules;
682 struct ocelot_bridge_vlan {
684 unsigned long portmask;
685 unsigned long untagged;
686 struct list_head list;
689 enum ocelot_port_tag_config {
690 /* all VLANs are egress-untagged */
691 OCELOT_PORT_TAG_DISABLED = 0,
692 /* all VLANs except the native VLAN and VID 0 are egress-tagged */
693 OCELOT_PORT_TAG_NATIVE = 1,
694 /* all VLANs except VID 0 are egress-tagged */
695 OCELOT_PORT_TAG_TRUNK_NO_VID0 = 2,
696 /* all VLANs are egress-tagged */
697 OCELOT_PORT_TAG_TRUNK = 3,
700 struct ocelot_psfp_list {
701 struct list_head stream_list;
702 struct list_head sfi_list;
703 struct list_head sgi_list;
704 /* Serialize access to the lists */
714 enum ocelot_sb_pool {
720 /* MAC table entry types.
721 * ENTRYTYPE_NORMAL is subject to aging.
722 * ENTRYTYPE_LOCKED is not subject to aging.
723 * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast.
724 * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast.
726 enum macaccess_entry_type {
727 ENTRYTYPE_NORMAL = 0,
734 OCELOT_PROTO_PTP_L2 = BIT(0),
735 OCELOT_PROTO_PTP_L4 = BIT(1),
738 #define OCELOT_QUIRK_PCS_PERFORMS_RATE_ADAPTATION BIT(0)
739 #define OCELOT_QUIRK_QSGMII_PORTS_MUST_BE_UP BIT(1)
741 struct ocelot_lag_fdb {
742 unsigned char addr[ETH_ALEN];
744 struct net_device *bond;
745 struct list_head list;
748 struct ocelot_mirror {
753 struct ocelot_mm_state {
754 enum ethtool_mm_verify_status verify_status;
758 u8 active_preemptible_tcs;
764 struct ocelot *ocelot;
766 struct regmap *target;
768 struct net_device *bond;
769 struct net_device *bridge;
771 struct ocelot_port *dsa_8021q_cpu;
773 /* VLAN that untagged frames are classified to, on ingress */
774 const struct ocelot_bridge_vlan *pvid_vlan;
776 struct tc_taprio_qopt_offload *taprio;
778 phy_interface_t phy_mode;
780 unsigned int ptp_skbs_in_flight;
781 struct sk_buff_head tx_skbs;
783 unsigned int trap_proto;
794 bool is_dsa_8021q_cpu;
806 struct devlink *devlink;
807 struct devlink_port *devlink_ports;
809 const struct ocelot_ops *ops;
810 struct regmap *targets[TARGET_MAX];
811 struct regmap_field *regfields[REGFIELD_MAX];
812 const u32 *const *map;
813 struct list_head stats_regions;
815 u32 pool_size[OCELOT_SB_NUM][OCELOT_SB_POOL_NUM];
816 int packet_buffer_size;
820 struct ocelot_port **ports;
822 u8 base_mac[ETH_ALEN];
824 struct list_head vlans;
825 struct list_head traps;
826 struct list_head lag_fdbs;
828 /* Switches like VSC9959 have flooding per traffic class */
829 int num_flooding_pgids;
831 /* In tables like ANA:PORT and the ANA:PGID:PGID mask,
832 * the CPU is located after the physical ports (at the
833 * num_phys_ports index).
839 enum ocelot_tag_prefix npi_inj_prefix;
840 enum ocelot_tag_prefix npi_xtr_prefix;
842 unsigned long bridges;
844 struct list_head multicast;
845 struct list_head pgids;
847 struct list_head dummy_rules;
848 struct ocelot_vcap_block block[3];
849 struct ocelot_vcap_policer vcap_pol;
850 struct vcap_props *vcap;
851 struct ocelot_mirror *mirror;
853 struct ocelot_psfp_list psfp;
855 /* Workqueue to check statistics for overflow */
856 struct delayed_work stats_work;
857 struct workqueue_struct *stats_queue;
858 /* Lock for serializing access to the statistics array */
859 spinlock_t stats_lock;
862 /* Lock for serializing indirect access to STAT_VIEW registers */
863 struct mutex stat_view_lock;
864 /* Lock for serializing access to the MAC table */
865 struct mutex mact_lock;
866 /* Lock for serializing forwarding domain changes */
867 struct mutex fwd_domain_lock;
869 /* Lock for serializing Time-Aware Shaper changes */
870 struct mutex tas_lock;
872 struct workqueue_struct *owq;
876 struct ptp_clock *ptp_clock;
877 struct ptp_clock_info ptp_info;
878 unsigned int ptp_skbs_in_flight;
879 /* Protects the 2-step TX timestamp ID logic */
880 spinlock_t ts_id_lock;
881 /* Protects the PTP clock */
882 spinlock_t ptp_clock_lock;
883 struct ptp_pin_desc ptp_pins[OCELOT_PTP_PINS_NUM];
885 struct ocelot_mm_state *mm;
887 struct ocelot_fdma *fdma;
890 struct ocelot_policer {
891 u32 rate; /* kilobit per second */
892 u32 burst; /* bytes */
895 #define ocelot_bulk_read(ocelot, reg, buf, count) \
896 __ocelot_bulk_read_ix(ocelot, reg, 0, buf, count)
898 #define ocelot_read_ix(ocelot, reg, gi, ri) \
899 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
900 #define ocelot_read_gix(ocelot, reg, gi) \
901 __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
902 #define ocelot_read_rix(ocelot, reg, ri) \
903 __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
904 #define ocelot_read(ocelot, reg) \
905 __ocelot_read_ix(ocelot, reg, 0)
907 #define ocelot_write_ix(ocelot, val, reg, gi, ri) \
908 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
909 #define ocelot_write_gix(ocelot, val, reg, gi) \
910 __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
911 #define ocelot_write_rix(ocelot, val, reg, ri) \
912 __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
913 #define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
915 #define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) \
916 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
917 #define ocelot_rmw_gix(ocelot, val, m, reg, gi) \
918 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
919 #define ocelot_rmw_rix(ocelot, val, m, reg, ri) \
920 __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
921 #define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
923 #define ocelot_field_write(ocelot, reg, val) \
924 regmap_field_write((ocelot)->regfields[(reg)], (val))
925 #define ocelot_field_read(ocelot, reg, val) \
926 regmap_field_read((ocelot)->regfields[(reg)], (val))
927 #define ocelot_fields_write(ocelot, id, reg, val) \
928 regmap_fields_write((ocelot)->regfields[(reg)], (id), (val))
929 #define ocelot_fields_read(ocelot, id, reg, val) \
930 regmap_fields_read((ocelot)->regfields[(reg)], (id), (val))
932 #define ocelot_target_read_ix(ocelot, target, reg, gi, ri) \
933 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
934 #define ocelot_target_read_gix(ocelot, target, reg, gi) \
935 __ocelot_target_read_ix(ocelot, target, reg, reg##_GSZ * (gi))
936 #define ocelot_target_read_rix(ocelot, target, reg, ri) \
937 __ocelot_target_read_ix(ocelot, target, reg, reg##_RSZ * (ri))
938 #define ocelot_target_read(ocelot, target, reg) \
939 __ocelot_target_read_ix(ocelot, target, reg, 0)
941 #define ocelot_target_write_ix(ocelot, target, val, reg, gi, ri) \
942 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
943 #define ocelot_target_write_gix(ocelot, target, val, reg, gi) \
944 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_GSZ * (gi))
945 #define ocelot_target_write_rix(ocelot, target, val, reg, ri) \
946 __ocelot_target_write_ix(ocelot, target, val, reg, reg##_RSZ * (ri))
947 #define ocelot_target_write(ocelot, target, val, reg) \
948 __ocelot_target_write_ix(ocelot, target, val, reg, 0)
951 u32 ocelot_port_readl(struct ocelot_port *port, enum ocelot_reg reg);
952 void ocelot_port_writel(struct ocelot_port *port, u32 val, enum ocelot_reg reg);
953 void ocelot_port_rmwl(struct ocelot_port *port, u32 val, u32 mask,
954 enum ocelot_reg reg);
955 int __ocelot_bulk_read_ix(struct ocelot *ocelot, enum ocelot_reg reg,
956 u32 offset, void *buf, int count);
957 u32 __ocelot_read_ix(struct ocelot *ocelot, enum ocelot_reg reg, u32 offset);
958 void __ocelot_write_ix(struct ocelot *ocelot, u32 val, enum ocelot_reg reg,
960 void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask,
961 enum ocelot_reg reg, u32 offset);
962 u32 __ocelot_target_read_ix(struct ocelot *ocelot, enum ocelot_target target,
963 u32 reg, u32 offset);
964 void __ocelot_target_write_ix(struct ocelot *ocelot, enum ocelot_target target,
965 u32 val, u32 reg, u32 offset);
968 bool ocelot_can_inject(struct ocelot *ocelot, int grp);
969 void ocelot_port_inject_frame(struct ocelot *ocelot, int port, int grp,
970 u32 rew_op, struct sk_buff *skb);
971 void ocelot_ifh_port_set(void *ifh, int port, u32 rew_op, u32 vlan_tag);
972 int ocelot_xtr_poll_frame(struct ocelot *ocelot, int grp, struct sk_buff **skb);
973 void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp);
974 void ocelot_ptp_rx_timestamp(struct ocelot *ocelot, struct sk_buff *skb,
977 /* Hardware initialization */
978 int ocelot_regfields_init(struct ocelot *ocelot,
979 const struct reg_field *const regfields);
980 struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
981 int ocelot_reset(struct ocelot *ocelot);
982 int ocelot_init(struct ocelot *ocelot);
983 void ocelot_deinit(struct ocelot *ocelot);
984 void ocelot_init_port(struct ocelot *ocelot, int port);
985 void ocelot_deinit_port(struct ocelot *ocelot, int port);
987 void ocelot_port_setup_dsa_8021q_cpu(struct ocelot *ocelot, int cpu);
988 void ocelot_port_teardown_dsa_8021q_cpu(struct ocelot *ocelot, int cpu);
989 void ocelot_port_assign_dsa_8021q_cpu(struct ocelot *ocelot, int port, int cpu);
990 void ocelot_port_unassign_dsa_8021q_cpu(struct ocelot *ocelot, int port);
991 u32 ocelot_port_assigned_dsa_8021q_cpu_mask(struct ocelot *ocelot, int port);
993 /* Watermark interface */
994 u16 ocelot_wm_enc(u16 value);
995 u16 ocelot_wm_dec(u16 wm);
996 void ocelot_wm_stat(u32 val, u32 *inuse, u32 *maxuse);
999 void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
1000 void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
1001 int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
1002 void ocelot_port_get_stats64(struct ocelot *ocelot, int port,
1003 struct rtnl_link_stats64 *stats);
1004 void ocelot_port_get_pause_stats(struct ocelot *ocelot, int port,
1005 struct ethtool_pause_stats *pause_stats);
1006 void ocelot_port_get_mm_stats(struct ocelot *ocelot, int port,
1007 struct ethtool_mm_stats *stats);
1008 void ocelot_port_get_rmon_stats(struct ocelot *ocelot, int port,
1009 struct ethtool_rmon_stats *rmon_stats,
1010 const struct ethtool_rmon_hist_range **ranges);
1011 void ocelot_port_get_eth_ctrl_stats(struct ocelot *ocelot, int port,
1012 struct ethtool_eth_ctrl_stats *ctrl_stats);
1013 void ocelot_port_get_eth_mac_stats(struct ocelot *ocelot, int port,
1014 struct ethtool_eth_mac_stats *mac_stats);
1015 void ocelot_port_get_eth_phy_stats(struct ocelot *ocelot, int port,
1016 struct ethtool_eth_phy_stats *phy_stats);
1017 int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1018 struct ethtool_ts_info *info);
1019 void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
1020 int ocelot_port_vlan_filtering(struct ocelot *ocelot, int port, bool enabled,
1021 struct netlink_ext_ack *extack);
1022 void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
1023 u32 ocelot_get_bridge_fwd_mask(struct ocelot *ocelot, int src_port);
1024 int ocelot_port_pre_bridge_flags(struct ocelot *ocelot, int port,
1025 struct switchdev_brport_flags val);
1026 void ocelot_port_bridge_flags(struct ocelot *ocelot, int port,
1027 struct switchdev_brport_flags val);
1028 int ocelot_port_get_default_prio(struct ocelot *ocelot, int port);
1029 int ocelot_port_set_default_prio(struct ocelot *ocelot, int port, u8 prio);
1030 int ocelot_port_get_dscp_prio(struct ocelot *ocelot, int port, u8 dscp);
1031 int ocelot_port_add_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
1032 int ocelot_port_del_dscp_prio(struct ocelot *ocelot, int port, u8 dscp, u8 prio);
1033 int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1034 struct net_device *bridge, int bridge_num,
1035 struct netlink_ext_ack *extack);
1036 void ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1037 struct net_device *bridge);
1038 int ocelot_mact_flush(struct ocelot *ocelot, int port);
1039 int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1040 dsa_fdb_dump_cb_t *cb, void *data);
1041 int ocelot_fdb_add(struct ocelot *ocelot, int port, const unsigned char *addr,
1042 u16 vid, const struct net_device *bridge);
1043 int ocelot_fdb_del(struct ocelot *ocelot, int port, const unsigned char *addr,
1044 u16 vid, const struct net_device *bridge);
1045 int ocelot_lag_fdb_add(struct ocelot *ocelot, struct net_device *bond,
1046 const unsigned char *addr, u16 vid,
1047 const struct net_device *bridge);
1048 int ocelot_lag_fdb_del(struct ocelot *ocelot, struct net_device *bond,
1049 const unsigned char *addr, u16 vid,
1050 const struct net_device *bridge);
1051 int ocelot_vlan_prepare(struct ocelot *ocelot, int port, u16 vid, bool pvid,
1052 bool untagged, struct netlink_ext_ack *extack);
1053 int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
1055 int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
1056 int ocelot_hwstamp_get(struct ocelot *ocelot, int port, struct ifreq *ifr);
1057 int ocelot_hwstamp_set(struct ocelot *ocelot, int port, struct ifreq *ifr);
1058 int ocelot_port_txtstamp_request(struct ocelot *ocelot, int port,
1059 struct sk_buff *skb,
1060 struct sk_buff **clone);
1061 void ocelot_get_txtstamp(struct ocelot *ocelot);
1062 void ocelot_port_set_maxlen(struct ocelot *ocelot, int port, size_t sdu);
1063 int ocelot_get_max_mtu(struct ocelot *ocelot, int port);
1064 int ocelot_port_policer_add(struct ocelot *ocelot, int port,
1065 struct ocelot_policer *pol);
1066 int ocelot_port_policer_del(struct ocelot *ocelot, int port);
1067 int ocelot_port_mirror_add(struct ocelot *ocelot, int from, int to,
1068 bool ingress, struct netlink_ext_ack *extack);
1069 void ocelot_port_mirror_del(struct ocelot *ocelot, int from, bool ingress);
1070 int ocelot_cls_flower_replace(struct ocelot *ocelot, int port,
1071 struct flow_cls_offload *f, bool ingress);
1072 int ocelot_cls_flower_destroy(struct ocelot *ocelot, int port,
1073 struct flow_cls_offload *f, bool ingress);
1074 int ocelot_cls_flower_stats(struct ocelot *ocelot, int port,
1075 struct flow_cls_offload *f, bool ingress);
1076 int ocelot_port_mdb_add(struct ocelot *ocelot, int port,
1077 const struct switchdev_obj_port_mdb *mdb,
1078 const struct net_device *bridge);
1079 int ocelot_port_mdb_del(struct ocelot *ocelot, int port,
1080 const struct switchdev_obj_port_mdb *mdb,
1081 const struct net_device *bridge);
1082 int ocelot_port_lag_join(struct ocelot *ocelot, int port,
1083 struct net_device *bond,
1084 struct netdev_lag_upper_info *info,
1085 struct netlink_ext_ack *extack);
1086 void ocelot_port_lag_leave(struct ocelot *ocelot, int port,
1087 struct net_device *bond);
1088 void ocelot_port_lag_change(struct ocelot *ocelot, int port, bool lag_tx_active);
1089 int ocelot_bond_get_id(struct ocelot *ocelot, struct net_device *bond);
1091 int ocelot_devlink_sb_register(struct ocelot *ocelot);
1092 void ocelot_devlink_sb_unregister(struct ocelot *ocelot);
1093 int ocelot_sb_pool_get(struct ocelot *ocelot, unsigned int sb_index,
1095 struct devlink_sb_pool_info *pool_info);
1096 int ocelot_sb_pool_set(struct ocelot *ocelot, unsigned int sb_index,
1097 u16 pool_index, u32 size,
1098 enum devlink_sb_threshold_type threshold_type,
1099 struct netlink_ext_ack *extack);
1100 int ocelot_sb_port_pool_get(struct ocelot *ocelot, int port,
1101 unsigned int sb_index, u16 pool_index,
1103 int ocelot_sb_port_pool_set(struct ocelot *ocelot, int port,
1104 unsigned int sb_index, u16 pool_index,
1105 u32 threshold, struct netlink_ext_ack *extack);
1106 int ocelot_sb_tc_pool_bind_get(struct ocelot *ocelot, int port,
1107 unsigned int sb_index, u16 tc_index,
1108 enum devlink_sb_pool_type pool_type,
1109 u16 *p_pool_index, u32 *p_threshold);
1110 int ocelot_sb_tc_pool_bind_set(struct ocelot *ocelot, int port,
1111 unsigned int sb_index, u16 tc_index,
1112 enum devlink_sb_pool_type pool_type,
1113 u16 pool_index, u32 threshold,
1114 struct netlink_ext_ack *extack);
1115 int ocelot_sb_occ_snapshot(struct ocelot *ocelot, unsigned int sb_index);
1116 int ocelot_sb_occ_max_clear(struct ocelot *ocelot, unsigned int sb_index);
1117 int ocelot_sb_occ_port_pool_get(struct ocelot *ocelot, int port,
1118 unsigned int sb_index, u16 pool_index,
1119 u32 *p_cur, u32 *p_max);
1120 int ocelot_sb_occ_tc_port_bind_get(struct ocelot *ocelot, int port,
1121 unsigned int sb_index, u16 tc_index,
1122 enum devlink_sb_pool_type pool_type,
1123 u32 *p_cur, u32 *p_max);
1125 int ocelot_port_configure_serdes(struct ocelot *ocelot, int port,
1126 struct device_node *portnp);
1128 void ocelot_phylink_mac_config(struct ocelot *ocelot, int port,
1129 unsigned int link_an_mode,
1130 const struct phylink_link_state *state);
1131 void ocelot_phylink_mac_link_down(struct ocelot *ocelot, int port,
1132 unsigned int link_an_mode,
1133 phy_interface_t interface,
1134 unsigned long quirks);
1135 void ocelot_phylink_mac_link_up(struct ocelot *ocelot, int port,
1136 struct phy_device *phydev,
1137 unsigned int link_an_mode,
1138 phy_interface_t interface,
1139 int speed, int duplex,
1140 bool tx_pause, bool rx_pause,
1141 unsigned long quirks);
1143 int ocelot_mact_lookup(struct ocelot *ocelot, int *dst_idx,
1144 const unsigned char mac[ETH_ALEN],
1145 unsigned int vid, enum macaccess_entry_type *type);
1146 int ocelot_mact_learn_streamdata(struct ocelot *ocelot, int dst_idx,
1147 const unsigned char mac[ETH_ALEN],
1149 enum macaccess_entry_type type,
1150 int sfid, int ssid);
1152 int ocelot_migrate_mdbs(struct ocelot *ocelot, unsigned long from_mask,
1153 unsigned long to_mask);
1155 int ocelot_vcap_policer_add(struct ocelot *ocelot, u32 pol_ix,
1156 struct ocelot_policer *pol);
1157 int ocelot_vcap_policer_del(struct ocelot *ocelot, u32 pol_ix);
1159 void ocelot_mm_irq(struct ocelot *ocelot);
1160 int ocelot_port_set_mm(struct ocelot *ocelot, int port,
1161 struct ethtool_mm_cfg *cfg,
1162 struct netlink_ext_ack *extack);
1163 int ocelot_port_get_mm(struct ocelot *ocelot, int port,
1164 struct ethtool_mm_state *state);
1165 int ocelot_port_mqprio(struct ocelot *ocelot, int port,
1166 struct tc_mqprio_qopt_offload *mqprio);
1167 void ocelot_port_update_preemptible_tcs(struct ocelot *ocelot, int port);
1169 #if IS_ENABLED(CONFIG_BRIDGE_MRP)
1170 int ocelot_mrp_add(struct ocelot *ocelot, int port,
1171 const struct switchdev_obj_mrp *mrp);
1172 int ocelot_mrp_del(struct ocelot *ocelot, int port,
1173 const struct switchdev_obj_mrp *mrp);
1174 int ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1175 const struct switchdev_obj_ring_role_mrp *mrp);
1176 int ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1177 const struct switchdev_obj_ring_role_mrp *mrp);
1179 static inline int ocelot_mrp_add(struct ocelot *ocelot, int port,
1180 const struct switchdev_obj_mrp *mrp)
1185 static inline int ocelot_mrp_del(struct ocelot *ocelot, int port,
1186 const struct switchdev_obj_mrp *mrp)
1192 ocelot_mrp_add_ring_role(struct ocelot *ocelot, int port,
1193 const struct switchdev_obj_ring_role_mrp *mrp)
1199 ocelot_mrp_del_ring_role(struct ocelot *ocelot, int port,
1200 const struct switchdev_obj_ring_role_mrp *mrp)
1206 void ocelot_pll5_init(struct ocelot *ocelot);