2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * Back ported to the 8xx platform (from the 8260 platform) by
24 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
33 * Controller registers
36 #define SDHCI_DMA_ADDRESS 0x00
38 #define SDHCI_BLOCK_SIZE 0x04
39 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
41 #define SDHCI_BLOCK_COUNT 0x06
43 #define SDHCI_ARGUMENT 0x08
45 #define SDHCI_TRANSFER_MODE 0x0C
46 #define SDHCI_TRNS_DMA 0x01
47 #define SDHCI_TRNS_BLK_CNT_EN 0x02
48 #define SDHCI_TRNS_ACMD12 0x04
49 #define SDHCI_TRNS_READ 0x10
50 #define SDHCI_TRNS_MULTI 0x20
52 #define SDHCI_COMMAND 0x0E
53 #define SDHCI_CMD_RESP_MASK 0x03
54 #define SDHCI_CMD_CRC 0x08
55 #define SDHCI_CMD_INDEX 0x10
56 #define SDHCI_CMD_DATA 0x20
57 #define SDHCI_CMD_ABORTCMD 0xC0
59 #define SDHCI_CMD_RESP_NONE 0x00
60 #define SDHCI_CMD_RESP_LONG 0x01
61 #define SDHCI_CMD_RESP_SHORT 0x02
62 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03
64 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff)) //to check f & 0xf
65 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
67 #define SDHCI_RESPONSE 0x10
69 #define SDHCI_BUFFER 0x20
71 #define SDHCI_PRESENT_STATE 0x24
72 #define SDHCI_CMD_INHIBIT 0x00000001
73 #define SDHCI_DATA_INHIBIT 0x00000002
74 #define SDHCI_DOING_WRITE 0x00000100
75 #define SDHCI_DOING_READ 0x00000200
76 #define SDHCI_SPACE_AVAILABLE 0x00000400
77 #define SDHCI_DATA_AVAILABLE 0x00000800
78 //#define SDHCI_CARD_PRESENT 0x00010000
79 //#define SDHCI_WRITE_PROTECT 0x00080000
81 #define SDHCI_HOST_CONTROL 0x28
82 #define SDHCI_CTRL_4BITBUS 0x02
83 #define SDHCI_CTRL_HISPD 0x04
85 #define SDHCI_POWER_CONTROL 0x29
86 #define SDHCI_POWER_ON 0x01
87 #define SDHCI_POWER_180 0x0A
88 #define SDHCI_POWER_300 0x0C
89 #define SDHCI_POWER_330 0x0E
91 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
93 #define SDHCI_WAKE_UP_CONTROL 0x2B
94 #define SDHCI_WAKE_ON_INT 0x01
95 #define SDHCI_WAKE_ON_INSERT 0x02
96 #define SDHCI_WAKE_ON_REMOVE 0x04
98 #define SDHCI_CLOCK_CONTROL 0x2C
99 #define SDHCI_DIVIDER_SHIFT 8
100 #define SDHCI_DIVIDER_HI_SHIFT 6
101 #define SDHCI_DIV_MASK 0xFF
102 #define SDHCI_DIV_MASK_LEN 8
103 #define SDHCI_DIV_HI_MASK 0x300
104 #define SDHCI_CLOCK_CARD_EN 0x0004
105 #define SDHCI_CLOCK_INT_STABLE 0x0002
106 #define SDHCI_CLOCK_INT_EN 0x0001
108 #define SDHCI_TIMEOUT_CONTROL 0x2E
110 #define SDHCI_SOFTWARE_RESET 0x2F
111 #define SDHCI_RESET_ALL 0x01
112 #define SDHCI_RESET_CMD 0x02
113 #define SDHCI_RESET_DATA 0x04
114 #define SDHCI_HW_RST 0x08
116 #define SDHCI_INT_STATUS 0x30
117 #define SDHCI_INT_ENABLE 0x34
118 #define SDHCI_SIGNAL_ENABLE 0x38
119 #define SDHCI_INT_RESPONSE 0x00000001
120 #define SDHCI_INT_DATA_END 0x00000002
121 #define SDHCI_INT_DMA_END 0x00000008
122 #define SDHCI_INT_SPACE_AVAIL 0x00000010
123 #define SDHCI_INT_DATA_AVAIL 0x00000020
124 //#define SDHCI_INT_CARD_INSERT 0x00000040
125 //#define SDHCI_INT_CARD_REMOVE 0x00000080
126 #define SDHCI_INT_CARD_INT 0x00000100
127 #define SDHCI_INT_ERROR 0x00008000
128 #define SDHCI_INT_TIMEOUT 0x00010000
129 #define SDHCI_INT_CRC 0x00020000
130 #define SDHCI_INT_END_BIT 0x00040000
131 #define SDHCI_INT_INDEX 0x00080000
132 #define SDHCI_INT_DATA_TIMEOUT 0x00100000
133 #define SDHCI_INT_DATA_CRC 0x00200000
134 #define SDHCI_INT_DATA_END_BIT 0x00400000
135 #define SDHCI_INT_BUS_POWER 0x00800000
136 #define SDHCI_INT_ACMD12ERR 0x01000000
138 #define SDHCI_INT_NORMAL_MASK 0x00007FFF
139 #define SDHCI_INT_ERROR_MASK 0xFFFF8000
141 #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
142 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
143 #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
144 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
145 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
146 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
147 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
149 #define SDHCI_ACMD12_ERR 0x3C
153 #define SDHCI_CAPABILITIES 0x40
154 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
155 #define SDHCI_TIMEOUT_CLK_SHIFT 0
156 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
157 #define SDHCI_CLOCK_BASE_MASK 0x00003F00
158 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
159 #define SDHCI_CLOCK_BASE_SHIFT 8
160 #define SDHCI_MAX_BLOCK_MASK 0x00030000
161 #define SDHCI_MAX_BLOCK_SHIFT 16
162 #define SDHCI_CAN_DO_HISPD 0x00200000
163 #define SDHCI_CAN_DO_SDMA 0x00400000
164 #define SDHCI_CAN_VDD_330 0x01000000
165 #define SDHCI_CAN_VDD_300 0x02000000
166 #define SDHCI_CAN_VDD_180 0x04000000
168 #define SDHCI_CAPABILITIES_1 0x44
170 #define SDHCI_MAX_CURRENT 0x48
172 /* 4C-4F reserved for more max current */
174 #define SDHCI_SET_ACMD12_ERROR 0x50
175 #define SDHCI_SET_INT_ERROR 0x52
177 #define SDHCI_ADMA_ERROR 0x54
181 #define SDHCI_ADMA_ADDRESS 0x58
185 #define SDHCI_SLOT_INT_STATUS 0xFC
187 #define SDHCI_HOST_VERSION 0xFE
188 #define SDHCI_VENDOR_VER_MASK 0xFF00
189 #define SDHCI_VENDOR_VER_SHIFT 8
190 #define SDHCI_SPEC_VER_MASK 0x00FF
191 #define SDHCI_SPEC_VER_SHIFT 0
192 #define SDHCI_SPEC_100 0
193 #define SDHCI_SPEC_200 1
194 #define SDHCI_SPEC_300 2
197 * End of controller registers.
204 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
205 #define SDHCI_QUIRK_REG32_RW (1 << 1)
207 /* to make gcc happy */
211 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
213 #define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
214 #define SDHCI_DEFAULT_BOUNDARY_ARG (7)
216 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
217 u32 (*read_l)(struct sdhci_host *host, int reg);
218 u16 (*read_w)(struct sdhci_host *host, int reg);
219 u8 (*read_b)(struct sdhci_host *host, int reg);
220 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
221 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
222 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
230 unsigned int version;
233 const struct sdhci_ops *ops;
236 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
238 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
240 if (unlikely(host->ops->write_l))
241 host->ops->write_l(host, val, reg);
243 writel(val, host->ioaddr + reg);
246 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
248 if (unlikely(host->ops->write_w))
249 host->ops->write_w(host, val, reg);
251 writew(val, host->ioaddr + reg);
254 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
256 if (unlikely(host->ops->write_b))
257 host->ops->write_b(host, val, reg);
259 writeb(val, host->ioaddr + reg);
262 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
264 if (unlikely(host->ops->read_l))
265 return host->ops->read_l(host, reg);
267 return readl(host->ioaddr + reg);
270 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
272 if (unlikely(host->ops->read_w))
273 return host->ops->read_w(host, reg);
275 return readw(host->ioaddr + reg);
278 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
280 if (unlikely(host->ops->read_b))
281 return host->ops->read_b(host, reg);
283 return readb(host->ioaddr + reg);
288 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
290 writel(val, host->ioaddr + reg);
293 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
295 writew(val, host->ioaddr + reg);
298 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
300 writeb(val, host->ioaddr + reg);
302 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
304 return readl(host->ioaddr + reg);
307 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
309 return readw(host->ioaddr + reg);
312 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
314 return readb(host->ioaddr + reg);
318 static inline void sdhci_sdclk_enable(struct sdhci_host *host, u8 val)
322 regVal = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
325 regVal &= ~SDHCI_CLOCK_CARD_EN;
326 sdhci_writel(host, regVal, SDHCI_CLOCK_CONTROL);
329 regVal |= SDHCI_CLOCK_CARD_EN;
330 sdhci_writel(host, regVal, SDHCI_CLOCK_CONTROL);
334 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk);
335 #endif /* __SDHCI_HW_H */