Merge branch 'master' of git://www.denx.de/git/u-boot-sh
[platform/kernel/u-boot.git] / include / s3c2410.h
1 /*
2  * (C) Copyright 2003
3  * David Müller ELSOFT AG Switzerland. d.mueller@elsoft.ch
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23
24 /************************************************
25  * NAME     : s3c2410.h
26  * Version  : 31.3.2003
27  *
28  * Based on S3C2410X User's manual Rev 1.1
29  ************************************************/
30
31 #ifndef __S3C2410_H__
32 #define __S3C2410_H__
33
34 #define S3C24X0_UART_CHANNELS   3
35 #define S3C24X0_SPI_CHANNELS    2
36
37 /* S3C2410 only supports 512 Byte HW ECC */
38 #define S3C2410_ECCSIZE         512
39 #define S3C2410_ECCBYTES        3
40
41 typedef enum {
42         S3C24X0_UART0,
43         S3C24X0_UART1,
44         S3C24X0_UART2
45 } S3C24X0_UARTS_NR;
46
47 /* S3C2410 device base addresses */
48 #define S3C24X0_MEMCTL_BASE             0x48000000
49 #define S3C24X0_USB_HOST_BASE           0x49000000
50 #define S3C24X0_INTERRUPT_BASE          0x4A000000
51 #define S3C24X0_DMA_BASE                0x4B000000
52 #define S3C24X0_CLOCK_POWER_BASE        0x4C000000
53 #define S3C24X0_LCD_BASE                0x4D000000
54 #define S3C2410_NAND_BASE               0x4E000000
55 #define S3C24X0_UART_BASE               0x50000000
56 #define S3C24X0_TIMER_BASE              0x51000000
57 #define S3C24X0_USB_DEVICE_BASE         0x52000140
58 #define S3C24X0_WATCHDOG_BASE           0x53000000
59 #define S3C24X0_I2C_BASE                0x54000000
60 #define S3C24X0_I2S_BASE                0x55000000
61 #define S3C24X0_GPIO_BASE               0x56000000
62 #define S3C24X0_RTC_BASE                0x57000000
63 #define S3C2410_ADC_BASE                0x58000000
64 #define S3C24X0_SPI_BASE                0x59000000
65 #define S3C2410_SDI_BASE                0x5A000000
66
67
68 /* include common stuff */
69 #include <s3c24x0.h>
70
71
72 static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
73 {
74         return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
75 }
76 static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
77 {
78         return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
79 }
80 static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
81 {
82         return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
83 }
84 static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
85 {
86         return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
87 }
88 static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
89 {
90         return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
91 }
92 static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
93 {
94         return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
95 }
96 static inline S3C2410_NAND * S3C2410_GetBase_NAND(void)
97 {
98         return (S3C2410_NAND * const)S3C2410_NAND_BASE;
99 }
100 static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
101 {
102         return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
103 }
104 static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
105 {
106         return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
107 }
108 static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
109 {
110         return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
111 }
112 static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
113 {
114         return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
115 }
116 static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
117 {
118         return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
119 }
120 static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
121 {
122         return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
123 }
124 static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
125 {
126         return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
127 }
128 static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
129 {
130         return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
131 }
132 static inline S3C2410_ADC * S3C2410_GetBase_ADC(void)
133 {
134         return (S3C2410_ADC * const)S3C2410_ADC_BASE;
135 }
136 static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
137 {
138         return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
139 }
140 static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
141 {
142         return (S3C2410_SDI * const)S3C2410_SDI_BASE;
143 }
144
145
146 /* ISR */
147 #define pISR_RESET              (*(unsigned *)(_ISR_STARTADDRESS+0x0))
148 #define pISR_UNDEF              (*(unsigned *)(_ISR_STARTADDRESS+0x4))
149 #define pISR_SWI                (*(unsigned *)(_ISR_STARTADDRESS+0x8))
150 #define pISR_PABORT             (*(unsigned *)(_ISR_STARTADDRESS+0xC))
151 #define pISR_DABORT             (*(unsigned *)(_ISR_STARTADDRESS+0x10))
152 #define pISR_RESERVED           (*(unsigned *)(_ISR_STARTADDRESS+0x14))
153 #define pISR_IRQ                (*(unsigned *)(_ISR_STARTADDRESS+0x18))
154 #define pISR_FIQ                (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
155
156 #define pISR_EINT0              (*(unsigned *)(_ISR_STARTADDRESS+0x20))
157 #define pISR_EINT1              (*(unsigned *)(_ISR_STARTADDRESS+0x24))
158 #define pISR_EINT2              (*(unsigned *)(_ISR_STARTADDRESS+0x28))
159 #define pISR_EINT3              (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
160 #define pISR_EINT4_7            (*(unsigned *)(_ISR_STARTADDRESS+0x30))
161 #define pISR_EINT8_23           (*(unsigned *)(_ISR_STARTADDRESS+0x34))
162 #define pISR_BAT_FLT            (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
163 #define pISR_TICK               (*(unsigned *)(_ISR_STARTADDRESS+0x40))
164 #define pISR_WDT                (*(unsigned *)(_ISR_STARTADDRESS+0x44))
165 #define pISR_TIMER0             (*(unsigned *)(_ISR_STARTADDRESS+0x48))
166 #define pISR_TIMER1             (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
167 #define pISR_TIMER2             (*(unsigned *)(_ISR_STARTADDRESS+0x50))
168 #define pISR_TIMER3             (*(unsigned *)(_ISR_STARTADDRESS+0x54))
169 #define pISR_TIMER4             (*(unsigned *)(_ISR_STARTADDRESS+0x58))
170 #define pISR_UART2              (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
171 #define pISR_NOTUSED            (*(unsigned *)(_ISR_STARTADDRESS+0x60))
172 #define pISR_DMA0               (*(unsigned *)(_ISR_STARTADDRESS+0x64))
173 #define pISR_DMA1               (*(unsigned *)(_ISR_STARTADDRESS+0x68))
174 #define pISR_DMA2               (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
175 #define pISR_DMA3               (*(unsigned *)(_ISR_STARTADDRESS+0x70))
176 #define pISR_SDI                (*(unsigned *)(_ISR_STARTADDRESS+0x74))
177 #define pISR_SPI0               (*(unsigned *)(_ISR_STARTADDRESS+0x78))
178 #define pISR_UART1              (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
179 #define pISR_USBD               (*(unsigned *)(_ISR_STARTADDRESS+0x84))
180 #define pISR_USBH               (*(unsigned *)(_ISR_STARTADDRESS+0x88))
181 #define pISR_IIC                (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
182 #define pISR_UART0              (*(unsigned *)(_ISR_STARTADDRESS+0x90))
183 #define pISR_SPI1               (*(unsigned *)(_ISR_STARTADDRESS+0x94))
184 #define pISR_RTC                (*(unsigned *)(_ISR_STARTADDRESS+0x98))
185 #define pISR_ADC                (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
186
187
188 /* PENDING BIT */
189 #define BIT_EINT0               (0x1)
190 #define BIT_EINT1               (0x1<<1)
191 #define BIT_EINT2               (0x1<<2)
192 #define BIT_EINT3               (0x1<<3)
193 #define BIT_EINT4_7             (0x1<<4)
194 #define BIT_EINT8_23            (0x1<<5)
195 #define BIT_BAT_FLT             (0x1<<7)
196 #define BIT_TICK                (0x1<<8)
197 #define BIT_WDT                 (0x1<<9)
198 #define BIT_TIMER0              (0x1<<10)
199 #define BIT_TIMER1              (0x1<<11)
200 #define BIT_TIMER2              (0x1<<12)
201 #define BIT_TIMER3              (0x1<<13)
202 #define BIT_TIMER4              (0x1<<14)
203 #define BIT_UART2               (0x1<<15)
204 #define BIT_LCD                 (0x1<<16)
205 #define BIT_DMA0                (0x1<<17)
206 #define BIT_DMA1                (0x1<<18)
207 #define BIT_DMA2                (0x1<<19)
208 #define BIT_DMA3                (0x1<<20)
209 #define BIT_SDI                 (0x1<<21)
210 #define BIT_SPI0                (0x1<<22)
211 #define BIT_UART1               (0x1<<23)
212 #define BIT_USBD                (0x1<<25)
213 #define BIT_USBH                (0x1<<26)
214 #define BIT_IIC                 (0x1<<27)
215 #define BIT_UART0               (0x1<<28)
216 #define BIT_SPI1                (0x1<<29)
217 #define BIT_RTC                 (0x1<<30)
218 #define BIT_ADC                 (0x1<<31)
219 #define BIT_ALLMSK              (0xFFFFFFFF)
220
221 #define ClearPending(bit) {\
222                  rSRCPND = bit;\
223                  rINTPND = bit;\
224                  rINTPND;\
225                  }
226 /* Wait until rINTPND is changed for the case that the ISR is very short. */
227 #endif /*__S3C2410_H__*/