Merge git://www.denx.de/git/u-boot
[kernel/u-boot.git] / include / radeon.h
1 #ifndef _RADEON_H
2 #define _RADEON_H
3
4
5 #define RADEON_REGSIZE                  0x4000
6
7
8 #define MM_INDEX                        0x0000
9 #define MM_DATA                         0x0004
10 #define BUS_CNTL                        0x0030
11 #define HI_STAT                         0x004C
12 #define BUS_CNTL1                       0x0034
13 #define I2C_CNTL_1                      0x0094
14 #define CONFIG_CNTL                     0x00E0
15 #define CONFIG_MEMSIZE                  0x00F8
16 #define CONFIG_APER_0_BASE              0x0100
17 #define CONFIG_APER_1_BASE              0x0104
18 #define CONFIG_APER_SIZE                0x0108
19 #define CONFIG_REG_1_BASE               0x010C
20 #define CONFIG_REG_APER_SIZE            0x0110
21 #define PAD_AGPINPUT_DELAY              0x0164
22 #define PAD_CTLR_STRENGTH               0x0168
23 #define PAD_CTLR_UPDATE                 0x016C
24 #define PAD_CTLR_MISC                   0x0aa0
25 #define AGP_CNTL                        0x0174
26 #define BM_STATUS                       0x0160
27 #define CAP0_TRIG_CNTL                  0x0950
28 #define CAP1_TRIG_CNTL                  0x09c0
29 #define VIPH_CONTROL                    0x0C40
30 #define VENDOR_ID                       0x0F00
31 #define DEVICE_ID                       0x0F02
32 #define COMMAND                         0x0F04
33 #define STATUS                          0x0F06
34 #define REVISION_ID                     0x0F08
35 #define REGPROG_INF                     0x0F09
36 #define SUB_CLASS                       0x0F0A
37 #define BASE_CODE                       0x0F0B
38 #define CACHE_LINE                      0x0F0C
39 #define LATENCY                         0x0F0D
40 #define HEADER                          0x0F0E
41 #define BIST                            0x0F0F
42 #define REG_MEM_BASE                    0x0F10
43 #define REG_IO_BASE                     0x0F14
44 #define REG_REG_BASE                    0x0F18
45 #define ADAPTER_ID                      0x0F2C
46 #define BIOS_ROM                        0x0F30
47 #define CAPABILITIES_PTR                0x0F34
48 #define INTERRUPT_LINE                  0x0F3C
49 #define INTERRUPT_PIN                   0x0F3D
50 #define MIN_GRANT                       0x0F3E
51 #define MAX_LATENCY                     0x0F3F
52 #define ADAPTER_ID_W                    0x0F4C
53 #define PMI_CAP_ID                      0x0F50
54 #define PMI_NXT_CAP_PTR                 0x0F51
55 #define PMI_PMC_REG                     0x0F52
56 #define PM_STATUS                       0x0F54
57 #define PMI_DATA                        0x0F57
58 #define AGP_CAP_ID                      0x0F58
59 #define AGP_STATUS                      0x0F5C
60 #define AGP_COMMAND                     0x0F60
61 #define AIC_CTRL                        0x01D0
62 #define AIC_STAT                        0x01D4
63 #define AIC_PT_BASE                     0x01D8
64 #define AIC_LO_ADDR                     0x01DC
65 #define AIC_HI_ADDR                     0x01E0
66 #define AIC_TLB_ADDR                    0x01E4
67 #define AIC_TLB_DATA                    0x01E8
68 #define DAC_CNTL                        0x0058
69 #define DAC_CNTL2                       0x007c
70 #define CRTC_GEN_CNTL                   0x0050
71 #define MEM_CNTL                        0x0140
72 #define MC_CNTL                         0x0140
73 #define EXT_MEM_CNTL                    0x0144
74 #define MC_TIMING_CNTL                  0x0144
75 #define MC_AGP_LOCATION                 0x014C
76 #define MEM_IO_CNTL_A0                  0x0178
77 #define MEM_REFRESH_CNTL                0x0178
78 #define MEM_INIT_LATENCY_TIMER          0x0154
79 #define MC_INIT_GFX_LAT_TIMER           0x0154
80 #define MEM_SDRAM_MODE_REG              0x0158
81 #define AGP_BASE                        0x0170
82 #define MEM_IO_CNTL_A1                  0x017C
83 #define MC_READ_CNTL_AB                 0x017C
84 #define MEM_IO_CNTL_B0                  0x0180
85 #define MC_INIT_MISC_LAT_TIMER          0x0180
86 #define MEM_IO_CNTL_B1                  0x0184
87 #define MC_IOPAD_CNTL                   0x0184
88 #define MC_DEBUG                        0x0188
89 #define MC_STATUS                       0x0150
90 #define MEM_IO_OE_CNTL                  0x018C
91 #define MC_CHIP_IO_OE_CNTL_AB           0x018C
92 #define MC_FB_LOCATION                  0x0148
93 /* #define MC_FB_LOCATION               0x0188 */
94 #define HOST_PATH_CNTL                  0x0130
95 #define MEM_VGA_WP_SEL                  0x0038
96 #define MEM_VGA_RP_SEL                  0x003C
97 #define HDP_DEBUG                       0x0138
98 #define SW_SEMAPHORE                    0x013C
99 #define CRTC2_GEN_CNTL                  0x03f8
100 #define CRTC2_DISPLAY_BASE_ADDR         0x033c
101 #define SURFACE_CNTL                    0x0B00
102 #define SURFACE0_LOWER_BOUND            0x0B04
103 #define SURFACE1_LOWER_BOUND            0x0B14
104 #define SURFACE2_LOWER_BOUND            0x0B24
105 #define SURFACE3_LOWER_BOUND            0x0B34
106 #define SURFACE4_LOWER_BOUND            0x0B44
107 #define SURFACE5_LOWER_BOUND            0x0B54
108 #define SURFACE6_LOWER_BOUND            0x0B64
109 #define SURFACE7_LOWER_BOUND            0x0B74
110 #define SURFACE0_UPPER_BOUND            0x0B08
111 #define SURFACE1_UPPER_BOUND            0x0B18
112 #define SURFACE2_UPPER_BOUND            0x0B28
113 #define SURFACE3_UPPER_BOUND            0x0B38
114 #define SURFACE4_UPPER_BOUND            0x0B48
115 #define SURFACE5_UPPER_BOUND            0x0B58
116 #define SURFACE6_UPPER_BOUND            0x0B68
117 #define SURFACE7_UPPER_BOUND            0x0B78
118 #define SURFACE0_INFO                   0x0B0C
119 #define SURFACE1_INFO                   0x0B1C
120 #define SURFACE2_INFO                   0x0B2C
121 #define SURFACE3_INFO                   0x0B3C
122 #define SURFACE4_INFO                   0x0B4C
123 #define SURFACE5_INFO                   0x0B5C
124 #define SURFACE6_INFO                   0x0B6C
125 #define SURFACE7_INFO                   0x0B7C
126 #define SURFACE_ACCESS_FLAGS            0x0BF8
127 #define SURFACE_ACCESS_CLR              0x0BFC
128 #define GEN_INT_CNTL                    0x0040
129 #define GEN_INT_STATUS                  0x0044
130 #define CRTC_EXT_CNTL                   0x0054
131 #define RB3D_CNTL                       0x1C3C
132 #define WAIT_UNTIL                      0x1720
133 #define ISYNC_CNTL                      0x1724
134 #define RBBM_GUICNTL                    0x172C
135 #define RBBM_STATUS                     0x0E40
136 #define RBBM_STATUS_alt_1               0x1740
137 #define RBBM_CNTL                       0x00EC
138 #define RBBM_CNTL_alt_1                 0x0E44
139 #define RBBM_SOFT_RESET                 0x00F0
140 #define RBBM_SOFT_RESET_alt_1           0x0E48
141 #define NQWAIT_UNTIL                    0x0E50
142 #define RBBM_DEBUG                      0x0E6C
143 #define RBBM_CMDFIFO_ADDR               0x0E70
144 #define RBBM_CMDFIFO_DATAL              0x0E74
145 #define RBBM_CMDFIFO_DATAH              0x0E78
146 #define RBBM_CMDFIFO_STAT               0x0E7C
147 #define CRTC_STATUS                     0x005C
148 #define GPIO_VGA_DDC                    0x0060
149 #define GPIO_DVI_DDC                    0x0064
150 #define GPIO_MONID                      0x0068
151 #define GPIO_CRT2_DDC                   0x006c
152 #define PALETTE_INDEX                   0x00B0
153 #define PALETTE_DATA                    0x00B4
154 #define PALETTE_30_DATA                 0x00B8
155 #define CRTC_H_TOTAL_DISP               0x0200
156 #define CRTC_H_SYNC_STRT_WID            0x0204
157 #define CRTC_V_TOTAL_DISP               0x0208
158 #define CRTC_V_SYNC_STRT_WID            0x020C
159 #define CRTC_VLINE_CRNT_VLINE           0x0210
160 #define CRTC_CRNT_FRAME                 0x0214
161 #define CRTC_GUI_TRIG_VLINE             0x0218
162 #define CRTC_DEBUG                      0x021C
163 #define CRTC_OFFSET_RIGHT               0x0220
164 #define CRTC_OFFSET                     0x0224
165 #define CRTC_OFFSET_CNTL                0x0228
166 #define CRTC_PITCH                      0x022C
167 #define OVR_CLR                         0x0230
168 #define OVR_WID_LEFT_RIGHT              0x0234
169 #define OVR_WID_TOP_BOTTOM              0x0238
170 #define DISPLAY_BASE_ADDR               0x023C
171 #define SNAPSHOT_VH_COUNTS              0x0240
172 #define SNAPSHOT_F_COUNT                0x0244
173 #define N_VIF_COUNT                     0x0248
174 #define SNAPSHOT_VIF_COUNT              0x024C
175 #define FP_CRTC_H_TOTAL_DISP            0x0250
176 #define FP_CRTC_V_TOTAL_DISP            0x0254
177 #define CRT_CRTC_H_SYNC_STRT_WID        0x0258
178 #define CRT_CRTC_V_SYNC_STRT_WID        0x025C
179 #define CUR_OFFSET                      0x0260
180 #define CUR_HORZ_VERT_POSN              0x0264
181 #define CUR_HORZ_VERT_OFF               0x0268
182 #define CUR_CLR0                        0x026C
183 #define CUR_CLR1                        0x0270
184 #define FP_HORZ_VERT_ACTIVE             0x0278
185 #define CRTC_MORE_CNTL                  0x027C
186 #define CRTC_H_CUTOFF_ACTIVE_EN         (1<<4)
187 #define CRTC_V_CUTOFF_ACTIVE_EN         (1<<5)
188 #define DAC_EXT_CNTL                    0x0280
189 #define FP_GEN_CNTL                     0x0284
190 #define FP_HORZ_STRETCH                 0x028C
191 #define FP_VERT_STRETCH                 0x0290
192 #define FP_H_SYNC_STRT_WID              0x02C4
193 #define FP_V_SYNC_STRT_WID              0x02C8
194 #define AUX_WINDOW_HORZ_CNTL            0x02D8
195 #define AUX_WINDOW_VERT_CNTL            0x02DC
196 /* #define DDA_CONFIG                   0x02e0 */
197 /* #define DDA_ON_OFF                   0x02e4 */
198 #define DVI_I2C_CNTL_1                  0x02e4
199 #define GRPH_BUFFER_CNTL                0x02F0
200 #define GRPH2_BUFFER_CNTL               0x03F0
201 #define VGA_BUFFER_CNTL                 0x02F4
202 #define OV0_Y_X_START                   0x0400
203 #define OV0_Y_X_END                     0x0404
204 #define OV0_PIPELINE_CNTL               0x0408
205 #define OV0_REG_LOAD_CNTL               0x0410
206 #define OV0_SCALE_CNTL                  0x0420
207 #define OV0_V_INC                       0x0424
208 #define OV0_P1_V_ACCUM_INIT             0x0428
209 #define OV0_P23_V_ACCUM_INIT            0x042C
210 #define OV0_P1_BLANK_LINES_AT_TOP       0x0430
211 #define OV0_P23_BLANK_LINES_AT_TOP      0x0434
212 #define OV0_BASE_ADDR                   0x043C
213 #define OV0_VID_BUF0_BASE_ADRS          0x0440
214 #define OV0_VID_BUF1_BASE_ADRS          0x0444
215 #define OV0_VID_BUF2_BASE_ADRS          0x0448
216 #define OV0_VID_BUF3_BASE_ADRS          0x044C
217 #define OV0_VID_BUF4_BASE_ADRS          0x0450
218 #define OV0_VID_BUF5_BASE_ADRS          0x0454
219 #define OV0_VID_BUF_PITCH0_VALUE        0x0460
220 #define OV0_VID_BUF_PITCH1_VALUE        0x0464
221 #define OV0_AUTO_FLIP_CNTRL             0x0470
222 #define OV0_DEINTERLACE_PATTERN         0x0474
223 #define OV0_SUBMIT_HISTORY              0x0478
224 #define OV0_H_INC                       0x0480
225 #define OV0_STEP_BY                     0x0484
226 #define OV0_P1_H_ACCUM_INIT             0x0488
227 #define OV0_P23_H_ACCUM_INIT            0x048C
228 #define OV0_P1_X_START_END              0x0494
229 #define OV0_P2_X_START_END              0x0498
230 #define OV0_P3_X_START_END              0x049C
231 #define OV0_FILTER_CNTL                 0x04A0
232 #define OV0_FOUR_TAP_COEF_0             0x04B0
233 #define OV0_FOUR_TAP_COEF_1             0x04B4
234 #define OV0_FOUR_TAP_COEF_2             0x04B8
235 #define OV0_FOUR_TAP_COEF_3             0x04BC
236 #define OV0_FOUR_TAP_COEF_4             0x04C0
237 #define OV0_FLAG_CNTRL                  0x04DC
238 #define OV0_SLICE_CNTL                  0x04E0
239 #define OV0_VID_KEY_CLR_LOW             0x04E4
240 #define OV0_VID_KEY_CLR_HIGH            0x04E8
241 #define OV0_GRPH_KEY_CLR_LOW            0x04EC
242 #define OV0_GRPH_KEY_CLR_HIGH           0x04F0
243 #define OV0_KEY_CNTL                    0x04F4
244 #define OV0_TEST                        0x04F8
245 #define SUBPIC_CNTL                     0x0540
246 #define SUBPIC_DEFCOLCON                0x0544
247 #define SUBPIC_Y_X_START                0x054C
248 #define SUBPIC_Y_X_END                  0x0550
249 #define SUBPIC_V_INC                    0x0554
250 #define SUBPIC_H_INC                    0x0558
251 #define SUBPIC_BUF0_OFFSET              0x055C
252 #define SUBPIC_BUF1_OFFSET              0x0560
253 #define SUBPIC_LC0_OFFSET               0x0564
254 #define SUBPIC_LC1_OFFSET               0x0568
255 #define SUBPIC_PITCH                    0x056C
256 #define SUBPIC_BTN_HLI_COLCON           0x0570
257 #define SUBPIC_BTN_HLI_Y_X_START        0x0574
258 #define SUBPIC_BTN_HLI_Y_X_END          0x0578
259 #define SUBPIC_PALETTE_INDEX            0x057C
260 #define SUBPIC_PALETTE_DATA             0x0580
261 #define SUBPIC_H_ACCUM_INIT             0x0584
262 #define SUBPIC_V_ACCUM_INIT             0x0588
263 #define DISP_MISC_CNTL                  0x0D00
264 #define DAC_MACRO_CNTL                  0x0D04
265 #define DISP_PWR_MAN                    0x0D08
266 #define DISP_TEST_DEBUG_CNTL            0x0D10
267 #define DISP_HW_DEBUG                   0x0D14
268 #define DAC_CRC_SIG1                    0x0D18
269 #define DAC_CRC_SIG2                    0x0D1C
270 #define OV0_LIN_TRANS_A                 0x0D20
271 #define OV0_LIN_TRANS_B                 0x0D24
272 #define OV0_LIN_TRANS_C                 0x0D28
273 #define OV0_LIN_TRANS_D                 0x0D2C
274 #define OV0_LIN_TRANS_E                 0x0D30
275 #define OV0_LIN_TRANS_F                 0x0D34
276 #define OV0_GAMMA_0_F                   0x0D40
277 #define OV0_GAMMA_10_1F                 0x0D44
278 #define OV0_GAMMA_20_3F                 0x0D48
279 #define OV0_GAMMA_40_7F                 0x0D4C
280 #define OV0_GAMMA_380_3BF               0x0D50
281 #define OV0_GAMMA_3C0_3FF               0x0D54
282 #define DISP_MERGE_CNTL                 0x0D60
283 #define DISP_OUTPUT_CNTL                0x0D64
284 #define DISP_LIN_TRANS_GRPH_A           0x0D80
285 #define DISP_LIN_TRANS_GRPH_B           0x0D84
286 #define DISP_LIN_TRANS_GRPH_C           0x0D88
287 #define DISP_LIN_TRANS_GRPH_D           0x0D8C
288 #define DISP_LIN_TRANS_GRPH_E           0x0D90
289 #define DISP_LIN_TRANS_GRPH_F           0x0D94
290 #define DISP_LIN_TRANS_VID_A            0x0D98
291 #define DISP_LIN_TRANS_VID_B            0x0D9C
292 #define DISP_LIN_TRANS_VID_C            0x0DA0
293 #define DISP_LIN_TRANS_VID_D            0x0DA4
294 #define DISP_LIN_TRANS_VID_E            0x0DA8
295 #define DISP_LIN_TRANS_VID_F            0x0DAC
296 #define RMX_HORZ_FILTER_0TAP_COEF       0x0DB0
297 #define RMX_HORZ_FILTER_1TAP_COEF       0x0DB4
298 #define RMX_HORZ_FILTER_2TAP_COEF       0x0DB8
299 #define RMX_HORZ_PHASE                  0x0DBC
300 #define DAC_EMBEDDED_SYNC_CNTL          0x0DC0
301 #define DAC_BROAD_PULSE                 0x0DC4
302 #define DAC_SKEW_CLKS                   0x0DC8
303 #define DAC_INCR                        0x0DCC
304 #define DAC_NEG_SYNC_LEVEL              0x0DD0
305 #define DAC_POS_SYNC_LEVEL              0x0DD4
306 #define DAC_BLANK_LEVEL                 0x0DD8
307 #define CLOCK_CNTL_INDEX                0x0008
308 #define CLOCK_CNTL_DATA                 0x000C
309 #define CP_RB_CNTL                      0x0704
310 #define CP_RB_BASE                      0x0700
311 #define CP_RB_RPTR_ADDR                 0x070C
312 #define CP_RB_RPTR                      0x0710
313 #define CP_RB_WPTR                      0x0714
314 #define CP_RB_WPTR_DELAY                0x0718
315 #define CP_IB_BASE                      0x0738
316 #define CP_IB_BUFSZ                     0x073C
317 #define SCRATCH_REG0                    0x15E0
318 #define GUI_SCRATCH_REG0                0x15E0
319 #define SCRATCH_REG1                    0x15E4
320 #define GUI_SCRATCH_REG1                0x15E4
321 #define SCRATCH_REG2                    0x15E8
322 #define GUI_SCRATCH_REG2                0x15E8
323 #define SCRATCH_REG3                    0x15EC
324 #define GUI_SCRATCH_REG3                0x15EC
325 #define SCRATCH_REG4                    0x15F0
326 #define GUI_SCRATCH_REG4                0x15F0
327 #define SCRATCH_REG5                    0x15F4
328 #define GUI_SCRATCH_REG5                0x15F4
329 #define SCRATCH_UMSK                    0x0770
330 #define SCRATCH_ADDR                    0x0774
331 #define DP_BRUSH_FRGD_CLR               0x147C
332 #define DP_BRUSH_BKGD_CLR               0x1478
333 #define DST_LINE_START                  0x1600
334 #define DST_LINE_END                    0x1604
335 #define SRC_OFFSET                      0x15AC
336 #define SRC_PITCH                       0x15B0
337 #define SRC_TILE                        0x1704
338 #define SRC_PITCH_OFFSET                0x1428
339 #define SRC_X                           0x1414
340 #define SRC_Y                           0x1418
341 #define SRC_X_Y                         0x1590
342 #define SRC_Y_X                         0x1434
343 #define DST_Y_X                         0x1438
344 #define DST_WIDTH_HEIGHT                0x1598
345 #define DST_HEIGHT_WIDTH                0x143c
346 #define DST_OFFSET                      0x1404
347 #define SRC_CLUT_ADDRESS                0x1780
348 #define SRC_CLUT_DATA                   0x1784
349 #define SRC_CLUT_DATA_RD                0x1788
350 #define HOST_DATA0                      0x17C0
351 #define HOST_DATA1                      0x17C4
352 #define HOST_DATA2                      0x17C8
353 #define HOST_DATA3                      0x17CC
354 #define HOST_DATA4                      0x17D0
355 #define HOST_DATA5                      0x17D4
356 #define HOST_DATA6                      0x17D8
357 #define HOST_DATA7                      0x17DC
358 #define HOST_DATA_LAST                  0x17E0
359 #define DP_SRC_ENDIAN                   0x15D4
360 #define DP_SRC_FRGD_CLR                 0x15D8
361 #define DP_SRC_BKGD_CLR                 0x15DC
362 #define SC_LEFT                         0x1640
363 #define SC_RIGHT                        0x1644
364 #define SC_TOP                          0x1648
365 #define SC_BOTTOM                       0x164C
366 #define SRC_SC_RIGHT                    0x1654
367 #define SRC_SC_BOTTOM                   0x165C
368 #define DP_CNTL                         0x16C0
369 #define DP_CNTL_XDIR_YDIR_YMAJOR        0x16D0
370 #define DP_DATATYPE                     0x16C4
371 #define DP_MIX                          0x16C8
372 #define DP_WRITE_MSK                    0x16CC
373 #define DP_XOP                          0x17F8
374 #define CLR_CMP_CLR_SRC                 0x15C4
375 #define CLR_CMP_CLR_DST                 0x15C8
376 #define CLR_CMP_CNTL                    0x15C0
377 #define CLR_CMP_MSK                     0x15CC
378 #define DSTCACHE_MODE                   0x1710
379 #define DSTCACHE_CTLSTAT                0x1714
380 #define DEFAULT_PITCH_OFFSET            0x16E0
381 #define DEFAULT_SC_BOTTOM_RIGHT         0x16E8
382 #define DEFAULT_SC_TOP_LEFT             0x16EC
383 #define SRC_PITCH_OFFSET                0x1428
384 #define DST_PITCH_OFFSET                0x142C
385 #define DP_GUI_MASTER_CNTL              0x146C
386 #define SC_TOP_LEFT                     0x16EC
387 #define SC_BOTTOM_RIGHT                 0x16F0
388 #define SRC_SC_BOTTOM_RIGHT             0x16F4
389 #define RB2D_DSTCACHE_MODE              0x3428
390 #define RB2D_DSTCACHE_CTLSTAT           0x342C
391 #define LVDS_GEN_CNTL                   0x02d0
392 #define LVDS_PLL_CNTL                   0x02d4
393 #define FP2_GEN_CNTL                    0x0288
394 #define TMDS_CNTL                       0x0294
395 #define TMDS_CRC                        0x02a0
396 #define TMDS_TRANSMITTER_CNTL           0x02a4
397 #define MPP_TB_CONFIG                   0x01c0
398 #define PAMAC0_DLY_CNTL                 0x0a94
399 #define PAMAC1_DLY_CNTL                 0x0a98
400 #define PAMAC2_DLY_CNTL                 0x0a9c
401 #define FW_CNTL                         0x0118
402 #define FCP_CNTL                        0x0910
403 #define VGA_DDA_ON_OFF                  0x02ec
404 #define TV_MASTER_CNTL                  0x0800
405
406 /* #define BASE_CODE                    0x0f0b */
407 #define BIOS_0_SCRATCH                  0x0010
408 #define BIOS_1_SCRATCH                  0x0014
409 #define BIOS_2_SCRATCH                  0x0018
410 #define BIOS_3_SCRATCH                  0x001c
411 #define BIOS_4_SCRATCH                  0x0020
412 #define BIOS_5_SCRATCH                  0x0024
413 #define BIOS_6_SCRATCH                  0x0028
414 #define BIOS_7_SCRATCH                  0x002c
415
416 #define HDP_SOFT_RESET                  (1 << 26)
417
418 #define TV_DAC_CNTL                     0x088c
419 #define GPIOPAD_MASK                    0x0198
420 #define GPIOPAD_A                       0x019c
421 #define GPIOPAD_EN                      0x01a0
422 #define GPIOPAD_Y                       0x01a4
423 #define ZV_LCDPAD_MASK                  0x01a8
424 #define ZV_LCDPAD_A                     0x01ac
425 #define ZV_LCDPAD_EN                    0x01b0
426 #define ZV_LCDPAD_Y                     0x01b4
427
428 /* PLL Registers */
429 #define CLK_PIN_CNTL                    0x0001
430 #define PPLL_CNTL                       0x0002
431 #define PPLL_REF_DIV                    0x0003
432 #define PPLL_DIV_0                      0x0004
433 #define PPLL_DIV_1                      0x0005
434 #define PPLL_DIV_2                      0x0006
435 #define PPLL_DIV_3                      0x0007
436 #define VCLK_ECP_CNTL                   0x0008
437 #define HTOTAL_CNTL                     0x0009
438 #define M_SPLL_REF_FB_DIV               0x000a
439 #define AGP_PLL_CNTL                    0x000b
440 #define SPLL_CNTL                       0x000c
441 #define SCLK_CNTL                       0x000d
442 #define MPLL_CNTL                       0x000e
443 #define MDLL_CKO                        0x000f
444 #define MDLL_RDCKA                      0x0010
445 #define MCLK_CNTL                       0x0012
446 #define AGP_PLL_CNTL                    0x000b
447 #define PLL_TEST_CNTL                   0x0013
448 #define CLK_PWRMGT_CNTL                 0x0014
449 #define PLL_PWRMGT_CNTL                 0x0015
450 #define MCLK_MISC                       0x001f
451 #define P2PLL_CNTL                      0x002a
452 #define P2PLL_REF_DIV                   0x002b
453 #define PIXCLKS_CNTL                    0x002d
454 #define SCLK_MORE_CNTL                  0x0035
455
456 /* MCLK_CNTL bit constants */
457 #define FORCEON_MCLKA                   (1 << 16)
458 #define FORCEON_MCLKB                   (1 << 17)
459 #define FORCEON_YCLKA                   (1 << 18)
460 #define FORCEON_YCLKB                   (1 << 19)
461 #define FORCEON_MC                      (1 << 20)
462 #define FORCEON_AIC                     (1 << 21)
463
464 /* SCLK_CNTL bit constants */
465 #define DYN_STOP_LAT_MASK               0x00007ff8
466 #define CP_MAX_DYN_STOP_LAT             0x0008
467 #define SCLK_FORCEON_MASK               0xffff8000
468
469 /* SCLK_MORE_CNTL bit constants */
470 #define SCLK_MORE_FORCEON               0x0700
471
472 /* BUS_CNTL bit constants */
473 #define BUS_DBL_RESYNC                  0x00000001
474 #define BUS_MSTR_RESET                  0x00000002
475 #define BUS_FLUSH_BUF                   0x00000004
476 #define BUS_STOP_REQ_DIS                0x00000008
477 #define BUS_ROTATION_DIS                0x00000010
478 #define BUS_MASTER_DIS                  0x00000040
479 #define BUS_ROM_WRT_EN                  0x00000080
480 #define BUS_DIS_ROM                     0x00001000
481 #define BUS_PCI_READ_RETRY_EN           0x00002000
482 #define BUS_AGP_AD_STEPPING_EN          0x00004000
483 #define BUS_PCI_WRT_RETRY_EN            0x00008000
484 #define BUS_MSTR_RD_MULT                0x00100000
485 #define BUS_MSTR_RD_LINE                0x00200000
486 #define BUS_SUSPEND                     0x00400000
487 #define LAT_16X                         0x00800000
488 #define BUS_RD_DISCARD_EN               0x01000000
489 #define BUS_RD_ABORT_EN                 0x02000000
490 #define BUS_MSTR_WS                     0x04000000
491 #define BUS_PARKING_DIS                 0x08000000
492 #define BUS_MSTR_DISCONNECT_EN          0x10000000
493 #define BUS_WRT_BURST                   0x20000000
494 #define BUS_READ_BURST                  0x40000000
495 #define BUS_RDY_READ_DLY                0x80000000
496
497 /* PIXCLKS_CNTL */
498 #define PIX2CLK_SRC_SEL_MASK            0x03
499 #define PIX2CLK_SRC_SEL_CPUCLK          0x00
500 #define PIX2CLK_SRC_SEL_PSCANCLK        0x01
501 #define PIX2CLK_SRC_SEL_BYTECLK         0x02
502 #define PIX2CLK_SRC_SEL_P2PLLCLK        0x03
503 #define PIX2CLK_ALWAYS_ONb              (1<<6)
504 #define PIX2CLK_DAC_ALWAYS_ONb          (1<<7)
505 #define PIXCLK_TV_SRC_SEL               (1 << 8)
506 #define PIXCLK_LVDS_ALWAYS_ONb          (1 << 14)
507 #define PIXCLK_TMDS_ALWAYS_ONb          (1 << 15)
508
509
510 /* CLOCK_CNTL_INDEX bit constants */
511 #define PLL_WR_EN                       0x00000080
512
513 /* CONFIG_CNTL bit constants */
514 #define CFG_VGA_RAM_EN                  0x00000100
515 #define CFG_ATI_REV_ID_MASK             (0xf << 16)
516 #define CFG_ATI_REV_A11                 (0 << 16)
517 #define CFG_ATI_REV_A12                 (1 << 16)
518 #define CFG_ATI_REV_A13                 (2 << 16)
519
520 /* CRTC_EXT_CNTL bit constants */
521 #define VGA_ATI_LINEAR                  0x00000008
522 #define VGA_128KAP_PAGING               0x00000010
523 #define XCRT_CNT_EN                     (1 << 6)
524 #define CRTC_HSYNC_DIS                  (1 << 8)
525 #define CRTC_VSYNC_DIS                  (1 << 9)
526 #define CRTC_DISPLAY_DIS                (1 << 10)
527 #define CRTC_CRT_ON                     (1 << 15)
528
529
530 /* DSTCACHE_CTLSTAT bit constants */
531 #define RB2D_DC_FLUSH                   (3 << 0)
532 #define RB2D_DC_FLUSH_ALL               0xf
533 #define RB2D_DC_BUSY                    (1 << 31)
534
535
536 /* CRTC_GEN_CNTL bit constants */
537 #define CRTC_DBL_SCAN_EN                0x00000001
538 #define CRTC_CUR_EN                     0x00010000
539 #define CRTC_INTERLACE_EN               (1 << 1)
540 #define CRTC_BYPASS_LUT_EN              (1 << 14)
541 #define CRTC_EXT_DISP_EN                (1 << 24)
542 #define CRTC_EN                         (1 << 25)
543 #define CRTC_DISP_REQ_EN_B              (1 << 26)
544
545 /* CRTC_STATUS bit constants */
546 #define CRTC_VBLANK                     0x00000001
547
548 /* CRTC2_GEN_CNTL bit constants */
549 #define CRT2_ON                         (1 << 7)
550 #define CRTC2_DISPLAY_DIS               (1 << 23)
551 #define CRTC2_EN                        (1 << 25)
552 #define CRTC2_DISP_REQ_EN_B             (1 << 26)
553
554 /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
555 #define CUR_LOCK                        0x80000000
556
557 /* GPIO bit constants */
558 #define GPIO_A_0                        (1 <<  0)
559 #define GPIO_A_1                        (1 <<  1)
560 #define GPIO_Y_0                        (1 <<  8)
561 #define GPIO_Y_1                        (1 <<  9)
562 #define GPIO_EN_0                       (1 << 16)
563 #define GPIO_EN_1                       (1 << 17)
564 #define GPIO_MASK_0                     (1 << 24)
565 #define GPIO_MASK_1                     (1 << 25)
566 #define VGA_DDC_DATA_OUTPUT             GPIO_A_0
567 #define VGA_DDC_CLK_OUTPUT              GPIO_A_1
568 #define VGA_DDC_DATA_INPUT              GPIO_Y_0
569 #define VGA_DDC_CLK_INPUT               GPIO_Y_1
570 #define VGA_DDC_DATA_OUT_EN             GPIO_EN_0
571 #define VGA_DDC_CLK_OUT_EN              GPIO_EN_1
572
573
574 /* FP bit constants */
575 #define FP_CRTC_H_TOTAL_MASK            000003ff
576 #define FP_CRTC_H_DISP_MASK             0x01ff0000
577 #define FP_CRTC_V_TOTAL_MASK            0x00000fff
578 #define FP_CRTC_V_DISP_MASK             0x0fff0000
579 #define FP_H_SYNC_STRT_CHAR_MASK        0x00001ff8
580 #define FP_H_SYNC_WID_MASK              0x003f0000
581 #define FP_V_SYNC_STRT_MASK             0x00000fff
582 #define FP_V_SYNC_WID_MASK              0x001f0000
583 #define FP_CRTC_H_TOTAL_SHIFT           0x00000000
584 #define FP_CRTC_H_DISP_SHIFT            0x00000010
585 #define FP_CRTC_V_TOTAL_SHIFT           0x00000000
586 #define FP_CRTC_V_DISP_SHIFT            0x00000010
587 #define FP_H_SYNC_STRT_CHAR_SHIFT       0x00000003
588 #define FP_H_SYNC_WID_SHIFT             0x00000010
589 #define FP_V_SYNC_STRT_SHIFT            0x00000000
590 #define FP_V_SYNC_WID_SHIFT             0x00000010
591
592 /* FP_GEN_CNTL bit constants */
593 #define FP_FPON                         (1 << 0)
594 #define FP_TMDS_EN                      (1 << 2)
595 #define FP_PANEL_FORMAT                 (1 << 3)
596 #define FP_EN_TMDS                      (1 << 7)
597 #define FP_DETECT_SENSE                 (1 << 8)
598 #define R200_FP_SOURCE_SEL_MASK         (3 << 10)
599 #define R200_FP_SOURCE_SEL_CRTC1        (0 << 10)
600 #define R200_FP_SOURCE_SEL_CRTC2        (1 << 10)
601 #define R200_FP_SOURCE_SEL_RMX          (2 << 10)
602 #define R200_FP_SOURCE_SEL_TRANS        (3 << 10)
603 #define FP_SEL_CRTC1                    (0 << 13)
604 #define FP_SEL_CRTC2                    (1 << 13)
605 #define FP_USE_VGA_HSYNC                (1 << 14)
606 #define FP_CRTC_DONT_SHADOW_HPAR        (1 << 15)
607 #define FP_CRTC_DONT_SHADOW_VPAR        (1 << 16)
608 #define FP_CRTC_DONT_SHADOW_HEND        (1 << 17)
609 #define FP_CRTC_USE_SHADOW_VEND         (1 << 18)
610 #define FP_RMX_HVSYNC_CONTROL_EN        (1 << 20)
611 #define FP_DFP_SYNC_SEL                 (1 << 21)
612 #define FP_CRTC_LOCK_8DOT               (1 << 22)
613 #define FP_CRT_SYNC_SEL                 (1 << 23)
614 #define FP_USE_SHADOW_EN                (1 << 24)
615 #define FP_CRT_SYNC_ALT                 (1 << 26)
616
617 /* FP2_GEN_CNTL bit constants */
618 #define FP2_BLANK_EN                    (1 <<   1)
619 #define FP2_ON                          (1 <<   2)
620 #define FP2_PANEL_FORMAT                (1 <<   3)
621 #define FP2_SOURCE_SEL_MASK             (3 << 10)
622 #define FP2_SOURCE_SEL_CRTC2            (1 << 10)
623 #define FP2_SRC_SEL_MASK                (3 << 13)
624 #define FP2_SRC_SEL_CRTC2               (1 << 13)
625 #define FP2_FP_POL                      (1 << 16)
626 #define FP2_LP_POL                      (1 << 17)
627 #define FP2_SCK_POL                     (1 << 18)
628 #define FP2_LCD_CNTL_MASK               (7 << 19)
629 #define FP2_PAD_FLOP_EN                 (1 << 22)
630 #define FP2_CRC_EN                      (1 << 23)
631 #define FP2_CRC_READ_EN                 (1 << 24)
632 #define FP2_DV0_EN                      (1 << 25)
633 #define FP2_DV0_RATE_SEL_SDR            (1 << 26)
634
635
636 /* LVDS_GEN_CNTL bit constants */
637 #define LVDS_ON                         (1 << 0)
638 #define LVDS_DISPLAY_DIS                (1 << 1)
639 #define LVDS_PANEL_TYPE                 (1 << 2)
640 #define LVDS_PANEL_FORMAT               (1 << 3)
641 #define LVDS_EN                         (1 << 7)
642 #define LVDS_BL_MOD_LEVEL_MASK          0x0000ff00
643 #define LVDS_BL_MOD_LEVEL_SHIFT         8
644 #define LVDS_BL_MOD_EN                  (1 << 16)
645 #define LVDS_DIGON                      (1 << 18)
646 #define LVDS_BLON                       (1 << 19)
647 #define LVDS_SEL_CRTC2                  (1 << 23)
648 #define LVDS_STATE_MASK \
649         (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
650
651 /* LVDS_PLL_CNTL bit constatns */
652 #define HSYNC_DELAY_SHIFT               0x1c
653 #define HSYNC_DELAY_MASK                (0xf << 0x1c)
654
655 /* TMDS_TRANSMITTER_CNTL bit constants */
656 #define TMDS_PLL_EN                     (1 << 0)
657 #define TMDS_PLLRST                     (1 << 1)
658 #define TMDS_RAN_PAT_RST                (1 << 7)
659 #define TMDS_ICHCSEL                    (1 << 28)
660
661 /* FP_HORZ_STRETCH bit constants */
662 #define HORZ_STRETCH_RATIO_MASK         0xffff
663 #define HORZ_STRETCH_RATIO_MAX          4096
664 #define HORZ_PANEL_SIZE                 (0x1ff << 16)
665 #define HORZ_PANEL_SHIFT                16
666 #define HORZ_STRETCH_PIXREP             (0 << 25)
667 #define HORZ_STRETCH_BLEND              (1 << 26)
668 #define HORZ_STRETCH_ENABLE             (1 << 25)
669 #define HORZ_AUTO_RATIO                 (1 << 27)
670 #define HORZ_FP_LOOP_STRETCH            (0x7 << 28)
671 #define HORZ_AUTO_RATIO_INC             (1 << 31)
672
673
674 /* FP_VERT_STRETCH bit constants */
675 #define VERT_STRETCH_RATIO_MASK         0xfff
676 #define VERT_STRETCH_RATIO_MAX          4096
677 #define VERT_PANEL_SIZE                 (0xfff << 12)
678 #define VERT_PANEL_SHIFT                12
679 #define VERT_STRETCH_LINREP             (0 << 26)
680 #define VERT_STRETCH_BLEND              (1 << 26)
681 #define VERT_STRETCH_ENABLE             (1 << 25)
682 #define VERT_AUTO_RATIO_EN              (1 << 27)
683 #define VERT_FP_LOOP_STRETCH            (0x7 << 28)
684 #define VERT_STRETCH_RESERVED           0xf1000000
685
686 /* DAC_CNTL bit constants */
687 #define DAC_8BIT_EN                     0x00000100
688 #define DAC_4BPP_PIX_ORDER              0x00000200
689 #define DAC_CRC_EN                      0x00080000
690 #define DAC_MASK_ALL                    (0xff << 24)
691 #define DAC_PDWN                        (1 << 15)
692 #define DAC_EXPAND_MODE                 (1 << 14)
693 #define DAC_VGA_ADR_EN                  (1 << 13)
694 #define DAC_RANGE_CNTL                  (3 <<  0)
695 #define DAC_RANGE_CNTL_MASK             0x03
696 #define DAC_BLANKING                    (1 <<  2)
697 #define DAC_CMP_EN                      (1 <<  3)
698 #define DAC_CMP_OUTPUT                  (1 <<  7)
699
700 /* DAC_CNTL2 bit constants */
701 #define DAC2_EXPAND_MODE                (1 << 14)
702 #define DAC2_CMP_EN                     (1 << 7)
703 #define DAC2_PALETTE_ACCESS_CNTL        (1 << 5)
704
705 /* DAC_EXT_CNTL bit constants */
706 #define DAC_FORCE_BLANK_OFF_EN          (1 << 4)
707 #define DAC_FORCE_DATA_EN               (1 << 5)
708 #define DAC_FORCE_DATA_SEL_MASK         (3 << 6)
709 #define DAC_FORCE_DATA_MASK             0x0003ff00
710 #define DAC_FORCE_DATA_SHIFT            8
711
712 /* GEN_RESET_CNTL bit constants */
713 #define SOFT_RESET_GUI                  0x00000001
714 #define SOFT_RESET_VCLK                 0x00000100
715 #define SOFT_RESET_PCLK                 0x00000200
716 #define SOFT_RESET_ECP                  0x00000400
717 #define SOFT_RESET_DISPENG_XCLK         0x00000800
718
719 /* MEM_CNTL bit constants */
720 #define MEM_CTLR_STATUS_IDLE            0x00000000
721 #define MEM_CTLR_STATUS_BUSY            0x00100000
722 #define MEM_SEQNCR_STATUS_IDLE          0x00000000
723 #define MEM_SEQNCR_STATUS_BUSY          0x00200000
724 #define MEM_ARBITER_STATUS_IDLE         0x00000000
725 #define MEM_ARBITER_STATUS_BUSY         0x00400000
726 #define MEM_REQ_UNLOCK                  0x00000000
727 #define MEM_REQ_LOCK                    0x00800000
728 #define MEM_NUM_CHANNELS_MASK           0x00000001
729 #define MEM_USE_B_CH_ONLY               0x00000002
730 #define RV100_MEM_HALF_MODE             0x00000008
731 #define R300_MEM_NUM_CHANNELS_MASK      0x00000003
732 #define R300_MEM_USE_CD_CH_ONLY         0x00000004
733
734
735 /* RBBM_SOFT_RESET bit constants */
736 #define SOFT_RESET_CP                   (1 <<  0)
737 #define SOFT_RESET_HI                   (1 <<  1)
738 #define SOFT_RESET_SE                   (1 <<  2)
739 #define SOFT_RESET_RE                   (1 <<  3)
740 #define SOFT_RESET_PP                   (1 <<  4)
741 #define SOFT_RESET_E2                   (1 <<  5)
742 #define SOFT_RESET_RB                   (1 <<  6)
743 #define SOFT_RESET_HDP                  (1 <<  7)
744
745 /* SURFACE_CNTL bit consants */
746 #define SURF_TRANSLATION_DIS            (1 << 8)
747 #define NONSURF_AP0_SWP_16BPP           (1 << 20)
748 #define NONSURF_AP0_SWP_32BPP           (1 << 21)
749 #define NONSURF_AP1_SWP_16BPP           (1 << 22)
750 #define NONSURF_AP1_SWP_32BPP           (1 << 23)
751
752 /* DEFAULT_SC_BOTTOM_RIGHT bit constants */
753 #define DEFAULT_SC_RIGHT_MAX            (0x1fff << 0)
754 #define DEFAULT_SC_BOTTOM_MAX           (0x1fff << 16)
755
756 /* MM_INDEX bit constants */
757 #define MM_APER                         0x80000000
758
759 /* CLR_CMP_CNTL bit constants */
760 #define COMPARE_SRC_FALSE               0x00000000
761 #define COMPARE_SRC_TRUE                0x00000001
762 #define COMPARE_SRC_NOT_EQUAL           0x00000004
763 #define COMPARE_SRC_EQUAL               0x00000005
764 #define COMPARE_SRC_EQUAL_FLIP          0x00000007
765 #define COMPARE_DST_FALSE               0x00000000
766 #define COMPARE_DST_TRUE                0x00000100
767 #define COMPARE_DST_NOT_EQUAL           0x00000400
768 #define COMPARE_DST_EQUAL               0x00000500
769 #define COMPARE_DESTINATION             0x00000000
770 #define COMPARE_SOURCE                  0x01000000
771 #define COMPARE_SRC_AND_DST             0x02000000
772
773
774 /* DP_CNTL bit constants */
775 #define DST_X_RIGHT_TO_LEFT             0x00000000
776 #define DST_X_LEFT_TO_RIGHT             0x00000001
777 #define DST_Y_BOTTOM_TO_TOP             0x00000000
778 #define DST_Y_TOP_TO_BOTTOM             0x00000002
779 #define DST_X_MAJOR                     0x00000000
780 #define DST_Y_MAJOR                     0x00000004
781 #define DST_X_TILE                      0x00000008
782 #define DST_Y_TILE                      0x00000010
783 #define DST_LAST_PEL                    0x00000020
784 #define DST_TRAIL_X_RIGHT_TO_LEFT       0x00000000
785 #define DST_TRAIL_X_LEFT_TO_RIGHT       0x00000040
786 #define DST_TRAP_FILL_RIGHT_TO_LEFT     0x00000000
787 #define DST_TRAP_FILL_LEFT_TO_RIGHT     0x00000080
788 #define DST_BRES_SIGN                   0x00000100
789 #define DST_HOST_BIG_ENDIAN_EN          0x00000200
790 #define DST_POLYLINE_NONLAST            0x00008000
791 #define DST_RASTER_STALL                0x00010000
792 #define DST_POLY_EDGE                   0x00040000
793
794
795 /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
796 #define DST_X_MAJOR_S                   0x00000000
797 #define DST_Y_MAJOR_S                   0x00000001
798 #define DST_Y_BOTTOM_TO_TOP_S           0x00000000
799 #define DST_Y_TOP_TO_BOTTOM_S           0x00008000
800 #define DST_X_RIGHT_TO_LEFT_S           0x00000000
801 #define DST_X_LEFT_TO_RIGHT_S           0x80000000
802
803
804 /* DP_DATATYPE bit constants */
805 #define DST_8BPP                        0x00000002
806 #define DST_15BPP                       0x00000003
807 #define DST_16BPP                       0x00000004
808 #define DST_24BPP                       0x00000005
809 #define DST_32BPP                       0x00000006
810 #define DST_8BPP_RGB332                 0x00000007
811 #define DST_8BPP_Y8                     0x00000008
812 #define DST_8BPP_RGB8                   0x00000009
813 #define DST_16BPP_VYUY422               0x0000000b
814 #define DST_16BPP_YVYU422               0x0000000c
815 #define DST_32BPP_AYUV444               0x0000000e
816 #define DST_16BPP_ARGB4444              0x0000000f
817 #define BRUSH_SOLIDCOLOR                0x00000d00
818 #define SRC_MONO                        0x00000000
819 #define SRC_MONO_LBKGD                  0x00010000
820 #define SRC_DSTCOLOR                    0x00030000
821 #define BYTE_ORDER_MSB_TO_LSB           0x00000000
822 #define BYTE_ORDER_LSB_TO_MSB           0x40000000
823 #define DP_CONVERSION_TEMP              0x80000000
824 #define HOST_BIG_ENDIAN_EN              (1 << 29)
825
826
827 /* DP_GUI_MASTER_CNTL bit constants */
828 #define GMC_SRC_PITCH_OFFSET_DEFAULT    0x00000000
829 #define GMC_SRC_PITCH_OFFSET_LEAVE      0x00000001
830 #define GMC_DST_PITCH_OFFSET_DEFAULT    0x00000000
831 #define GMC_DST_PITCH_OFFSET_LEAVE      0x00000002
832 #define GMC_SRC_CLIP_DEFAULT            0x00000000
833 #define GMC_SRC_CLIP_LEAVE              0x00000004
834 #define GMC_DST_CLIP_DEFAULT            0x00000000
835 #define GMC_DST_CLIP_LEAVE              0x00000008
836 #define GMC_BRUSH_8x8MONO               0x00000000
837 #define GMC_BRUSH_8x8MONO_LBKGD         0x00000010
838 #define GMC_BRUSH_8x1MONO               0x00000020
839 #define GMC_BRUSH_8x1MONO_LBKGD         0x00000030
840 #define GMC_BRUSH_1x8MONO               0x00000040
841 #define GMC_BRUSH_1x8MONO_LBKGD         0x00000050
842 #define GMC_BRUSH_32x1MONO              0x00000060
843 #define GMC_BRUSH_32x1MONO_LBKGD        0x00000070
844 #define GMC_BRUSH_32x32MONO             0x00000080
845 #define GMC_BRUSH_32x32MONO_LBKGD       0x00000090
846 #define GMC_BRUSH_8x8COLOR              0x000000a0
847 #define GMC_BRUSH_8x1COLOR              0x000000b0
848 #define GMC_BRUSH_1x8COLOR              0x000000c0
849 #define GMC_BRUSH_SOLID_COLOR           0x000000d0
850 #define GMC_DST_8BPP                    0x00000200
851 #define GMC_DST_15BPP                   0x00000300
852 #define GMC_DST_16BPP                   0x00000400
853 #define GMC_DST_24BPP                   0x00000500
854 #define GMC_DST_32BPP                   0x00000600
855 #define GMC_DST_8BPP_RGB332             0x00000700
856 #define GMC_DST_8BPP_Y8                 0x00000800
857 #define GMC_DST_8BPP_RGB8               0x00000900
858 #define GMC_DST_16BPP_VYUY422           0x00000b00
859 #define GMC_DST_16BPP_YVYU422           0x00000c00
860 #define GMC_DST_32BPP_AYUV444           0x00000e00
861 #define GMC_DST_16BPP_ARGB4444          0x00000f00
862 #define GMC_SRC_MONO                    0x00000000
863 #define GMC_SRC_MONO_LBKGD              0x00001000
864 #define GMC_SRC_DSTCOLOR                0x00003000
865 #define GMC_BYTE_ORDER_MSB_TO_LSB       0x00000000
866 #define GMC_BYTE_ORDER_LSB_TO_MSB       0x00004000
867 #define GMC_DP_CONVERSION_TEMP_9300     0x00008000
868 #define GMC_DP_CONVERSION_TEMP_6500     0x00000000
869 #define GMC_DP_SRC_RECT                 0x02000000
870 #define GMC_DP_SRC_HOST                 0x03000000
871 #define GMC_DP_SRC_HOST_BYTEALIGN       0x04000000
872 #define GMC_3D_FCN_EN_CLR               0x00000000
873 #define GMC_3D_FCN_EN_SET               0x08000000
874 #define GMC_DST_CLR_CMP_FCN_LEAVE       0x00000000
875 #define GMC_DST_CLR_CMP_FCN_CLEAR       0x10000000
876 #define GMC_AUX_CLIP_LEAVE              0x00000000
877 #define GMC_AUX_CLIP_CLEAR              0x20000000
878 #define GMC_WRITE_MASK_LEAVE            0x00000000
879 #define GMC_WRITE_MASK_SET              0x40000000
880 #define GMC_CLR_CMP_CNTL_DIS            (1 << 28)
881 #define GMC_SRC_DATATYPE_COLOR          (3 << 12)
882 #define ROP3_S                          0x00cc0000
883 #define ROP3_SRCCOPY                    0x00cc0000
884 #define ROP3_P                          0x00f00000
885 #define ROP3_PATCOPY                    0x00f00000
886 #define DP_SRC_SOURCE_MASK              (7  << 24)
887 #define GMC_BRUSH_NONE                  (15 <<  4)
888 #define DP_SRC_SOURCE_MEMORY            (2  << 24)
889 #define GMC_BRUSH_SOLIDCOLOR            0x000000d0
890
891 /* DP_MIX bit constants */
892 #define DP_SRC_RECT                     0x00000200
893 #define DP_SRC_HOST                     0x00000300
894 #define DP_SRC_HOST_BYTEALIGN           0x00000400
895
896 /* MPLL_CNTL bit constants */
897 #define MPLL_RESET                      0x00000001
898
899 /* MDLL_CKO bit constants */
900 #define MCKOA_SLEEP                     0x00000001
901 #define MCKOA_RESET                     0x00000002
902 #define MCKOA_REF_SKEW_MASK             0x00000700
903 #define MCKOA_FB_SKEW_MASK              0x00007000
904
905 /* MDLL_RDCKA bit constants */
906 #define MRDCKA0_SLEEP                   0x00000001
907 #define MRDCKA0_RESET                   0x00000002
908 #define MRDCKA1_SLEEP                   0x00010000
909 #define MRDCKA1_RESET                   0x00020000
910
911 /* VCLK_ECP_CNTL constants */
912 #define VCLK_SRC_SEL_MASK               0x03
913 #define VCLK_SRC_SEL_CPUCLK             0x00
914 #define VCLK_SRC_SEL_PSCANCLK           0x01
915 #define VCLK_SRC_SEL_BYTECLK            0x02
916 #define VCLK_SRC_SEL_PPLLCLK            0x03
917 #define PIXCLK_ALWAYS_ONb               0x00000040
918 #define PIXCLK_DAC_ALWAYS_ONb           0x00000080
919
920 /* BUS_CNTL1 constants */
921 #define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK      0x0c000000
922 #define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT     26
923 #define BUS_CNTL1_AGPCLK_VALID                  0x80000000
924
925 /* PLL_PWRMGT_CNTL constants */
926 #define PLL_PWRMGT_CNTL_SPLL_TURNOFF            0x00000002
927 #define PLL_PWRMGT_CNTL_PPLL_TURNOFF            0x00000004
928 #define PLL_PWRMGT_CNTL_P2PLL_TURNOFF           0x00000008
929 #define PLL_PWRMGT_CNTL_TVPLL_TURNOFF           0x00000010
930 #define PLL_PWRMGT_CNTL_MOBILE_SU               0x00010000
931 #define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK        0x00020000
932 #define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK        0x00040000
933
934 /* TV_DAC_CNTL constants */
935 #define TV_DAC_CNTL_BGSLEEP                     0x00000040
936 #define TV_DAC_CNTL_DETECT                      0x00000010
937 #define TV_DAC_CNTL_BGADJ_MASK                  0x000f0000
938 #define TV_DAC_CNTL_DACADJ_MASK                 0x00f00000
939 #define TV_DAC_CNTL_BGADJ__SHIFT                16
940 #define TV_DAC_CNTL_DACADJ__SHIFT               20
941 #define TV_DAC_CNTL_RDACPD                      0x01000000
942 #define TV_DAC_CNTL_GDACPD                      0x02000000
943 #define TV_DAC_CNTL_BDACPD                      0x04000000
944
945 /* DISP_MISC_CNTL constants */
946 #define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP       (1 << 0)
947 #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP     (1 << 1)
948 #define DISP_MISC_CNTL_SOFT_RESET_OV0_PP        (1 << 2)
949 #define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK     (1 << 4)
950 #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK   (1 << 5)
951 #define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK      (1 << 6)
952 #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP      (1 << 12)
953 #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK    (1 << 15)
954 #define DISP_MISC_CNTL_SOFT_RESET_LVDS          (1 << 16)
955 #define DISP_MISC_CNTL_SOFT_RESET_TMDS          (1 << 17)
956 #define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS      (1 << 18)
957 #define DISP_MISC_CNTL_SOFT_RESET_TV            (1 << 19)
958
959 /* DISP_PWR_MAN constants */
960 #define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN    (1 << 0)
961 #define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN  (1 << 4)
962 #define DISP_PWR_MAN_DISP_D3_RST                (1 << 16)
963 #define DISP_PWR_MAN_DISP_D3_REG_RST            (1 << 17)
964 #define DISP_PWR_MAN_DISP_D3_GRPH_RST           (1 << 18)
965 #define DISP_PWR_MAN_DISP_D3_SUBPIC_RST         (1 << 19)
966 #define DISP_PWR_MAN_DISP_D3_OV0_RST            (1 << 20)
967 #define DISP_PWR_MAN_DISP_D1D2_GRPH_RST         (1 << 21)
968 #define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST       (1 << 22)
969 #define DISP_PWR_MAN_DISP_D1D2_OV0_RST          (1 << 23)
970 #define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST        (1 << 24)
971 #define DISP_PWR_MAN_TV_ENABLE_RST              (1 << 25)
972 #define DISP_PWR_MAN_AUTO_PWRUP_EN              (1 << 26)
973
974 /* masks */
975
976 #define CONFIG_MEMSIZE_MASK             0x1f000000
977 #define MEM_CFG_TYPE                    0x40000000
978 #define DST_OFFSET_MASK                 0x003fffff
979 #define DST_PITCH_MASK                  0x3fc00000
980 #define DEFAULT_TILE_MASK               0xc0000000
981 #define PPLL_DIV_SEL_MASK               0x00000300
982 #define PPLL_RESET                      0x00000001
983 #define PPLL_SLEEP                      0x00000002
984 #define PPLL_ATOMIC_UPDATE_EN           0x00010000
985 #define PPLL_REF_DIV_MASK               0x000003ff
986 #define PPLL_FB3_DIV_MASK               0x000007ff
987 #define PPLL_POST3_DIV_MASK             0x00070000
988 #define PPLL_ATOMIC_UPDATE_R            0x00008000
989 #define PPLL_ATOMIC_UPDATE_W            0x00008000
990 #define PPLL_VGA_ATOMIC_UPDATE_EN       0x00020000
991 #define R300_PPLL_REF_DIV_ACC_MASK      (0x3ff << 18)
992 #define R300_PPLL_REF_DIV_ACC_SHIFT     18
993
994 #define GUI_ACTIVE                      0x80000000
995
996
997 #define MC_IND_INDEX                    0x01F8
998 #define MC_IND_DATA                     0x01FC
999
1000 /* PAD_CTLR_STRENGTH */
1001 #define PAD_MANUAL_OVERRIDE             0x80000000
1002
1003 /* pllCLK_PIN_CNTL */
1004 #define CLK_PIN_CNTL__OSC_EN_MASK                       0x00000001L
1005 #define CLK_PIN_CNTL__OSC_EN                            0x00000001L
1006 #define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK                 0x00000004L
1007 #define CLK_PIN_CNTL__XTL_LOW_GAIN                      0x00000004L
1008 #define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK              0x00000010L
1009 #define CLK_PIN_CNTL__DONT_USE_XTALIN                   0x00000010L
1010 #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK            0x00000020L
1011 #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE                 0x00000020L
1012 #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK             0x00000800L
1013 #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN                  0x00000800L
1014 #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK        0x00001000L
1015 #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN             0x00001000L
1016 #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK       0x00002000L
1017 #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND            0x00002000L
1018 #define CLK_PIN_CNTL__CG_SPARE_MASK                     0x00004000L
1019 #define CLK_PIN_CNTL__CG_SPARE                          0x00004000L
1020 #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK          0x00008000L
1021 #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL               0x00008000L
1022 #define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK               0x00010000L
1023 #define CLK_PIN_CNTL__CP_CLK_RUNNING                    0x00010000L
1024 #define CLK_PIN_CNTL__CG_SPARE_RD_MASK                  0x00060000L
1025 #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK            0x00080000L
1026 #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb                 0x00080000L
1027 #define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK                 0xff000000L
1028
1029 /* pllCLK_PWRMGT_CNTL */
1030 #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT         0x00000000
1031 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT         0x00000001
1032 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT         0x00000002
1033 #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT        0x00000003
1034 #define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT            0x00000004
1035 #define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT            0x00000005
1036 #define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT            0x00000006
1037 #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT           0x00000007
1038 #define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT              0x00000008
1039 #define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT               0x00000009
1040 #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT          0x0000000a
1041 #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT      0x0000000c
1042 #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT         0x0000000d
1043 #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT       0x0000000f
1044 #define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT                 0x00000010
1045 #define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT             0x00000011
1046 #define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT               0x00000012
1047 #define CLK_PWRMGT_CNTL__DLL_READY__SHIFT               0x00000013
1048 #define CLK_PWRMGT_CNTL__DISP_PM__SHIFT                 0x00000014
1049 #define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT           0x00000015
1050 #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT            0x00000018
1051 #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT        0x0000001e
1052 #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT           0x0000001f
1053
1054 /* pllP2PLL_CNTL */
1055 #define P2PLL_CNTL__P2PLL_RESET_MASK                    0x00000001L
1056 #define P2PLL_CNTL__P2PLL_RESET                         0x00000001L
1057 #define P2PLL_CNTL__P2PLL_SLEEP_MASK                    0x00000002L
1058 #define P2PLL_CNTL__P2PLL_SLEEP                         0x00000002L
1059 #define P2PLL_CNTL__P2PLL_TST_EN_MASK                   0x00000004L
1060 #define P2PLL_CNTL__P2PLL_TST_EN                        0x00000004L
1061 #define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK               0x00000010L
1062 #define P2PLL_CNTL__P2PLL_REFCLK_SEL                    0x00000010L
1063 #define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK                0x00000020L
1064 #define P2PLL_CNTL__P2PLL_FBCLK_SEL                     0x00000020L
1065 #define P2PLL_CNTL__P2PLL_TCPOFF_MASK                   0x00000040L
1066 #define P2PLL_CNTL__P2PLL_TCPOFF                        0x00000040L
1067 #define P2PLL_CNTL__P2PLL_TVCOMAX_MASK                  0x00000080L
1068 #define P2PLL_CNTL__P2PLL_TVCOMAX                       0x00000080L
1069 #define P2PLL_CNTL__P2PLL_PCP_MASK                      0x00000700L
1070 #define P2PLL_CNTL__P2PLL_PVG_MASK                      0x00003800L
1071 #define P2PLL_CNTL__P2PLL_PDC_MASK                      0x0000c000L
1072 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK         0x00010000L
1073 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN              0x00010000L
1074 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK       0x00040000L
1075 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC            0x00040000L
1076 #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK       0x00080000L
1077 #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET            0x00080000L
1078
1079 /* pllPIXCLKS_CNTL */
1080 #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT            0x00000000
1081 #define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT             0x00000004
1082 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT         0x00000005
1083 #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT         0x00000006
1084 #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT     0x00000007
1085 #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT          0x00000008
1086 #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT    0x0000000b
1087 #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT       0x0000000c
1088 #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d
1089 #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT     0x0000000e
1090 #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT     0x0000000f
1091
1092
1093 /* pllPIXCLKS_CNTL */
1094 #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK              0x00000003L
1095 #define PIXCLKS_CNTL__PIX2CLK_INVERT                    0x00000010L
1096 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT                0x00000020L
1097 #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb                0x00000040L
1098 #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb            0x00000080L
1099 #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL                 0x00000100L
1100 #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb           0x00000800L
1101 #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb              0x00001000L
1102 #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb        0x00002000L
1103 #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb            0x00004000L
1104 #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb            0x00008000L
1105 #define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb   (1 << 9)
1106 #define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb            (1 << 10)
1107 #define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb        (1 << 13)
1108 #define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb      (1 << 16)
1109 #define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb        (1 << 17)
1110 #define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb           (1 << 18)
1111 #define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb       (1 << 19)
1112 #define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
1113
1114
1115 /* pllP2PLL_DIV_0 */
1116 #define P2PLL_DIV_0__P2PLL_FB_DIV_MASK                  0x000007ffL
1117 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK         0x00008000L
1118 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W              0x00008000L
1119 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK         0x00008000L
1120 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R              0x00008000L
1121 #define P2PLL_DIV_0__P2PLL_POST_DIV_MASK                0x00070000L
1122
1123 /* pllSCLK_CNTL */
1124 #define SCLK_CNTL__SCLK_SRC_SEL_MASK                    0x00000007L
1125 #define SCLK_CNTL__CP_MAX_DYN_STOP_LAT                  0x00000008L
1126 #define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT                 0x00000010L
1127 #define SCLK_CNTL__TV_MAX_DYN_STOP_LAT                  0x00000020L
1128 #define SCLK_CNTL__E2_MAX_DYN_STOP_LAT                  0x00000040L
1129 #define SCLK_CNTL__SE_MAX_DYN_STOP_LAT                  0x00000080L
1130 #define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT                0x00000100L
1131 #define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT                 0x00000200L
1132 #define SCLK_CNTL__RE_MAX_DYN_STOP_LAT                  0x00000400L
1133 #define SCLK_CNTL__PB_MAX_DYN_STOP_LAT                  0x00000800L
1134 #define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT                 0x00001000L
1135 #define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT                 0x00002000L
1136 #define SCLK_CNTL__RB_MAX_DYN_STOP_LAT                  0x00004000L
1137 #define SCLK_CNTL__DYN_STOP_LAT_MASK                    0x00007ff8
1138 #define SCLK_CNTL__FORCE_DISP2                          0x00008000L
1139 #define SCLK_CNTL__FORCE_CP                             0x00010000L
1140 #define SCLK_CNTL__FORCE_HDP                            0x00020000L
1141 #define SCLK_CNTL__FORCE_DISP1                          0x00040000L
1142 #define SCLK_CNTL__FORCE_TOP                            0x00080000L
1143 #define SCLK_CNTL__FORCE_E2                             0x00100000L
1144 #define SCLK_CNTL__FORCE_SE                             0x00200000L
1145 #define SCLK_CNTL__FORCE_IDCT                           0x00400000L
1146 #define SCLK_CNTL__FORCE_VIP                            0x00800000L
1147 #define SCLK_CNTL__FORCE_RE                             0x01000000L
1148 #define SCLK_CNTL__FORCE_PB                             0x02000000L
1149 #define SCLK_CNTL__FORCE_TAM                            0x04000000L
1150 #define SCLK_CNTL__FORCE_TDM                            0x08000000L
1151 #define SCLK_CNTL__FORCE_RB                             0x10000000L
1152 #define SCLK_CNTL__FORCE_TV_SCLK                        0x20000000L
1153 #define SCLK_CNTL__FORCE_SUBPIC                         0x40000000L
1154 #define SCLK_CNTL__FORCE_OV0                            0x80000000L
1155 #define SCLK_CNTL__R300_FORCE_VAP                       (1<<21)
1156 #define SCLK_CNTL__R300_FORCE_SR                        (1<<25)
1157 #define SCLK_CNTL__R300_FORCE_PX                        (1<<26)
1158 #define SCLK_CNTL__R300_FORCE_TX                        (1<<27)
1159 #define SCLK_CNTL__R300_FORCE_US                        (1<<28)
1160 #define SCLK_CNTL__R300_FORCE_SU                        (1<<30)
1161 #define SCLK_CNTL__FORCEON_MASK                         0xffff8000L
1162
1163 /* pllSCLK_CNTL2 */
1164 #define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT           (1<<10)
1165 #define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT            (1<<11)
1166 #define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT           (1<<12)
1167 #define SCLK_CNTL2__R300_FORCE_TCL                      (1<<13)
1168 #define SCLK_CNTL2__R300_FORCE_CBA                      (1<<14)
1169 #define SCLK_CNTL2__R300_FORCE_GA                       (1<<15)
1170
1171 /* SCLK_MORE_CNTL */
1172 #define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT       0x00000001L
1173 #define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT         0x00000002L
1174 #define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT        0x00000004L
1175 #define SCLK_MORE_CNTL__FORCE_DISPREGS                  0x00000100L
1176 #define SCLK_MORE_CNTL__FORCE_MC_GUI                    0x00000200L
1177 #define SCLK_MORE_CNTL__FORCE_MC_HOST                   0x00000400L
1178 #define SCLK_MORE_CNTL__STOP_SCLK_EN                    0x00001000L
1179 #define SCLK_MORE_CNTL__STOP_SCLK_A                     0x00002000L
1180 #define SCLK_MORE_CNTL__STOP_SCLK_B                     0x00004000L
1181 #define SCLK_MORE_CNTL__STOP_SCLK_C                     0x00008000L
1182 #define SCLK_MORE_CNTL__HALF_SPEED_SCLK                 0x00010000L
1183 #define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP              0x00020000L
1184 #define SCLK_MORE_CNTL__TVFB_SOFT_RESET                 0x00040000L
1185 #define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC               0x00080000L
1186 #define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK            0x00400000L
1187 #define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK              0x00800000L
1188 #define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK              0xff000000L
1189 #define SCLK_MORE_CNTL__FORCEON                         0x00000700L
1190
1191 /* MCLK_CNTL */
1192 #define MCLK_CNTL__MCLKA_SRC_SEL_MASK                   0x00000007L
1193 #define MCLK_CNTL__YCLKA_SRC_SEL_MASK                   0x00000070L
1194 #define MCLK_CNTL__MCLKB_SRC_SEL_MASK                   0x00000700L
1195 #define MCLK_CNTL__YCLKB_SRC_SEL_MASK                   0x00007000L
1196 #define MCLK_CNTL__FORCE_MCLKA_MASK                     0x00010000L
1197 #define MCLK_CNTL__FORCE_MCLKA                          0x00010000L
1198 #define MCLK_CNTL__FORCE_MCLKB_MASK                     0x00020000L
1199 #define MCLK_CNTL__FORCE_MCLKB                          0x00020000L
1200 #define MCLK_CNTL__FORCE_YCLKA_MASK                     0x00040000L
1201 #define MCLK_CNTL__FORCE_YCLKA                          0x00040000L
1202 #define MCLK_CNTL__FORCE_YCLKB_MASK                     0x00080000L
1203 #define MCLK_CNTL__FORCE_YCLKB                          0x00080000L
1204 #define MCLK_CNTL__FORCE_MC_MASK                        0x00100000L
1205 #define MCLK_CNTL__FORCE_MC                             0x00100000L
1206 #define MCLK_CNTL__FORCE_AIC_MASK                       0x00200000L
1207 #define MCLK_CNTL__FORCE_AIC                            0x00200000L
1208 #define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK                 0x03000000L
1209 #define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK                 0x0c000000L
1210 #define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK                 0x30000000L
1211 #define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK                 0xc0000000L
1212 #define MCLK_CNTL__R300_DISABLE_MC_MCLKA                (1 << 21)
1213 #define MCLK_CNTL__R300_DISABLE_MC_MCLKB                (1 << 21)
1214
1215 /* MCLK_MISC */
1216 #define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK      0x00000003L
1217 #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK          0x00000004L
1218 #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL               0x00000004L
1219 #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK           0x00000008L
1220 #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL                0x00000008L
1221 #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK      0x00000010L
1222 #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN           0x00000010L
1223 #define MCLK_MISC__DLL_READY_LAT_MASK                   0x00000100L
1224 #define MCLK_MISC__DLL_READY_LAT                        0x00000100L
1225 #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK        0x00001000L
1226 #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT             0x00001000L
1227 #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK        0x00002000L
1228 #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT             0x00002000L
1229 #define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK              0x00004000L
1230 #define MCLK_MISC__MC_MCLK_DYN_ENABLE                   0x00004000L
1231 #define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK              0x00008000L
1232 #define MCLK_MISC__IO_MCLK_DYN_ENABLE                   0x00008000L
1233 #define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK               0x00010000L
1234 #define MCLK_MISC__CGM_CLK_TO_OUTPIN                    0x00010000L
1235 #define MCLK_MISC__CLK_OR_COUNT_SEL_MASK                0x00020000L
1236 #define MCLK_MISC__CLK_OR_COUNT_SEL                     0x00020000L
1237 #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK     0x00040000L
1238 #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND          0x00040000L
1239 #define MCLK_MISC__CGM_SPARE_RD_MASK                    0x00300000L
1240 #define MCLK_MISC__CGM_SPARE_A_RD_MASK                  0x00c00000L
1241 #define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK                0x01000000L
1242 #define MCLK_MISC__TCLK_TO_YCLKB_EN                     0x01000000L
1243 #define MCLK_MISC__CGM_SPARE_A_MASK                     0x0e000000L
1244
1245 /* VCLK_ECP_CNTL */
1246 #define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK                0x00000003L
1247 #define VCLK_ECP_CNTL__VCLK_INVERT                      0x00000010L
1248 #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT                0x00000020L
1249 #define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb                0x00000040L
1250 #define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb            0x00000080L
1251 #define VCLK_ECP_CNTL__ECP_DIV_MASK                     0x00000300L
1252 #define VCLK_ECP_CNTL__ECP_FORCE_ON                     0x00040000L
1253 #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON                  0x00080000L
1254 #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF  (1<<23)
1255
1256 /* PLL_PWRMGT_CNTL */
1257 #define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK              0x00000001L
1258 #define PLL_PWRMGT_CNTL__MPLL_TURNOFF                   0x00000001L
1259 #define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK              0x00000002L
1260 #define PLL_PWRMGT_CNTL__SPLL_TURNOFF                   0x00000002L
1261 #define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK              0x00000004L
1262 #define PLL_PWRMGT_CNTL__PPLL_TURNOFF                   0x00000004L
1263 #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK             0x00000008L
1264 #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF                  0x00000008L
1265 #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK             0x00000010L
1266 #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF                  0x00000010L
1267 #define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK       0x000001e0L
1268 #define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK           0x00000600L
1269 #define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK           0x00001800L
1270 #define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK               0x00002000L
1271 #define PLL_PWRMGT_CNTL__PM_MODE_SEL                    0x00002000L
1272 #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK       0x00004000L
1273 #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND            0x00004000L
1274 #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK       0x00008000L
1275 #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND            0x00008000L
1276 #define PLL_PWRMGT_CNTL__MOBILE_SU_MASK                 0x00010000L
1277 #define PLL_PWRMGT_CNTL__MOBILE_SU                      0x00010000L
1278 #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK          0x00020000L
1279 #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK               0x00020000L
1280 #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK          0x00040000L
1281 #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK               0x00040000L
1282 #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK        0x00080000L
1283 #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE             0x00080000L
1284 #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK        0x00100000L
1285 #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE             0x00100000L
1286 #define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK        0x00200000L
1287 #define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD            0x00200000L
1288 #define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK              0xff000000L
1289
1290 /* CLK_PWRMGT_CNTL */
1291 #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK           0x00000001L
1292 #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF                0x00000001L
1293 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK           0x00000002L
1294 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF                0x00000002L
1295 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK           0x00000004L
1296 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF                0x00000004L
1297 #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK          0x00000008L
1298 #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF               0x00000008L
1299 #define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK              0x00000010L
1300 #define CLK_PWRMGT_CNTL__MCLK_TURNOFF                   0x00000010L
1301 #define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK              0x00000020L
1302 #define CLK_PWRMGT_CNTL__SCLK_TURNOFF                   0x00000020L
1303 #define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK              0x00000040L
1304 #define CLK_PWRMGT_CNTL__PCLK_TURNOFF                   0x00000040L
1305 #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK             0x00000080L
1306 #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF                  0x00000080L
1307 #define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK                0x00000100L
1308 #define CLK_PWRMGT_CNTL__MC_CH_MODE                     0x00000100L
1309 #define CLK_PWRMGT_CNTL__TEST_MODE_MASK                 0x00000200L
1310 #define CLK_PWRMGT_CNTL__TEST_MODE                      0x00000200L
1311 #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK            0x00000400L
1312 #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN                 0x00000400L
1313 #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK        0x00001000L
1314 #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE             0x00001000L
1315 #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK           0x00006000L
1316 #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK         0x00008000L
1317 #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT              0x00008000L
1318 #define CLK_PWRMGT_CNTL__MC_BUSY_MASK                   0x00010000L
1319 #define CLK_PWRMGT_CNTL__MC_BUSY                        0x00010000L
1320 #define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK               0x00020000L
1321 #define CLK_PWRMGT_CNTL__MC_INT_CNTL                    0x00020000L
1322 #define CLK_PWRMGT_CNTL__MC_SWITCH_MASK                 0x00040000L
1323 #define CLK_PWRMGT_CNTL__MC_SWITCH                      0x00040000L
1324 #define CLK_PWRMGT_CNTL__DLL_READY_MASK                 0x00080000L
1325 #define CLK_PWRMGT_CNTL__DLL_READY                      0x00080000L
1326 #define CLK_PWRMGT_CNTL__DISP_PM_MASK                   0x00100000L
1327 #define CLK_PWRMGT_CNTL__DISP_PM                        0x00100000L
1328 #define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK             0x00e00000L
1329 #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK              0x3f000000L
1330 #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK          0x40000000L
1331 #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF               0x40000000L
1332 #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK             0x80000000L
1333 #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF                  0x80000000L
1334
1335 /* BUS_CNTL1 */
1336 #define BUS_CNTL1__PMI_IO_DISABLE_MASK                  0x00000001L
1337 #define BUS_CNTL1__PMI_IO_DISABLE                       0x00000001L
1338 #define BUS_CNTL1__PMI_MEM_DISABLE_MASK                 0x00000002L
1339 #define BUS_CNTL1__PMI_MEM_DISABLE                      0x00000002L
1340 #define BUS_CNTL1__PMI_BM_DISABLE_MASK                  0x00000004L
1341 #define BUS_CNTL1__PMI_BM_DISABLE                       0x00000004L
1342 #define BUS_CNTL1__PMI_INT_DISABLE_MASK                 0x00000008L
1343 #define BUS_CNTL1__PMI_INT_DISABLE                      0x00000008L
1344 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK      0x00000020L
1345 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE           0x00000020L
1346 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK      0x00000100L
1347 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS           0x00000100L
1348 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK      0x00000200L
1349 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS           0x00000200L
1350 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK      0x00000400L
1351 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS           0x00000400L
1352 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
1353 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS     0x00000800L
1354 #define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK             0x0c000000L
1355 #define BUS_CNTL1__SEND_SBA_LATENCY_MASK                0x70000000L
1356 #define BUS_CNTL1__AGPCLK_VALID_MASK                    0x80000000L
1357 #define BUS_CNTL1__AGPCLK_VALID                         0x80000000L
1358
1359 /* BUS_CNTL1 */
1360 #define BUS_CNTL1__PMI_IO_DISABLE__SHIFT                0x00000000
1361 #define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT               0x00000001
1362 #define BUS_CNTL1__PMI_BM_DISABLE__SHIFT                0x00000002
1363 #define BUS_CNTL1__PMI_INT_DISABLE__SHIFT               0x00000003
1364 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT    0x00000005
1365 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT    0x00000008
1366 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT    0x00000009
1367 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT    0x0000000a
1368 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
1369 #define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT           0x0000001a
1370 #define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT              0x0000001c
1371 #define BUS_CNTL1__AGPCLK_VALID__SHIFT                  0x0000001f
1372
1373 /* CRTC_OFFSET_CNTL */
1374 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK           0x0000000fL
1375 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK     0x000000f0L
1376 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK       0x00004000L
1377 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT            0x00004000L
1378 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK             0x00008000L
1379 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN                  0x00008000L
1380 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK    0x00010000L
1381 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL         0x00010000L
1382 #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK    0x00020000L
1383 #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN         0x00020000L
1384 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK      0x000c0000L
1385 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK  0x00100000L
1386 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN       0x00100000L
1387 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK         0x00200000L
1388 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC              0x00200000L
1389 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
1390 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN  0x10000000L
1391 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
1392 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
1393 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK     0x40000000L
1394 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET          0x40000000L
1395 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK         0x80000000L
1396 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK              0x80000000L
1397
1398 /* CRTC_GEN_CNTL */
1399 #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK            0x00000001L
1400 #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN                 0x00000001L
1401 #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK           0x00000002L
1402 #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN                0x00000002L
1403 #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK              0x00000010L
1404 #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN                   0x00000010L
1405 #define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK              0x00000f00L
1406 #define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK                0x00008000L
1407 #define CRTC_GEN_CNTL__CRTC_ICON_EN                     0x00008000L
1408 #define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK                 0x00010000L
1409 #define CRTC_GEN_CNTL__CRTC_CUR_EN                      0x00010000L
1410 #define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK             0x00060000L
1411 #define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK               0x00700000L
1412 #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK            0x01000000L
1413 #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN                 0x01000000L
1414 #define CRTC_GEN_CNTL__CRTC_EN_MASK                     0x02000000L
1415 #define CRTC_GEN_CNTL__CRTC_EN                          0x02000000L
1416 #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK          0x04000000L
1417 #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B               0x04000000L
1418
1419 /* CRTC2_GEN_CNTL */
1420 #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK          0x00000001L
1421 #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN               0x00000001L
1422 #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK         0x00000002L
1423 #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN              0x00000002L
1424 #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK        0x00000010L
1425 #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE             0x00000010L
1426 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK       0x00000020L
1427 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE            0x00000020L
1428 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK       0x00000040L
1429 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE            0x00000040L
1430 #define CRTC2_GEN_CNTL__CRT2_ON_MASK                    0x00000080L
1431 #define CRTC2_GEN_CNTL__CRT2_ON                         0x00000080L
1432 #define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK            0x00000f00L
1433 #define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK              0x00008000L
1434 #define CRTC2_GEN_CNTL__CRTC2_ICON_EN                   0x00008000L
1435 #define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK               0x00010000L
1436 #define CRTC2_GEN_CNTL__CRTC2_CUR_EN                    0x00010000L
1437 #define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK             0x00700000L
1438 #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK          0x00800000L
1439 #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS               0x00800000L
1440 #define CRTC2_GEN_CNTL__CRTC2_EN_MASK                   0x02000000L
1441 #define CRTC2_GEN_CNTL__CRTC2_EN                        0x02000000L
1442 #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK        0x04000000L
1443 #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B             0x04000000L
1444 #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK            0x08000000L
1445 #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN                 0x08000000L
1446 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK            0x10000000L
1447 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS                 0x10000000L
1448 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK            0x20000000L
1449 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS                 0x20000000L
1450
1451 /* AGP_CNTL */
1452 #define AGP_CNTL__MAX_IDLE_CLK_MASK                     0x000000ffL
1453 #define AGP_CNTL__HOLD_RD_FIFO_MASK                     0x00000100L
1454 #define AGP_CNTL__HOLD_RD_FIFO                          0x00000100L
1455 #define AGP_CNTL__HOLD_RQ_FIFO_MASK                     0x00000200L
1456 #define AGP_CNTL__HOLD_RQ_FIFO                          0x00000200L
1457 #define AGP_CNTL__EN_2X_STBB_MASK                       0x00000400L
1458 #define AGP_CNTL__EN_2X_STBB                            0x00000400L
1459 #define AGP_CNTL__FORCE_FULL_SBA_MASK                   0x00000800L
1460 #define AGP_CNTL__FORCE_FULL_SBA                        0x00000800L
1461 #define AGP_CNTL__SBA_DIS_MASK                          0x00001000L
1462 #define AGP_CNTL__SBA_DIS                               0x00001000L
1463 #define AGP_CNTL__AGP_REV_ID_MASK                       0x00002000L
1464 #define AGP_CNTL__AGP_REV_ID                            0x00002000L
1465 #define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK                0x00004000L
1466 #define AGP_CNTL__REG_CRIPPLE_AGP4X                     0x00004000L
1467 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK              0x00008000L
1468 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X                   0x00008000L
1469 #define AGP_CNTL__FORCE_INT_VREF_MASK                   0x00010000L
1470 #define AGP_CNTL__FORCE_INT_VREF                        0x00010000L
1471 #define AGP_CNTL__PENDING_SLOTS_VAL_MASK                0x00060000L
1472 #define AGP_CNTL__PENDING_SLOTS_SEL_MASK                0x00080000L
1473 #define AGP_CNTL__PENDING_SLOTS_SEL                     0x00080000L
1474 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK            0x00100000L
1475 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X                 0x00100000L
1476 #define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK               0x00200000L
1477 #define AGP_CNTL__DIS_QUEUED_GNT_FIX                    0x00200000L
1478 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK          0x00400000L
1479 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET               0x00400000L
1480 #define AGP_CNTL__EN_RBFCALM_MASK                       0x00800000L
1481 #define AGP_CNTL__EN_RBFCALM                            0x00800000L
1482 #define AGP_CNTL__FORCE_EXT_VREF_MASK                   0x01000000L
1483 #define AGP_CNTL__FORCE_EXT_VREF                        0x01000000L
1484 #define AGP_CNTL__DIS_RBF_MASK                          0x02000000L
1485 #define AGP_CNTL__DIS_RBF                               0x02000000L
1486 #define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK               0x04000000L
1487 #define AGP_CNTL__DELAY_FIRST_SBA_EN                    0x04000000L
1488 #define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK              0x38000000L
1489 #define AGP_CNTL__AGP_MISC_MASK                         0xc0000000L
1490
1491 /* AGP_CNTL */
1492 #define AGP_CNTL__MAX_IDLE_CLK__SHIFT                   0x00000000
1493 #define AGP_CNTL__HOLD_RD_FIFO__SHIFT                   0x00000008
1494 #define AGP_CNTL__HOLD_RQ_FIFO__SHIFT                   0x00000009
1495 #define AGP_CNTL__EN_2X_STBB__SHIFT                     0x0000000a
1496 #define AGP_CNTL__FORCE_FULL_SBA__SHIFT                 0x0000000b
1497 #define AGP_CNTL__SBA_DIS__SHIFT                        0x0000000c
1498 #define AGP_CNTL__AGP_REV_ID__SHIFT                     0x0000000d
1499 #define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT              0x0000000e
1500 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT            0x0000000f
1501 #define AGP_CNTL__FORCE_INT_VREF__SHIFT                 0x00000010
1502 #define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT              0x00000011
1503 #define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT              0x00000013
1504 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT          0x00000014
1505 #define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT             0x00000015
1506 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT        0x00000016
1507 #define AGP_CNTL__EN_RBFCALM__SHIFT                     0x00000017
1508 #define AGP_CNTL__FORCE_EXT_VREF__SHIFT                 0x00000018
1509 #define AGP_CNTL__DIS_RBF__SHIFT                        0x00000019
1510 #define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT             0x0000001a
1511 #define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT            0x0000001b
1512 #define AGP_CNTL__AGP_MISC__SHIFT                       0x0000001e
1513
1514 /* DISP_MISC_CNTL */
1515 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK         0x00000001L
1516 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP              0x00000001L
1517 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK       0x00000002L
1518 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP            0x00000002L
1519 #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK          0x00000004L
1520 #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP               0x00000004L
1521 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK       0x00000010L
1522 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK            0x00000010L
1523 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK     0x00000020L
1524 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK          0x00000020L
1525 #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK        0x00000040L
1526 #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK             0x00000040L
1527 #define DISP_MISC_CNTL__SYNC_STRENGTH_MASK              0x00000300L
1528 #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK           0x00000400L
1529 #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN                0x00000400L
1530 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK        0x00001000L
1531 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP             0x00001000L
1532 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK      0x00008000L
1533 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK           0x00008000L
1534 #define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK            0x00010000L
1535 #define DISP_MISC_CNTL__SOFT_RESET_LVDS                 0x00010000L
1536 #define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK            0x00020000L
1537 #define DISP_MISC_CNTL__SOFT_RESET_TMDS                 0x00020000L
1538 #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK        0x00040000L
1539 #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS             0x00040000L
1540 #define DISP_MISC_CNTL__SOFT_RESET_TV_MASK              0x00080000L
1541 #define DISP_MISC_CNTL__SOFT_RESET_TV                   0x00080000L
1542 #define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK     0x00f00000L
1543 #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK      0x0f000000L
1544 #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK      0xf0000000L
1545
1546 /* DISP_PWR_MAN */
1547 #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK      0x00000001L
1548 #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN           0x00000001L
1549 #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK    0x00000010L
1550 #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN         0x00000010L
1551 #define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK            0x00000300L
1552 #define DISP_PWR_MAN__DISP_D3_RST_MASK                  0x00010000L
1553 #define DISP_PWR_MAN__DISP_D3_RST                       0x00010000L
1554 #define DISP_PWR_MAN__DISP_D3_REG_RST_MASK              0x00020000L
1555 #define DISP_PWR_MAN__DISP_D3_REG_RST                   0x00020000L
1556 #define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK             0x00040000L
1557 #define DISP_PWR_MAN__DISP_D3_GRPH_RST                  0x00040000L
1558 #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK           0x00080000L
1559 #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST                0x00080000L
1560 #define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK              0x00100000L
1561 #define DISP_PWR_MAN__DISP_D3_OV0_RST                   0x00100000L
1562 #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK           0x00200000L
1563 #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST                0x00200000L
1564 #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK         0x00400000L
1565 #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST              0x00400000L
1566 #define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK            0x00800000L
1567 #define DISP_PWR_MAN__DISP_D1D2_OV0_RST                 0x00800000L
1568 #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK          0x01000000L
1569 #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST               0x01000000L
1570 #define DISP_PWR_MAN__TV_ENABLE_RST_MASK                0x02000000L
1571 #define DISP_PWR_MAN__TV_ENABLE_RST                     0x02000000L
1572 #define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK                0x04000000L
1573 #define DISP_PWR_MAN__AUTO_PWRUP_EN                     0x04000000L
1574
1575 /* MC_IND_INDEX */
1576 #define MC_IND_INDEX__MC_IND_ADDR_MASK                  0x0000001fL
1577 #define MC_IND_INDEX__MC_IND_WR_EN_MASK                 0x00000100L
1578 #define MC_IND_INDEX__MC_IND_WR_EN                      0x00000100L
1579
1580 /* MC_IND_DATA */
1581 #define MC_IND_DATA__MC_IND_DATA_MASK                   0xffffffffL
1582
1583 /* MC_CHP_IO_CNTL_A1 */
1584 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT         0x00000000
1585 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT          0x00000001
1586 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT        0x00000002
1587 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT        0x00000003
1588 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT         0x00000004
1589 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT          0x00000005
1590 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT        0x00000006
1591 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT        0x00000007
1592 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT         0x00000008
1593 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT       0x00000009
1594 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT       0x0000000a
1595 #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT          0x0000000c
1596 #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT           0x0000000e
1597 #define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT            0x00000010
1598 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT          0x00000012
1599 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT          0x00000014
1600 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT       0x00000016
1601 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT      0x00000017
1602 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT          0x00000018
1603 #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT          0x0000001a
1604 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT          0x0000001c
1605 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT      0x0000001e
1606 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT      0x0000001f
1607
1608 /* MC_CHP_IO_CNTL_B1 */
1609 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT         0x00000000
1610 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT          0x00000001
1611 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT        0x00000002
1612 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT        0x00000003
1613 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT         0x00000004
1614 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT          0x00000005
1615 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT        0x00000006
1616 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT        0x00000007
1617 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT         0x00000008
1618 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT       0x00000009
1619 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT       0x0000000a
1620 #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT          0x0000000c
1621 #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT           0x0000000e
1622 #define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT            0x00000010
1623 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT          0x00000012
1624 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT          0x00000014
1625 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT       0x00000016
1626 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT      0x00000017
1627 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT          0x00000018
1628 #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT          0x0000001a
1629 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT          0x0000001c
1630 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT      0x0000001e
1631 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT      0x0000001f
1632
1633 /* MC_CHP_IO_CNTL_A1 */
1634 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK           0x00000001L
1635 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA                0x00000001L
1636 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK            0x00000002L
1637 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA                 0x00000002L
1638 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK          0x00000004L
1639 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA               0x00000004L
1640 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK          0x00000008L
1641 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA               0x00000008L
1642 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK           0x00000010L
1643 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA                0x00000010L
1644 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK            0x00000020L
1645 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA                 0x00000020L
1646 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK          0x00000040L
1647 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA               0x00000040L
1648 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK          0x00000080L
1649 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA               0x00000080L
1650 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK           0x00000100L
1651 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA                0x00000100L
1652 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK         0x00000200L
1653 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA              0x00000200L
1654 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK         0x00000400L
1655 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA              0x00000400L
1656 #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK            0x00003000L
1657 #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK             0x0000c000L
1658 #define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK              0x00030000L
1659 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK            0x000c0000L
1660 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK            0x00300000L
1661 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK         0x00400000L
1662 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA              0x00400000L
1663 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK        0x00800000L
1664 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA             0x00800000L
1665 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK            0x03000000L
1666 #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK            0x0c000000L
1667 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK            0x10000000L
1668 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA                 0x10000000L
1669 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK        0x40000000L
1670 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A             0x40000000L
1671 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK        0x80000000L
1672 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A             0x80000000L
1673
1674 /* MC_CHP_IO_CNTL_B1 */
1675 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK           0x00000001L
1676 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB                0x00000001L
1677 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK            0x00000002L
1678 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB                 0x00000002L
1679 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK          0x00000004L
1680 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB               0x00000004L
1681 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK          0x00000008L
1682 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB               0x00000008L
1683 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK           0x00000010L
1684 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB                0x00000010L
1685 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK            0x00000020L
1686 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB                 0x00000020L
1687 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK          0x00000040L
1688 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB               0x00000040L
1689 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK          0x00000080L
1690 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB               0x00000080L
1691 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK           0x00000100L
1692 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB                0x00000100L
1693 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK         0x00000200L
1694 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB              0x00000200L
1695 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK         0x00000400L
1696 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB              0x00000400L
1697 #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK            0x00003000L
1698 #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK             0x0000c000L
1699 #define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK              0x00030000L
1700 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK            0x000c0000L
1701 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK            0x00300000L
1702 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK         0x00400000L
1703 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB              0x00400000L
1704 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK        0x00800000L
1705 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB             0x00800000L
1706 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK            0x03000000L
1707 #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK            0x0c000000L
1708 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK            0x10000000L
1709 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB                 0x10000000L
1710 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK        0x40000000L
1711 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B             0x40000000L
1712 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK        0x80000000L
1713 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B             0x80000000L
1714
1715 /* MEM_SDRAM_MODE_REG */
1716 #define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK           0x00007fffL
1717 #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK         0x000f0000L
1718 #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK        0x00700000L
1719 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK        0x00800000L
1720 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY             0x00800000L
1721 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK        0x01000000L
1722 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY             0x01000000L
1723 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK       0x02000000L
1724 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD            0x02000000L
1725 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK      0x04000000L
1726 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA           0x04000000L
1727 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK       0x08000000L
1728 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR            0x08000000L
1729 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK       0x10000000L
1730 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE            0x10000000L
1731 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK            0x20000000L
1732 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL                 0x20000000L
1733 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK           0x40000000L
1734 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE                0x40000000L
1735 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK        0x80000000L
1736 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET             0x80000000L
1737
1738 /* MEM_SDRAM_MODE_REG */
1739 #define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT         0x00000000
1740 #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT       0x00000010
1741 #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT      0x00000014
1742 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT      0x00000017
1743 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT      0x00000018
1744 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT     0x00000019
1745 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT    0x0000001a
1746 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT     0x0000001b
1747 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT     0x0000001c
1748 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT          0x0000001d
1749 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT         0x0000001e
1750 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT      0x0000001f
1751
1752 /* MEM_REFRESH_CNTL */
1753 #define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK         0x000000ffL
1754 #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK          0x00000100L
1755 #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS               0x00000100L
1756 #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK          0x00000200L
1757 #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE               0x00000200L
1758 #define MEM_REFRESH_CNTL__MEM_TRFC_MASK                 0x0000f000L
1759 #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK         0x00010000L
1760 #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE              0x00010000L
1761 #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK        0x00020000L
1762 #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE             0x00020000L
1763 #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK         0x00040000L
1764 #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE              0x00040000L
1765 #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK        0x00080000L
1766 #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE             0x00080000L
1767 #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK        0x00100000L
1768 #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE             0x00100000L
1769 #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK          0x00c00000L
1770 #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK         0x01000000L
1771 #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE              0x01000000L
1772 #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK        0x02000000L
1773 #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE             0x02000000L
1774 #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK         0x04000000L
1775 #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE              0x04000000L
1776 #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK        0x08000000L
1777 #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE             0x08000000L
1778 #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK        0x10000000L
1779 #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE             0x10000000L
1780 #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK          0xc0000000L
1781
1782 /* MC_STATUS */
1783 #define MC_STATUS__MEM_PWRUP_COMPL_A_MASK               0x00000001L
1784 #define MC_STATUS__MEM_PWRUP_COMPL_A                    0x00000001L
1785 #define MC_STATUS__MEM_PWRUP_COMPL_B_MASK               0x00000002L
1786 #define MC_STATUS__MEM_PWRUP_COMPL_B                    0x00000002L
1787 #define MC_STATUS__MC_IDLE_MASK                         0x00000004L
1788 #define MC_STATUS__MC_IDLE                              0x00000004L
1789 #define MC_STATUS__IMP_N_VALUE_R_BACK_MASK              0x00000078L
1790 #define MC_STATUS__IMP_P_VALUE_R_BACK_MASK              0x00000780L
1791 #define MC_STATUS__TEST_OUT_R_BACK_MASK                 0x00000800L
1792 #define MC_STATUS__TEST_OUT_R_BACK                      0x00000800L
1793 #define MC_STATUS__DUMMY_OUT_R_BACK_MASK                0x00001000L
1794 #define MC_STATUS__DUMMY_OUT_R_BACK                     0x00001000L
1795 #define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK            0x0001e000L
1796 #define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK            0x001e0000L
1797 #define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK           0x01e00000L
1798 #define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK           0x1e000000L
1799
1800 /* MDLL_CKO */
1801 #define MDLL_CKO__MCKOA_SLEEP_MASK                      0x00000001L
1802 #define MDLL_CKO__MCKOA_SLEEP                           0x00000001L
1803 #define MDLL_CKO__MCKOA_RESET_MASK                      0x00000002L
1804 #define MDLL_CKO__MCKOA_RESET                           0x00000002L
1805 #define MDLL_CKO__MCKOA_RANGE_MASK                      0x0000000cL
1806 #define MDLL_CKO__ERSTA_SOUTSEL_MASK                    0x00000030L
1807 #define MDLL_CKO__MCKOA_FB_SEL_MASK                     0x000000c0L
1808 #define MDLL_CKO__MCKOA_REF_SKEW_MASK                   0x00000700L
1809 #define MDLL_CKO__MCKOA_FB_SKEW_MASK                    0x00007000L
1810 #define MDLL_CKO__MCKOA_BP_SEL_MASK                     0x00008000L
1811 #define MDLL_CKO__MCKOA_BP_SEL                          0x00008000L
1812 #define MDLL_CKO__MCKOB_SLEEP_MASK                      0x00010000L
1813 #define MDLL_CKO__MCKOB_SLEEP                           0x00010000L
1814 #define MDLL_CKO__MCKOB_RESET_MASK                      0x00020000L
1815 #define MDLL_CKO__MCKOB_RESET                           0x00020000L
1816 #define MDLL_CKO__MCKOB_RANGE_MASK                      0x000c0000L
1817 #define MDLL_CKO__ERSTB_SOUTSEL_MASK                    0x00300000L
1818 #define MDLL_CKO__MCKOB_FB_SEL_MASK                     0x00c00000L
1819 #define MDLL_CKO__MCKOB_REF_SKEW_MASK                   0x07000000L
1820 #define MDLL_CKO__MCKOB_FB_SKEW_MASK                    0x70000000L
1821 #define MDLL_CKO__MCKOB_BP_SEL_MASK                     0x80000000L
1822 #define MDLL_CKO__MCKOB_BP_SEL                          0x80000000L
1823
1824 /* MDLL_RDCKA */
1825 #define MDLL_RDCKA__MRDCKA0_SLEEP_MASK                  0x00000001L
1826 #define MDLL_RDCKA__MRDCKA0_SLEEP                       0x00000001L
1827 #define MDLL_RDCKA__MRDCKA0_RESET_MASK                  0x00000002L
1828 #define MDLL_RDCKA__MRDCKA0_RESET                       0x00000002L
1829 #define MDLL_RDCKA__MRDCKA0_RANGE_MASK                  0x0000000cL
1830 #define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK                0x00000030L
1831 #define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK                 0x000000c0L
1832 #define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK               0x00000700L
1833 #define MDLL_RDCKA__MRDCKA0_SINSEL_MASK                 0x00000800L
1834 #define MDLL_RDCKA__MRDCKA0_SINSEL                      0x00000800L
1835 #define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK                0x00007000L
1836 #define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK                 0x00008000L
1837 #define MDLL_RDCKA__MRDCKA0_BP_SEL                      0x00008000L
1838 #define MDLL_RDCKA__MRDCKA1_SLEEP_MASK                  0x00010000L
1839 #define MDLL_RDCKA__MRDCKA1_SLEEP                       0x00010000L
1840 #define MDLL_RDCKA__MRDCKA1_RESET_MASK                  0x00020000L
1841 #define MDLL_RDCKA__MRDCKA1_RESET                       0x00020000L
1842 #define MDLL_RDCKA__MRDCKA1_RANGE_MASK                  0x000c0000L
1843 #define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK                0x00300000L
1844 #define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK                 0x00c00000L
1845 #define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK               0x07000000L
1846 #define MDLL_RDCKA__MRDCKA1_SINSEL_MASK                 0x08000000L
1847 #define MDLL_RDCKA__MRDCKA1_SINSEL                      0x08000000L
1848 #define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK                0x70000000L
1849 #define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK                 0x80000000L
1850 #define MDLL_RDCKA__MRDCKA1_BP_SEL                      0x80000000L
1851
1852 /* MDLL_RDCKB */
1853 #define MDLL_RDCKB__MRDCKB0_SLEEP_MASK                  0x00000001L
1854 #define MDLL_RDCKB__MRDCKB0_SLEEP                       0x00000001L
1855 #define MDLL_RDCKB__MRDCKB0_RESET_MASK                  0x00000002L
1856 #define MDLL_RDCKB__MRDCKB0_RESET                       0x00000002L
1857 #define MDLL_RDCKB__MRDCKB0_RANGE_MASK                  0x0000000cL
1858 #define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK                0x00000030L
1859 #define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK                 0x000000c0L
1860 #define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK               0x00000700L
1861 #define MDLL_RDCKB__MRDCKB0_SINSEL_MASK                 0x00000800L
1862 #define MDLL_RDCKB__MRDCKB0_SINSEL                      0x00000800L
1863 #define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK                0x00007000L
1864 #define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK                 0x00008000L
1865 #define MDLL_RDCKB__MRDCKB0_BP_SEL                      0x00008000L
1866 #define MDLL_RDCKB__MRDCKB1_SLEEP_MASK                  0x00010000L
1867 #define MDLL_RDCKB__MRDCKB1_SLEEP                       0x00010000L
1868 #define MDLL_RDCKB__MRDCKB1_RESET_MASK                  0x00020000L
1869 #define MDLL_RDCKB__MRDCKB1_RESET                       0x00020000L
1870 #define MDLL_RDCKB__MRDCKB1_RANGE_MASK                  0x000c0000L
1871 #define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK                0x00300000L
1872 #define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK                 0x00c00000L
1873 #define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK               0x07000000L
1874 #define MDLL_RDCKB__MRDCKB1_SINSEL_MASK                 0x08000000L
1875 #define MDLL_RDCKB__MRDCKB1_SINSEL                      0x08000000L
1876 #define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK                0x70000000L
1877 #define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK                 0x80000000L
1878 #define MDLL_RDCKB__MRDCKB1_BP_SEL                      0x80000000L
1879
1880 #define MDLL_R300_RDCK__MRDCKA_SLEEP                    0x00000001L
1881 #define MDLL_R300_RDCK__MRDCKA_RESET                    0x00000002L
1882 #define MDLL_R300_RDCK__MRDCKB_SLEEP                    0x00000004L
1883 #define MDLL_R300_RDCK__MRDCKB_RESET                    0x00000008L
1884 #define MDLL_R300_RDCK__MRDCKC_SLEEP                    0x00000010L
1885 #define MDLL_R300_RDCK__MRDCKC_RESET                    0x00000020L
1886 #define MDLL_R300_RDCK__MRDCKD_SLEEP                    0x00000040L
1887 #define MDLL_R300_RDCK__MRDCKD_RESET                    0x00000080L
1888
1889 #define pllCLK_PIN_CNTL                         0x0001
1890 #define pllPPLL_CNTL                            0x0002
1891 #define pllPPLL_REF_DIV                         0x0003
1892 #define pllPPLL_DIV_0                           0x0004
1893 #define pllPPLL_DIV_1                           0x0005
1894 #define pllPPLL_DIV_2                           0x0006
1895 #define pllPPLL_DIV_3                           0x0007
1896 #define pllVCLK_ECP_CNTL                        0x0008
1897 #define pllHTOTAL_CNTL                          0x0009
1898 #define pllM_SPLL_REF_FB_DIV                    0x000A
1899 #define pllAGP_PLL_CNTL                         0x000B
1900 #define pllSPLL_CNTL                            0x000C
1901 #define pllSCLK_CNTL                            0x000D
1902 #define pllMPLL_CNTL                            0x000E
1903 #define pllMDLL_CKO                             0x000F
1904 #define pllMDLL_RDCKA                           0x0010
1905 #define pllMDLL_RDCKB                           0x0011
1906 #define pllMCLK_CNTL                            0x0012
1907 #define pllPLL_TEST_CNTL                        0x0013
1908 #define pllCLK_PWRMGT_CNTL                      0x0014
1909 #define pllPLL_PWRMGT_CNTL                      0x0015
1910 #define pllCG_TEST_MACRO_RW_WRITE               0x0016
1911 #define pllCG_TEST_MACRO_RW_READ                0x0017
1912 #define pllCG_TEST_MACRO_RW_DATA                0x0018
1913 #define pllCG_TEST_MACRO_RW_CNTL                0x0019
1914 #define pllDISP_TEST_MACRO_RW_WRITE             0x001A
1915 #define pllDISP_TEST_MACRO_RW_READ              0x001B
1916 #define pllDISP_TEST_MACRO_RW_DATA              0x001C
1917 #define pllDISP_TEST_MACRO_RW_CNTL              0x001D
1918 #define pllSCLK_CNTL2                           0x001E
1919 #define pllMCLK_MISC                            0x001F
1920 #define pllTV_PLL_FINE_CNTL                     0x0020
1921 #define pllTV_PLL_CNTL                          0x0021
1922 #define pllTV_PLL_CNTL1                         0x0022
1923 #define pllTV_DTO_INCREMENTS                    0x0023
1924 #define pllSPLL_AUX_CNTL                        0x0024
1925 #define pllMPLL_AUX_CNTL                        0x0025
1926 #define pllP2PLL_CNTL                           0x002A
1927 #define pllP2PLL_REF_DIV                        0x002B
1928 #define pllP2PLL_DIV_0                          0x002C
1929 #define pllPIXCLKS_CNTL                         0x002D
1930 #define pllHTOTAL2_CNTL                         0x002E
1931 #define pllSSPLL_CNTL                           0x0030
1932 #define pllSSPLL_REF_DIV                        0x0031
1933 #define pllSSPLL_DIV_0                          0x0032
1934 #define pllSS_INT_CNTL                          0x0033
1935 #define pllSS_TST_CNTL                          0x0034
1936 #define pllSCLK_MORE_CNTL                       0x0035
1937
1938 #define ixMC_PERF_CNTL                          0x0000
1939 #define ixMC_PERF_SEL                           0x0001
1940 #define ixMC_PERF_REGION_0                      0x0002
1941 #define ixMC_PERF_REGION_1                      0x0003
1942 #define ixMC_PERF_COUNT_0                       0x0004
1943 #define ixMC_PERF_COUNT_1                       0x0005
1944 #define ixMC_PERF_COUNT_2                       0x0006
1945 #define ixMC_PERF_COUNT_3                       0x0007
1946 #define ixMC_PERF_COUNT_MEMCH_A                 0x0008
1947 #define ixMC_PERF_COUNT_MEMCH_B                 0x0009
1948 #define ixMC_IMP_CNTL                           0x000A
1949 #define ixMC_CHP_IO_CNTL_A0                     0x000B
1950 #define ixMC_CHP_IO_CNTL_A1                     0x000C
1951 #define ixMC_CHP_IO_CNTL_B0                     0x000D
1952 #define ixMC_CHP_IO_CNTL_B1                     0x000E
1953 #define ixMC_IMP_CNTL_0                         0x000F
1954 #define ixTC_MISMATCH_1                         0x0010
1955 #define ixTC_MISMATCH_2                         0x0011
1956 #define ixMC_BIST_CTRL                          0x0012
1957 #define ixREG_COLLAR_WRITE                      0x0013
1958 #define ixREG_COLLAR_READ                       0x0014
1959 #define ixR300_MC_IMP_CNTL                      0x0018
1960 #define ixR300_MC_CHP_IO_CNTL_A0                0x0019
1961 #define ixR300_MC_CHP_IO_CNTL_A1                0x001a
1962 #define ixR300_MC_CHP_IO_CNTL_B0                0x001b
1963 #define ixR300_MC_CHP_IO_CNTL_B1                0x001c
1964 #define ixR300_MC_CHP_IO_CNTL_C0                0x001d
1965 #define ixR300_MC_CHP_IO_CNTL_C1                0x001e
1966 #define ixR300_MC_CHP_IO_CNTL_D0                0x001f
1967 #define ixR300_MC_CHP_IO_CNTL_D1                0x0020
1968 #define ixR300_MC_IMP_CNTL_0                    0x0021
1969 #define ixR300_MC_ELPIDA_CNTL                   0x0022
1970 #define ixR300_MC_CHP_IO_OE_CNTL_CD             0x0023
1971 #define ixR300_MC_READ_CNTL_CD                  0x0024
1972 #define ixR300_MC_MC_INIT_WR_LAT_TIMER          0x0025
1973 #define ixR300_MC_DEBUG_CNTL                    0x0026
1974 #define ixR300_MC_BIST_CNTL_0                   0x0028
1975 #define ixR300_MC_BIST_CNTL_1                   0x0029
1976 #define ixR300_MC_BIST_CNTL_2                   0x002a
1977 #define ixR300_MC_BIST_CNTL_3                   0x002b
1978 #define ixR300_MC_BIST_CNTL_4                   0x002c
1979 #define ixR300_MC_BIST_CNTL_5                   0x002d
1980 #define ixR300_MC_IMP_STATUS                    0x002e
1981 #define ixR300_MC_DLL_CNTL                      0x002f
1982 #define NB_TOM                                  0x15C
1983
1984 #endif  /* _RADEON_H */