1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
24 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
25 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
26 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
27 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
28 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License as
32 * published by the Free Software Foundation; either version 2 of
33 * the License, or (at your option) any later version.
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
49 #define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
51 /*--------------------------------------------------------------------- */
52 /* Special Purpose Registers */
53 /*--------------------------------------------------------------------- */
56 #define dec 0x016 /* decrementer */
57 #define srr0 0x01a /* save/restore register 0 */
58 #define srr1 0x01b /* save/restore register 1 */
59 #define pid 0x030 /* process id */
60 #define decar 0x036 /* decrementer auto-reload */
61 #define csrr0 0x03a /* critical save/restore register 0 */
62 #define csrr1 0x03b /* critical save/restore register 1 */
63 #define dear 0x03d /* data exception address register */
64 #define esr 0x03e /* exception syndrome register */
65 #define ivpr 0x03f /* interrupt prefix register */
66 #define usprg0 0x100 /* user special purpose register general 0 */
67 #define usprg1 0x110 /* user special purpose register general 1 */
68 #define tblr 0x10c /* time base lower, read only */
69 #define tbur 0x10d /* time base upper, read only */
70 #define sprg1 0x111 /* special purpose register general 1 */
71 #define sprg2 0x112 /* special purpose register general 2 */
72 #define sprg3 0x113 /* special purpose register general 3 */
73 #define sprg4 0x114 /* special purpose register general 4 */
74 #define sprg5 0x115 /* special purpose register general 5 */
75 #define sprg6 0x116 /* special purpose register general 6 */
76 #define sprg7 0x117 /* special purpose register general 7 */
77 #define tbl 0x11c /* time base lower (supervisor)*/
78 #define tbu 0x11d /* time base upper (supervisor)*/
79 #define pir 0x11e /* processor id register */
80 /*#define pvr 0x11f processor version register */
81 #define dbsr 0x130 /* debug status register */
82 #define dbcr0 0x134 /* debug control register 0 */
83 #define dbcr1 0x135 /* debug control register 1 */
84 #define dbcr2 0x136 /* debug control register 2 */
85 #define iac1 0x138 /* instruction address compare 1 */
86 #define iac2 0x139 /* instruction address compare 2 */
87 #define iac3 0x13a /* instruction address compare 3 */
88 #define iac4 0x13b /* instruction address compare 4 */
89 #define dac1 0x13c /* data address compare 1 */
90 #define dac2 0x13d /* data address compare 2 */
91 #define dvc1 0x13e /* data value compare 1 */
92 #define dvc2 0x13f /* data value compare 2 */
93 #define tsr 0x150 /* timer status register */
94 #define tcr 0x154 /* timer control register */
95 #define ivor0 0x190 /* interrupt vector offset register 0 */
96 #define ivor1 0x191 /* interrupt vector offset register 1 */
97 #define ivor2 0x192 /* interrupt vector offset register 2 */
98 #define ivor3 0x193 /* interrupt vector offset register 3 */
99 #define ivor4 0x194 /* interrupt vector offset register 4 */
100 #define ivor5 0x195 /* interrupt vector offset register 5 */
101 #define ivor6 0x196 /* interrupt vector offset register 6 */
102 #define ivor7 0x197 /* interrupt vector offset register 7 */
103 #define ivor8 0x198 /* interrupt vector offset register 8 */
104 #define ivor9 0x199 /* interrupt vector offset register 9 */
105 #define ivor10 0x19a /* interrupt vector offset register 10 */
106 #define ivor11 0x19b /* interrupt vector offset register 11 */
107 #define ivor12 0x19c /* interrupt vector offset register 12 */
108 #define ivor13 0x19d /* interrupt vector offset register 13 */
109 #define ivor14 0x19e /* interrupt vector offset register 14 */
110 #define ivor15 0x19f /* interrupt vector offset register 15 */
111 #if defined(CONFIG_440)
112 #define mcsrr0 0x23a /* machine check save/restore register 0 */
113 #define mcsrr1 0x23b /* mahcine check save/restore register 1 */
114 #define mcsr 0x23c /* machine check status register */
116 #define inv0 0x370 /* instruction cache normal victim 0 */
117 #define inv1 0x371 /* instruction cache normal victim 1 */
118 #define inv2 0x372 /* instruction cache normal victim 2 */
119 #define inv3 0x373 /* instruction cache normal victim 3 */
120 #define itv0 0x374 /* instruction cache transient victim 0 */
121 #define itv1 0x375 /* instruction cache transient victim 1 */
122 #define itv2 0x376 /* instruction cache transient victim 2 */
123 #define itv3 0x377 /* instruction cache transient victim 3 */
124 #define dnv0 0x390 /* data cache normal victim 0 */
125 #define dnv1 0x391 /* data cache normal victim 1 */
126 #define dnv2 0x392 /* data cache normal victim 2 */
127 #define dnv3 0x393 /* data cache normal victim 3 */
128 #define dtv0 0x394 /* data cache transient victim 0 */
129 #define dtv1 0x395 /* data cache transient victim 1 */
130 #define dtv2 0x396 /* data cache transient victim 2 */
131 #define dtv3 0x397 /* data cache transient victim 3 */
132 #define dvlim 0x398 /* data cache victim limit */
133 #define ivlim 0x399 /* instruction cache victim limit */
134 #define rstcfg 0x39b /* reset configuration */
135 #define dcdbtrl 0x39c /* data cache debug tag register low */
136 #define dcdbtrh 0x39d /* data cache debug tag register high */
137 #define icdbtrl 0x39e /* instruction cache debug tag register low */
138 #define icdbtrh 0x39f /* instruction cache debug tag register high */
139 #define mmucr 0x3b2 /* mmu control register */
140 #define ccr0 0x3b3 /* core configuration register 0 */
141 #define ccr1 0x378 /* core configuration for 440x5 only */
142 #define icdbdr 0x3d3 /* instruction cache debug data register */
143 #define dbdr 0x3f3 /* debug data register */
145 /******************************************************************************
147 ******************************************************************************/
149 /*-----------------------------------------------------------------------------
150 | Clocking Controller
151 +----------------------------------------------------------------------------*/
152 /* values for clkcfga register - indirect addressing of these regs */
153 #define clk_clkukpd 0x0020
154 #define clk_pllc 0x0040
155 #define clk_plld 0x0060
156 #define clk_primad 0x0080
157 #define clk_primbd 0x00a0
158 #define clk_opbd 0x00c0
159 #define clk_perd 0x00e0
160 #define clk_mald 0x0100
161 #define clk_spcid 0x0120
162 #define clk_icfg 0x0140
164 /* 440gx sdr register definations */
165 #define sdr_sdstp0 0x0020 /* */
166 #define sdr_sdstp1 0x0021 /* */
167 #define SDR_PINSTP 0x0040
168 #define sdr_sdcs 0x0060
169 #define sdr_ecid0 0x0080
170 #define sdr_ecid1 0x0081
171 #define sdr_ecid2 0x0082
172 #define sdr_jtag 0x00c0
173 #if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
174 #define sdr_ddrdl 0x00e0
176 #define sdr_cfg 0x00e0
177 #define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/
178 #define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */
179 #define SDR_CFG_32BITS 0x00000000 /* 32 bits */
180 #define SDR_CFG_64BITS 0x01000000 /* 64 bits */
181 #define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
182 #define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */
183 #define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */
184 #endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
185 #define sdr_ebc 0x0100
186 #define sdr_uart0 0x0120 /* UART0 Config */
187 #define sdr_uart1 0x0121 /* UART1 Config */
188 #define sdr_uart2 0x0122 /* UART2 Config */
189 #define sdr_uart3 0x0123 /* UART3 Config */
190 #define sdr_cp440 0x0180
191 #define sdr_xcr 0x01c0
192 #define sdr_xpllc 0x01c1
193 #define sdr_xplld 0x01c2
194 #define sdr_srst 0x0200
195 #define sdr_slpipe 0x0220
196 #define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
197 #define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
198 #define sdr_mirq0 0x0260
199 #define sdr_mirq1 0x0261
200 #define sdr_maltbl 0x0280
201 #define sdr_malrbl 0x02a0
202 #define sdr_maltbs 0x02c0
203 #define sdr_malrbs 0x02e0
204 #define sdr_pci0 0x0300
205 #define sdr_usb0 0x0320
206 #define sdr_cust0 0x4000
207 #define sdr_cust1 0x4002
208 #define sdr_pfc0 0x4100 /* Pin Function 0 */
209 #define sdr_pfc1 0x4101 /* Pin Function 1 */
210 #define sdr_plbtr 0x4200
211 #define sdr_mfr 0x4300 /* SDR0_MFR reg */
214 #define sdr_amp 0x0240
215 #define sdr_xpllc 0x01c1
216 #define sdr_xplld 0x01c2
217 #define sdr_xcr 0x01c0
218 #define sdr_sdstp2 0x4001
219 #define sdr_sdstp3 0x4003
220 #endif /* CONFIG_440GX */
222 /*----------------------------------------------------------------------------+
223 | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
224 +----------------------------------------------------------------------------*/
225 #define CCR0_PRE 0x40000000
226 #define CCR0_CRPE 0x08000000
227 #define CCR0_DSTG 0x00200000
228 #define CCR0_DAPUIB 0x00100000
229 #define CCR0_DTB 0x00008000
230 #define CCR0_GICBT 0x00004000
231 #define CCR0_GDCBT 0x00002000
232 #define CCR0_FLSTA 0x00000100
233 #define CCR0_ICSLC_MASK 0x0000000C
234 #define CCR0_ICSLT_MASK 0x00000003
235 #define CCR1_TCS_MASK 0x00000080
236 #define CCR1_TCS_INTCLK 0x00000000
237 #define CCR1_TCS_EXTCLK 0x00000080
238 #define MMUCR_SWOA 0x01000000
239 #define MMUCR_U1TE 0x00400000
240 #define MMUCR_U2SWOAE 0x00200000
241 #define MMUCR_DULXE 0x00800000
242 #define MMUCR_IULXE 0x00400000
243 #define MMUCR_STS 0x00100000
244 #define MMUCR_STID_MASK 0x000000FF
248 #define sdr_sdstp2 0x0022
250 #define sdr_sdstp3 0x0023
251 #define sdr_ddr0 0x00E1
252 #define sdr_uart2 0x0122
253 #define sdr_xcr0 0x01c0
254 /* #define sdr_xcr1 0x01c3 only one PCIX - SG */
255 /* #define sdr_xcr2 0x01c6 only one PCIX - SG */
256 #define sdr_xpllc0 0x01c1
257 #define sdr_xplld0 0x01c2
258 #define sdr_xpllc1 0x01c4 /*notRCW - SG */
259 #define sdr_xplld1 0x01c5 /*notRCW - SG */
260 #define sdr_xpllc2 0x01c7 /*notRCW - SG */
261 #define sdr_xplld2 0x01c8 /*notRCW - SG */
262 #define sdr_amp0 0x0240
263 #define sdr_amp1 0x0241
264 #define sdr_cust2 0x4004
265 #define sdr_cust3 0x4006
266 #define sdr_sdstp4 0x4001
267 #define sdr_sdstp5 0x4003
268 #define sdr_sdstp6 0x4005
269 #define sdr_sdstp7 0x4007
271 /******************************************************************************
272 * PCI express defines
273 ******************************************************************************/
274 #define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */
275 #define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */
276 #define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */
277 #define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */
278 #define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */
279 #define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */
280 #define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */
281 #define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */
282 #define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */
283 #define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */
284 #define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */
285 #define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */
286 #define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */
287 #define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */
288 #define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */
289 #define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */
290 #define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */
291 #define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */
292 #define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */
293 #define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */
294 #define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */
295 #define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */
296 #define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */
297 #define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */
298 #define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */
299 #define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */
300 #define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */
301 #define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */
302 #define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */
303 #define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */
304 #define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */
305 #define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */
306 #define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */
308 #define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */
309 #define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */
310 #define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */
311 #define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */
312 #define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */
313 #define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */
314 #define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */
315 #define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */
316 #define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */
317 #define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */
318 #define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */
319 #define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */
320 #define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */
321 #define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */
322 #define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */
323 #define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */
324 #define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */
325 #define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */
326 #define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */
327 #define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */
328 #define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */
329 #define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */
330 #define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */
331 #define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */
332 #define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */
333 #define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */
334 #define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */
335 #define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */
336 #define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */
337 #define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */
338 #define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */
339 #define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */
340 #define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */
341 #define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */
342 #define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */
343 #define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */
344 #define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */
345 #define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */
346 #define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */
347 #define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */
348 #define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
349 #define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
350 #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
351 #endif /* CONFIG_440SPE */
353 /*-----------------------------------------------------------------------------
354 | External Bus Controller
355 +----------------------------------------------------------------------------*/
356 /* values for ebccfga register - indirect addressing of these regs */
357 #define pb0cr 0x00 /* periph bank 0 config reg */
358 #define pb1cr 0x01 /* periph bank 1 config reg */
359 #define pb2cr 0x02 /* periph bank 2 config reg */
360 #define pb3cr 0x03 /* periph bank 3 config reg */
361 #define pb4cr 0x04 /* periph bank 4 config reg */
362 #define pb5cr 0x05 /* periph bank 5 config reg */
363 #define pb6cr 0x06 /* periph bank 6 config reg */
364 #define pb7cr 0x07 /* periph bank 7 config reg */
365 #define pb0ap 0x10 /* periph bank 0 access parameters */
366 #define pb1ap 0x11 /* periph bank 1 access parameters */
367 #define pb2ap 0x12 /* periph bank 2 access parameters */
368 #define pb3ap 0x13 /* periph bank 3 access parameters */
369 #define pb4ap 0x14 /* periph bank 4 access parameters */
370 #define pb5ap 0x15 /* periph bank 5 access parameters */
371 #define pb6ap 0x16 /* periph bank 6 access parameters */
372 #define pb7ap 0x17 /* periph bank 7 access parameters */
373 #define pbear 0x20 /* periph bus error addr reg */
374 #define pbesr 0x21 /* periph bus error status reg */
375 #define xbcfg 0x23 /* external bus configuration reg */
376 #define EBC0_CFG 0x23 /* external bus configuration reg */
377 #define xbcid 0x24 /* external bus core id reg */
379 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
380 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
382 /* PLB4 to PLB3 Bridge OUT */
383 #define P4P3_DCR_BASE 0x020
384 #define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
385 #define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
386 #define p4p3_eadr (P4P3_DCR_BASE+0x2)
387 #define p4p3_euadr (P4P3_DCR_BASE+0x3)
388 #define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
389 #define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
390 #define p4p3_confg (P4P3_DCR_BASE+0x6)
391 #define p4p3_pic (P4P3_DCR_BASE+0x7)
392 #define p4p3_peir (P4P3_DCR_BASE+0x8)
393 #define p4p3_rev (P4P3_DCR_BASE+0xA)
395 /* PLB3 to PLB4 Bridge IN */
396 #define P3P4_DCR_BASE 0x030
397 #define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
398 #define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
399 #define p3p4_eadr (P3P4_DCR_BASE+0x2)
400 #define p3p4_euadr (P3P4_DCR_BASE+0x3)
401 #define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
402 #define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
403 #define p3p4_confg (P3P4_DCR_BASE+0x6)
404 #define p3p4_pic (P3P4_DCR_BASE+0x7)
405 #define p3p4_peir (P3P4_DCR_BASE+0x8)
406 #define p3p4_rev (P3P4_DCR_BASE+0xA)
409 #define PLB3_DCR_BASE 0x070
410 #define plb3_revid (PLB3_DCR_BASE+0x2)
411 #define plb3_besr (PLB3_DCR_BASE+0x3)
412 #define plb3_bear (PLB3_DCR_BASE+0x6)
413 #define plb3_acr (PLB3_DCR_BASE+0x7)
415 /* PLB4 Arbiter - PowerPC440EP Pass1 */
416 #define PLB4_DCR_BASE 0x080
417 #define plb4_acr (PLB4_DCR_BASE+0x1)
418 #define plb4_revid (PLB4_DCR_BASE+0x2)
419 #define plb4_besr (PLB4_DCR_BASE+0x4)
420 #define plb4_bearl (PLB4_DCR_BASE+0x6)
421 #define plb4_bearh (PLB4_DCR_BASE+0x7)
423 #define PLB4_ACR_WRP (0x80000000 >> 7)
425 /* Nebula PLB4 Arbiter - PowerPC440EP */
426 #define PLB_ARBITER_BASE 0x80
428 #define plb0_revid (PLB_ARBITER_BASE+ 0x00)
429 #define plb0_acr (PLB_ARBITER_BASE+ 0x01)
430 #define plb0_acr_ppm_mask 0xF0000000
431 #define plb0_acr_ppm_fixed 0x00000000
432 #define plb0_acr_ppm_fair 0xD0000000
433 #define plb0_acr_hbu_mask 0x08000000
434 #define plb0_acr_hbu_disabled 0x00000000
435 #define plb0_acr_hbu_enabled 0x08000000
436 #define plb0_acr_rdp_mask 0x06000000
437 #define plb0_acr_rdp_disabled 0x00000000
438 #define plb0_acr_rdp_2deep 0x02000000
439 #define plb0_acr_rdp_3deep 0x04000000
440 #define plb0_acr_rdp_4deep 0x06000000
441 #define plb0_acr_wrp_mask 0x01000000
442 #define plb0_acr_wrp_disabled 0x00000000
443 #define plb0_acr_wrp_2deep 0x01000000
445 #define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
446 #define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
447 #define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
448 #define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
449 #define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
451 #define plb1_acr (PLB_ARBITER_BASE+ 0x09)
452 #define plb1_acr_ppm_mask 0xF0000000
453 #define plb1_acr_ppm_fixed 0x00000000
454 #define plb1_acr_ppm_fair 0xD0000000
455 #define plb1_acr_hbu_mask 0x08000000
456 #define plb1_acr_hbu_disabled 0x00000000
457 #define plb1_acr_hbu_enabled 0x08000000
458 #define plb1_acr_rdp_mask 0x06000000
459 #define plb1_acr_rdp_disabled 0x00000000
460 #define plb1_acr_rdp_2deep 0x02000000
461 #define plb1_acr_rdp_3deep 0x04000000
462 #define plb1_acr_rdp_4deep 0x06000000
463 #define plb1_acr_wrp_mask 0x01000000
464 #define plb1_acr_wrp_disabled 0x00000000
465 #define plb1_acr_wrp_2deep 0x01000000
467 #define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
468 #define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
469 #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
470 #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
472 /* Pin Function Control Register 1 */
473 #define SDR0_PFC1 0x4101
474 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
475 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
476 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
477 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
478 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
479 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
480 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
481 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
482 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
483 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
484 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
485 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
486 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
487 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
488 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
489 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
490 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
491 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
492 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
493 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
494 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
495 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
496 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
497 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
499 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
500 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
501 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
502 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
504 /* USB Control Register */
505 #define SDR0_USB0 0x0320
506 #define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
507 #define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
508 #define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
509 #define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
510 #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
511 #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
513 /* Miscealleneaous Function Reg. */
514 #define SDR0_MFR 0x4300
515 #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
516 #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
517 #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
518 #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
519 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
520 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
521 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
522 #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
523 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
524 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
525 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
526 #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
527 #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
529 #define SDR0_MFR_ERRATA3_EN0 0x00800000
530 #define SDR0_MFR_ERRATA3_EN1 0x00400000
531 #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
532 #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
533 #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
534 #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
535 #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
537 #define GPT0_COMP6 0x00000098
538 #define GPT0_COMP5 0x00000094
539 #define GPT0_COMP4 0x00000090
540 #define GPT0_COMP3 0x0000008C
541 #define GPT0_COMP2 0x00000088
542 #define GPT0_COMP1 0x00000084
544 #define GPT0_MASK6 0x000000D8
545 #define GPT0_MASK5 0x000000D4
546 #define GPT0_MASK4 0x000000D0
547 #define GPT0_MASK3 0x000000CC
548 #define GPT0_MASK2 0x000000C8
549 #define GPT0_MASK1 0x000000C4
551 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
552 #define SDR0_USB2D0CR 0x0320
553 #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
554 #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
555 #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
557 #define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
558 #define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
559 #define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
561 #define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
562 #define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
563 #define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
565 /* USB2 Host Control Register */
566 #define SDR0_USB2H0CR 0x0340
567 #define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
568 #define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
569 #define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
570 #define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
572 /* Pin Function Control Register 1 */
573 #define SDR0_PFC1 0x4101
574 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
575 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
576 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
578 #define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
579 #define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
580 #define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
581 #define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
582 #define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
583 #define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
584 #define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
585 #define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
587 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
588 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
589 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
590 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
591 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
592 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
593 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
594 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
595 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
596 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
597 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
598 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
599 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
600 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
601 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
602 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
603 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
604 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
605 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
606 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
607 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
609 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
610 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
611 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
612 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
614 /* Ethernet PLL Configuration Register */
615 #define SDR0_PFC2 0x4102
616 #define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
617 #define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
618 #define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
619 #define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
621 #define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
622 #define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
623 #define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
624 #define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
625 #define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
626 #define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
627 #define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
628 #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
630 #define SDR0_PFC4 0x4104
632 /* USB2PHY0 Control Register */
633 #define SDR0_USB2PHY0CR 0x4103
634 #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
635 #define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
636 #define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
638 #define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
639 #define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
640 #define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
642 #define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
643 #define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
644 #define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
646 #define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
647 #define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
648 #define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
650 #define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
651 #define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
652 #define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
654 #define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
655 #define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
656 #define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
658 #define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
659 #define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
660 #define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
662 #define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
663 #define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
664 #define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
666 #define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
667 #define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
668 #define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
670 #define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
671 #define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
672 #define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
673 #define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
675 /* Miscealleneaous Function Reg. */
676 #define SDR0_MFR 0x4300
677 #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
678 #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
679 #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
680 #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
681 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
682 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
683 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
684 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
685 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
686 #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
687 #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
689 #define SDR0_MFR_ERRATA3_EN0 0x00800000
690 #define SDR0_MFR_ERRATA3_EN1 0x00400000
691 #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
692 #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
693 #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
694 #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
695 #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
697 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
699 /* CUST1 Customer Configuration Register1 */
700 #define SDR0_CUST1 0x4002
701 #define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
702 #define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
703 #define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
705 /* Pin Function Control Register 0 */
706 #define SDR0_PFC0 0x4100
707 #define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
708 #define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
709 #define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
710 #define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
711 #define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
713 /* Pin Function Control Register 1 */
714 #define SDR0_PFC1 0x4101
715 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
716 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
717 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
718 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
719 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
720 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
721 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
722 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
723 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
724 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
725 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
726 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
727 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
728 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
729 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
730 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
731 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
732 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
733 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
734 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
735 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
736 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
737 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
738 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
740 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
741 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
742 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
743 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
745 #endif /* 440EP || 440GR || 440EPX || 440GRX */
747 /*-----------------------------------------------------------------------------
749 +----------------------------------------------------------------------------*/
750 #if defined (CONFIG_440GX) || \
751 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
752 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
753 defined(CONFIG_460SX)
754 #define L2_CACHE_BASE 0x030
755 #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
756 #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
757 #define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
758 #define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
759 #define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
760 #define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
761 #define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
762 #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
764 #endif /* CONFIG_440GX */
766 /*-----------------------------------------------------------------------------
768 +----------------------------------------------------------------------------*/
769 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
770 #define ISRAM0_DCR_BASE 0x380
772 #define ISRAM0_DCR_BASE 0x020
774 #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
775 #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
776 #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
777 #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
778 #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
779 #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
780 #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
781 #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
782 #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
783 #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
784 #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
786 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
787 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
788 defined(CONFIG_460EX) || defined(CONFIG_460GT)
789 /* CUST0 Customer Configuration Register0 */
790 #define SDR0_CUST0 0x4000
791 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
792 #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
793 #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
794 #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
796 #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
797 #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
798 #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
800 #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
801 #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
802 #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
804 #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
805 #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
806 #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
808 #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
809 #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
810 #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
812 #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
813 #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
814 #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
816 #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
817 #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
818 #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
820 #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
821 #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
822 #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
824 #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
825 #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
826 #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
827 #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
828 #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
829 #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
830 #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
833 /*-----------------------------------------------------------------------------
835 +----------------------------------------------------------------------------*/
836 /* TODO: as needed */
838 /*-----------------------------------------------------------------------------
839 | Clocking, Power Management and Chip Control
840 +----------------------------------------------------------------------------*/
841 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
842 defined(CONFIG_460SX)
843 #define CNTRL_DCR_BASE 0x160
845 #define CNTRL_DCR_BASE 0x0b0
848 #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
849 #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
850 #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
852 #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
853 #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
854 #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
855 #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
857 #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
858 #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
859 #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
860 #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
862 #define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
864 #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
865 #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
867 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
868 /*----------------------------------------------------------------------------+
869 | Clock / Power-on-reset DCR's.
870 +----------------------------------------------------------------------------*/
871 #define CPR0_CLKUPD 0x20
872 #define CPR0_CLKUPD_BSY_MASK 0x80000000
873 #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
874 #define CPR0_CLKUPD_BSY_BUSY 0x80000000
875 #define CPR0_CLKUPD_CUI_MASK 0x80000000
876 #define CPR0_CLKUPD_CUI_DISABLE 0x00000000
877 #define CPR0_CLKUPD_CUI_ENABLE 0x80000000
878 #define CPR0_CLKUPD_CUD_MASK 0x40000000
879 #define CPR0_CLKUPD_CUD_DISABLE 0x00000000
880 #define CPR0_CLKUPD_CUD_ENABLE 0x40000000
882 #define CPR0_PLLC 0x40
883 #define CPR0_PLLC_RST_MASK 0x80000000
884 #define CPR0_PLLC_RST_PLLLOCKED 0x00000000
885 #define CPR0_PLLC_RST_PLLRESET 0x80000000
886 #define CPR0_PLLC_ENG_MASK 0x40000000
887 #define CPR0_PLLC_ENG_DISABLE 0x00000000
888 #define CPR0_PLLC_ENG_ENABLE 0x40000000
889 #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
890 #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
891 #define CPR0_PLLC_SRC_MASK 0x20000000
892 #define CPR0_PLLC_SRC_PLLOUTA 0x00000000
893 #define CPR0_PLLC_SRC_PLLOUTB 0x20000000
894 #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
895 #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
896 #define CPR0_PLLC_SEL_MASK 0x07000000
897 #define CPR0_PLLC_SEL_PLLOUT 0x00000000
898 #define CPR0_PLLC_SEL_CPU 0x01000000
899 #define CPR0_PLLC_SEL_EBC 0x05000000
900 #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
901 #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
902 #define CPR0_PLLC_TUNE_MASK 0x000003FF
903 #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
904 #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
906 #define CPR0_PLLD 0x60
907 #define CPR0_PLLD_FBDV_MASK 0x1F000000
908 #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
909 #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
910 #define CPR0_PLLD_FWDVA_MASK 0x000F0000
911 #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
912 #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
913 #define CPR0_PLLD_FWDVB_MASK 0x00000700
914 #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
915 #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
916 #define CPR0_PLLD_LFBDV_MASK 0x0000003F
917 #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
918 #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
920 #define CPR0_PRIMAD 0x80
921 #define CPR0_PRIMAD_PRADV0_MASK 0x07000000
922 #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
923 #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
925 #define CPR0_PRIMBD 0xA0
926 #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
927 #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
928 #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
930 #define CPR0_OPBD 0xC0
931 #define CPR0_OPBD_OPBDV0_MASK 0x03000000
932 #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
933 #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
935 #define CPR0_PERD 0xE0
936 #if !defined(CONFIG_440EPX)
937 #define CPR0_PERD_PERDV0_MASK 0x03000000
938 #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
939 #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
942 #define CPR0_MALD 0x100
943 #define CPR0_MALD_MALDV0_MASK 0x03000000
944 #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
945 #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
947 #define CPR0_ICFG 0x140
948 #define CPR0_ICFG_RLI_MASK 0x80000000
949 #define CPR0_ICFG_RLI_RESETCPR 0x00000000
950 #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
951 #define CPR0_ICFG_ICS_MASK 0x00000007
952 #define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
953 #define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
955 /************************/
957 /************************/
958 #define IIC0_MMIO_BASE 0xA0000400
959 #define IIC1_MMIO_BASE 0xA0000500
961 #endif /* CONFIG_440SP */
963 /*-----------------------------------------------------------------------------
965 +----------------------------------------------------------------------------*/
966 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
967 #define DMA_DCR_BASE 0x200
969 #define DMA_DCR_BASE 0x100
971 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
972 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
973 #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
974 #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
975 #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
976 #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
977 #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
978 #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
979 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
980 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
981 #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
982 #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
983 #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
984 #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
985 #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
986 #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
987 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
988 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
989 #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
990 #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
991 #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
992 #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
993 #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
994 #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
995 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
996 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
997 #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
998 #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
999 #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
1000 #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
1001 #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
1002 #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
1003 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
1004 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
1005 #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
1006 #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
1008 /*-----------------------------------------------------------------------------
1009 | Memory Access Layer
1010 +----------------------------------------------------------------------------*/
1011 #define MAL_DCR_BASE 0x180
1012 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
1013 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
1014 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
1015 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
1016 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
1017 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
1018 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
1019 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
1020 #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
1021 #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
1022 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
1023 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
1024 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
1025 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
1026 #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
1027 #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
1028 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
1029 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
1030 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
1031 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
1032 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
1033 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
1034 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
1035 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
1036 #if defined(CONFIG_440GX) || \
1037 defined(CONFIG_460EX) || defined(CONFIG_460GT)
1038 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
1039 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
1040 #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */
1041 #define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */
1042 #define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */
1043 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
1044 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
1045 #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
1046 #define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
1047 #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
1048 #endif /* CONFIG_440GX */
1050 /*-----------------------------------------------------------------------------+
1052 +-----------------------------------------------------------------------------*/
1053 #if defined(CONFIG_440SP)
1054 #define SDR0_SRST 0x0200
1056 #define SDR0_DDR0 0x00E1
1057 #define SDR0_DDR0_DPLLRST 0x80000000
1058 #define SDR0_DDR0_DDRM_MASK 0x60000000
1059 #define SDR0_DDR0_DDRM_DDR1 0x20000000
1060 #define SDR0_DDR0_DDRM_DDR2 0x40000000
1061 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
1062 #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
1063 #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
1064 #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
1067 #if defined(CONFIG_440SPE) || defined(CONFIG_460SX)
1068 #define SDR0_CP440 0x0180
1069 #define SDR0_CP440_ERPN_MASK 0x30000000
1070 #define SDR0_CP440_ERPN_MASK_HI 0x3000
1071 #define SDR0_CP440_ERPN_MASK_LO 0x0000
1072 #define SDR0_CP440_ERPN_EBC 0x10000000
1073 #define SDR0_CP440_ERPN_EBC_HI 0x1000
1074 #define SDR0_CP440_ERPN_EBC_LO 0x0000
1075 #define SDR0_CP440_ERPN_PCI 0x20000000
1076 #define SDR0_CP440_ERPN_PCI_HI 0x2000
1077 #define SDR0_CP440_ERPN_PCI_LO 0x0000
1078 #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1079 #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1080 #define SDR0_CP440_NTO1_MASK 0x00000002
1081 #define SDR0_CP440_NTO1_NTOP 0x00000000
1082 #define SDR0_CP440_NTO1_NTO1 0x00000002
1083 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1084 #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
1086 #define SDR0_SDSTP0 0x0020
1087 #define SDR0_SDSTP0_ENG_MASK 0x80000000
1088 #define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
1089 #define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
1090 #define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1091 #define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1092 #define SDR0_SDSTP0_SRC_MASK 0x40000000
1093 #define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
1094 #define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
1095 #define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1096 #define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1097 #define SDR0_SDSTP0_SEL_MASK 0x38000000
1098 #define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
1099 #define SDR0_SDSTP0_SEL_CPU 0x08000000
1100 #define SDR0_SDSTP0_SEL_EBC 0x28000000
1101 #define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
1102 #define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
1103 #define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
1104 #define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
1105 #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
1106 #define SDR0_SDSTP0_FBDV_MASK 0x0001F000
1107 #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
1108 #define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
1109 #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
1110 #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
1111 #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
1112 #define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
1113 #define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
1114 #define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
1115 #define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
1116 #define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
1117 #define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
1118 #define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
1119 #define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
1120 #define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
1123 #define SDR0_SDSTP1 0x0021
1124 #define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
1125 #define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
1126 #define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
1127 #define SDR0_SDSTP1_PERDV0_MASK 0x03000000
1128 #define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1129 #define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
1130 #define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
1131 #define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
1132 #define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
1133 #define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
1134 #define SDR0_SDSTP1_DDR1_MODE 0x00100000
1135 #define SDR0_SDSTP1_DDR2_MODE 0x00200000
1136 #define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
1137 #define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
1138 #define SDR0_SDSTP1_ERPN_MASK 0x00080000
1139 #define SDR0_SDSTP1_ERPN_EBC 0x00000000
1140 #define SDR0_SDSTP1_ERPN_PCI 0x00080000
1141 #define SDR0_SDSTP1_PAE_MASK 0x00040000
1142 #define SDR0_SDSTP1_PAE_DISABLE 0x00000000
1143 #define SDR0_SDSTP1_PAE_ENABLE 0x00040000
1144 #define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
1145 #define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
1146 #define SDR0_SDSTP1_PHCE_MASK 0x00020000
1147 #define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
1148 #define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
1149 #define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
1150 #define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
1151 #define SDR0_SDSTP1_PISE_MASK 0x00010000
1152 #define SDR0_SDSTP1_PISE_DISABLE 0x00000000
1153 #define SDR0_SDSTP1_PISE_ENABLE 0x00001000
1154 #define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
1155 #define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
1156 #define SDR0_SDSTP1_PCWE_MASK 0x00008000
1157 #define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
1158 #define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
1159 #define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
1160 #define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
1161 #define SDR0_SDSTP1_PPIM_MASK 0x00007800
1162 #define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
1163 #define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
1164 #define SDR0_SDSTP1_PR64E_MASK 0x00000400
1165 #define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
1166 #define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
1167 #define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
1168 #define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
1169 #define SDR0_SDSTP1_PXFS_MASK 0x00000300
1170 #define SDR0_SDSTP1_PXFS_100_133 0x00000000
1171 #define SDR0_SDSTP1_PXFS_66_100 0x00000100
1172 #define SDR0_SDSTP1_PXFS_50_66 0x00000200
1173 #define SDR0_SDSTP1_PXFS_0_50 0x00000300
1174 #define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
1175 #define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
1176 #define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
1177 #define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
1178 #define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
1179 #define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
1180 #define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
1181 #define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
1182 #define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
1183 #define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
1184 #define SDR0_SDSTP1_ETH_MASK 0x00000004
1185 #define SDR0_SDSTP1_ETH_10_100 0x00000000
1186 #define SDR0_SDSTP1_ETH_GIGA 0x00000004
1187 #define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
1188 #define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
1189 #define SDR0_SDSTP1_NTO1_MASK 0x00000001
1190 #define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
1191 #define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
1192 #define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
1193 #define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
1195 #define SDR0_SDSTP2 0x0022
1196 #define SDR0_SDSTP2_P1AE_MASK 0x80000000
1197 #define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
1198 #define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
1199 #define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1200 #define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1201 #define SDR0_SDSTP2_P1HCE_MASK 0x40000000
1202 #define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
1203 #define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
1204 #define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1205 #define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1206 #define SDR0_SDSTP2_P1ISE_MASK 0x20000000
1207 #define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
1208 #define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
1209 #define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1210 #define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1211 #define SDR0_SDSTP2_P1CWE_MASK 0x10000000
1212 #define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
1213 #define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
1214 #define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1215 #define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1216 #define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
1217 #define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1218 #define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1219 #define SDR0_SDSTP2_P1R64E_MASK 0x00800000
1220 #define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
1221 #define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
1222 #define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1223 #define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1224 #define SDR0_SDSTP2_P1XFS_MASK 0x00600000
1225 #define SDR0_SDSTP2_P1XFS_100_133 0x00000000
1226 #define SDR0_SDSTP2_P1XFS_66_100 0x00200000
1227 #define SDR0_SDSTP2_P1XFS_50_66 0x00400000
1228 #define SDR0_SDSTP2_P1XFS_0_50 0x00600000
1229 #define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1230 #define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1231 #define SDR0_SDSTP2_P2AE_MASK 0x00040000
1232 #define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
1233 #define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
1234 #define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
1235 #define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
1236 #define SDR0_SDSTP2_P2HCE_MASK 0x00020000
1237 #define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
1238 #define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
1239 #define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
1240 #define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
1241 #define SDR0_SDSTP2_P2ISE_MASK 0x00010000
1242 #define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
1243 #define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
1244 #define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
1245 #define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
1246 #define SDR0_SDSTP2_P2CWE_MASK 0x00008000
1247 #define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
1248 #define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
1249 #define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
1250 #define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
1251 #define SDR0_SDSTP2_P2PIM_MASK 0x00007800
1252 #define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
1253 #define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
1254 #define SDR0_SDSTP2_P2XFS_MASK 0x00000300
1255 #define SDR0_SDSTP2_P2XFS_100_133 0x00000000
1256 #define SDR0_SDSTP2_P2XFS_66_100 0x00000100
1257 #define SDR0_SDSTP2_P2XFS_50_66 0x00000200
1258 #define SDR0_SDSTP2_P2XFS_0_50 0x00000100
1259 #define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
1260 #define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
1262 #define SDR0_SDSTP3 0x0023
1264 #define SDR0_PINSTP 0x0040
1265 #define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
1266 #define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
1267 #define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
1268 #define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
1269 #define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
1270 #define SDR0_SDCS 0x0060
1271 #define SDR0_ECID0 0x0080
1272 #define SDR0_ECID1 0x0081
1273 #define SDR0_ECID2 0x0082
1274 #define SDR0_JTAG 0x00C0
1276 #define SDR0_DDR0 0x00E1
1277 #define SDR0_DDR0_DPLLRST 0x80000000
1278 #define SDR0_DDR0_DDRM_MASK 0x60000000
1279 #define SDR0_DDR0_DDRM_DDR1 0x20000000
1280 #define SDR0_DDR0_DDRM_DDR2 0x40000000
1281 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
1282 #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
1283 #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
1284 #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
1286 #define SDR0_UART0 0x0120
1287 #define SDR0_UART1 0x0121
1288 #define SDR0_UART2 0x0122
1289 #define SDR0_UARTX_UXICS_MASK 0xF0000000
1290 #define SDR0_UARTX_UXICS_PLB 0x20000000
1291 #define SDR0_UARTX_UXEC_MASK 0x00800000
1292 #define SDR0_UARTX_UXEC_INT 0x00000000
1293 #define SDR0_UARTX_UXEC_EXT 0x00800000
1294 #define SDR0_UARTX_UXDIV_MASK 0x000000FF
1295 #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
1296 #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
1298 #define SDR0_CP440 0x0180
1299 #define SDR0_CP440_ERPN_MASK 0x30000000
1300 #define SDR0_CP440_ERPN_MASK_HI 0x3000
1301 #define SDR0_CP440_ERPN_MASK_LO 0x0000
1302 #define SDR0_CP440_ERPN_EBC 0x10000000
1303 #define SDR0_CP440_ERPN_EBC_HI 0x1000
1304 #define SDR0_CP440_ERPN_EBC_LO 0x0000
1305 #define SDR0_CP440_ERPN_PCI 0x20000000
1306 #define SDR0_CP440_ERPN_PCI_HI 0x2000
1307 #define SDR0_CP440_ERPN_PCI_LO 0x0000
1308 #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1309 #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1310 #define SDR0_CP440_NTO1_MASK 0x00000002
1311 #define SDR0_CP440_NTO1_NTOP 0x00000000
1312 #define SDR0_CP440_NTO1_NTO1 0x00000002
1313 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1314 #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
1316 #define SDR0_XCR0 0x01C0
1317 #define SDR0_XCR1 0x01C3
1318 #define SDR0_XCR2 0x01C6
1319 #define SDR0_XCRn_PAE_MASK 0x80000000
1320 #define SDR0_XCRn_PAE_DISABLE 0x00000000
1321 #define SDR0_XCRn_PAE_ENABLE 0x80000000
1322 #define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1323 #define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1324 #define SDR0_XCRn_PHCE_MASK 0x40000000
1325 #define SDR0_XCRn_PHCE_DISABLE 0x00000000
1326 #define SDR0_XCRn_PHCE_ENABLE 0x40000000
1327 #define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1328 #define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1329 #define SDR0_XCRn_PISE_MASK 0x20000000
1330 #define SDR0_XCRn_PISE_DISABLE 0x00000000
1331 #define SDR0_XCRn_PISE_ENABLE 0x20000000
1332 #define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1333 #define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1334 #define SDR0_XCRn_PCWE_MASK 0x10000000
1335 #define SDR0_XCRn_PCWE_DISABLE 0x00000000
1336 #define SDR0_XCRn_PCWE_ENABLE 0x10000000
1337 #define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1338 #define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1339 #define SDR0_XCRn_PPIM_MASK 0x0F000000
1340 #define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1341 #define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1342 #define SDR0_XCRn_PR64E_MASK 0x00800000
1343 #define SDR0_XCRn_PR64E_DISABLE 0x00000000
1344 #define SDR0_XCRn_PR64E_ENABLE 0x00800000
1345 #define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1346 #define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1347 #define SDR0_XCRn_PXFS_MASK 0x00600000
1348 #define SDR0_XCRn_PXFS_100_133 0x00000000
1349 #define SDR0_XCRn_PXFS_66_100 0x00200000
1350 #define SDR0_XCRn_PXFS_50_66 0x00400000
1351 #define SDR0_XCRn_PXFS_0_33 0x00600000
1352 #define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1353 #define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1355 #define SDR0_XPLLC0 0x01C1
1356 #define SDR0_XPLLD0 0x01C2
1357 #define SDR0_XPLLC1 0x01C4
1358 #define SDR0_XPLLD1 0x01C5
1359 #define SDR0_XPLLC2 0x01C7
1360 #define SDR0_XPLLD2 0x01C8
1361 #define SDR0_SRST 0x0200
1362 #define SDR0_SLPIPE 0x0220
1364 #define SDR0_AMP0 0x0240
1365 #define SDR0_AMP0_PRIORITY 0xFFFF0000
1366 #define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
1367 #define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
1369 #define SDR0_AMP1 0x0241
1370 #define SDR0_AMP1_PRIORITY 0xFC000000
1371 #define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
1372 #define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
1374 #define SDR0_MIRQ0 0x0260
1375 #define SDR0_MIRQ1 0x0261
1376 #define SDR0_MALTBL 0x0280
1377 #define SDR0_MALRBL 0x02A0
1378 #define SDR0_MALTBS 0x02C0
1379 #define SDR0_MALRBS 0x02E0
1381 /* Reserved for Customer Use */
1382 #define SDR0_CUST0 0x4000
1383 #define SDR0_CUST0_AUTONEG_MASK 0x8000000
1384 #define SDR0_CUST0_NO_AUTONEG 0x0000000
1385 #define SDR0_CUST0_AUTONEG 0x8000000
1386 #define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
1387 #define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
1388 #define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
1389 #define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
1390 #define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
1391 #define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
1392 #define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
1394 #define SDR0_SDSTP4 0x4001
1395 #define SDR0_CUST1 0x4002
1396 #define SDR0_SDSTP5 0x4003
1397 #define SDR0_CUST2 0x4004
1398 #define SDR0_SDSTP6 0x4005
1399 #define SDR0_CUST3 0x4006
1400 #define SDR0_SDSTP7 0x4007
1402 #define SDR0_PFC0 0x4100
1403 #define SDR0_PFC0_GPIO_0 0x80000000
1404 #define SDR0_PFC0_PCIX0REQ2_N 0x00000000
1405 #define SDR0_PFC0_GPIO_1 0x40000000
1406 #define SDR0_PFC0_PCIX0REQ3_N 0x00000000
1407 #define SDR0_PFC0_GPIO_2 0x20000000
1408 #define SDR0_PFC0_PCIX0GNT2_N 0x00000000
1409 #define SDR0_PFC0_GPIO_3 0x10000000
1410 #define SDR0_PFC0_PCIX0GNT3_N 0x00000000
1411 #define SDR0_PFC0_GPIO_4 0x08000000
1412 #define SDR0_PFC0_PCIX1REQ2_N 0x00000000
1413 #define SDR0_PFC0_GPIO_5 0x04000000
1414 #define SDR0_PFC0_PCIX1REQ3_N 0x00000000
1415 #define SDR0_PFC0_GPIO_6 0x02000000
1416 #define SDR0_PFC0_PCIX1GNT2_N 0x00000000
1417 #define SDR0_PFC0_GPIO_7 0x01000000
1418 #define SDR0_PFC0_PCIX1GNT3_N 0x00000000
1419 #define SDR0_PFC0_GPIO_8 0x00800000
1420 #define SDR0_PFC0_PERREADY 0x00000000
1421 #define SDR0_PFC0_GPIO_9 0x00400000
1422 #define SDR0_PFC0_PERCS1_N 0x00000000
1423 #define SDR0_PFC0_GPIO_10 0x00200000
1424 #define SDR0_PFC0_PERCS2_N 0x00000000
1425 #define SDR0_PFC0_GPIO_11 0x00100000
1426 #define SDR0_PFC0_IRQ0 0x00000000
1427 #define SDR0_PFC0_GPIO_12 0x00080000
1428 #define SDR0_PFC0_IRQ1 0x00000000
1429 #define SDR0_PFC0_GPIO_13 0x00040000
1430 #define SDR0_PFC0_IRQ2 0x00000000
1431 #define SDR0_PFC0_GPIO_14 0x00020000
1432 #define SDR0_PFC0_IRQ3 0x00000000
1433 #define SDR0_PFC0_GPIO_15 0x00010000
1434 #define SDR0_PFC0_IRQ4 0x00000000
1435 #define SDR0_PFC0_GPIO_16 0x00008000
1436 #define SDR0_PFC0_IRQ5 0x00000000
1437 #define SDR0_PFC0_GPIO_17 0x00004000
1438 #define SDR0_PFC0_PERBE0_N 0x00000000
1439 #define SDR0_PFC0_GPIO_18 0x00002000
1440 #define SDR0_PFC0_PCI0GNT0_N 0x00000000
1441 #define SDR0_PFC0_GPIO_19 0x00001000
1442 #define SDR0_PFC0_PCI0GNT1_N 0x00000000
1443 #define SDR0_PFC0_GPIO_20 0x00000800
1444 #define SDR0_PFC0_PCI0REQ0_N 0x00000000
1445 #define SDR0_PFC0_GPIO_21 0x00000400
1446 #define SDR0_PFC0_PCI0REQ1_N 0x00000000
1447 #define SDR0_PFC0_GPIO_22 0x00000200
1448 #define SDR0_PFC0_PCI1GNT0_N 0x00000000
1449 #define SDR0_PFC0_GPIO_23 0x00000100
1450 #define SDR0_PFC0_PCI1GNT1_N 0x00000000
1451 #define SDR0_PFC0_GPIO_24 0x00000080
1452 #define SDR0_PFC0_PCI1REQ0_N 0x00000000
1453 #define SDR0_PFC0_GPIO_25 0x00000040
1454 #define SDR0_PFC0_PCI1REQ1_N 0x00000000
1455 #define SDR0_PFC0_GPIO_26 0x00000020
1456 #define SDR0_PFC0_PCI2GNT0_N 0x00000000
1457 #define SDR0_PFC0_GPIO_27 0x00000010
1458 #define SDR0_PFC0_PCI2GNT1_N 0x00000000
1459 #define SDR0_PFC0_GPIO_28 0x00000008
1460 #define SDR0_PFC0_PCI2REQ0_N 0x00000000
1461 #define SDR0_PFC0_GPIO_29 0x00000004
1462 #define SDR0_PFC0_PCI2REQ1_N 0x00000000
1463 #define SDR0_PFC0_GPIO_30 0x00000002
1464 #define SDR0_PFC0_UART1RX 0x00000000
1465 #define SDR0_PFC0_GPIO_31 0x00000001
1466 #define SDR0_PFC0_UART1TX 0x00000000
1468 #define SDR0_PFC1 0x4101
1469 #define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
1470 #define SDR0_PFC1_UART1_DSR_DTR 0x00000000
1471 #define SDR0_PFC1_UART1_CTS_RTS 0x02000000
1472 #define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
1473 #define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
1474 #define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
1475 #define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
1476 #define SDR0_PFC1_ETH_10_100 0x00000000
1477 #define SDR0_PFC1_ETH_GIGA 0x00200000
1478 #define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
1479 #define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
1480 #define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
1481 #define SDR0_PFC1_CPU_NO_TRACE 0x00000000
1482 #define SDR0_PFC1_CPU_TRACE 0x00080000
1483 #define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
1484 #define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
1486 #define SDR0_MFR 0x4300
1487 #endif /* CONFIG_440SPE */
1489 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1490 /* Pin Function Control Register 0 (SDR0_PFC0) */
1491 #define SDR0_PFC0 0x4100
1492 #define SDR0_PFC0_DBG 0x00008000 /* debug enable */
1493 #define SDR0_PFC0_G49E 0x00004000 /* GPIO 49 enable */
1494 #define SDR0_PFC0_G50E 0x00002000 /* GPIO 50 enable */
1495 #define SDR0_PFC0_G51E 0x00001000 /* GPIO 51 enable */
1496 #define SDR0_PFC0_G52E 0x00000800 /* GPIO 52 enable */
1497 #define SDR0_PFC0_G53E 0x00000400 /* GPIO 53 enable */
1498 #define SDR0_PFC0_G54E 0x00000200 /* GPIO 54 enable */
1499 #define SDR0_PFC0_G55E 0x00000100 /* GPIO 55 enable */
1500 #define SDR0_PFC0_G56E 0x00000080 /* GPIO 56 enable */
1501 #define SDR0_PFC0_G57E 0x00000040 /* GPIO 57 enable */
1502 #define SDR0_PFC0_G58E 0x00000020 /* GPIO 58 enable */
1503 #define SDR0_PFC0_G59E 0x00000010 /* GPIO 59 enable */
1504 #define SDR0_PFC0_G60E 0x00000008 /* GPIO 60 enable */
1505 #define SDR0_PFC0_G61E 0x00000004 /* GPIO 61 enable */
1506 #define SDR0_PFC0_G62E 0x00000002 /* GPIO 62 enable */
1507 #define SDR0_PFC0_G63E 0x00000001 /* GPIO 63 enable */
1509 /* Pin Function Control Register 1 (SDR0_PFC1) */
1510 #define SDR0_PFC1 0x4101
1511 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1512 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1513 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1514 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1515 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1516 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1517 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1518 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins*/
1519 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins*/
1520 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1521 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1522 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1524 /* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
1525 #define SDR0_ETH_PLL 0x4102
1526 #define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/
1527 #define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000 /* Ethernet reference clock */
1528 #define SDR0_ETH_PLL_BYPASS 0x08000000 /* bypass mode enable */
1529 #define SDR0_ETH_PLL_STOPCLK 0x04000000 /* output clock disable */
1530 #define SDR0_ETH_PLL_TUNE_MASK 0x03FF0000 /* loop stability tuning bits */
1531 #define SDR0_ETH_PLL_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3ff)<<16)
1532 #define SDR0_ETH_PLL_MULTI_MASK 0x0000FF00 /* frequency multiplication */
1533 #define SDR0_ETH_PLL_MULTI_ENCODE(n) ((((unsigned long)(n))&0xff)<<8)
1534 #define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0 /* PLLOUTB/C frequency */
1535 #define SDR0_ETH_PLL_RANGEB_ENCODE(n) ((((unsigned long)(n))&0x0f)<<4)
1536 #define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F /* PLLOUTA frequency */
1537 #define SDR0_ETH_PLL_RANGEA_ENCODE(n) (((unsigned long)(n))&0x0f)
1539 /* Ethernet Configuration Register (SDR0_ETH_CFG) */
1540 #define SDR0_ETH_CFG 0x4103
1541 #define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */
1542 #define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */
1543 #define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */
1544 #define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */
1545 #define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */
1546 #define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */
1547 #define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */
1548 #define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */
1549 #define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */
1550 #define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */
1551 #define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */
1552 #define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */
1553 #define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */
1554 #define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */
1555 #define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */
1556 #define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */
1557 #define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */
1558 #define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */
1559 #define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */
1560 #define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */
1561 #define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */
1562 #define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */
1563 #define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */
1564 #define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */
1565 #define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */
1566 #define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */
1567 #define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */
1568 #define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */
1570 #define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4
1571 #define SDR0_ETH_CFG_ZMII_MII_MODE 0x00
1572 #define SDR0_ETH_CFG_ZMII_SMII_MODE 0x01
1573 #define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10
1574 #define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11
1576 /* Miscealleneaous Function Reg. (SDR0_MFR) */
1577 #define SDR0_MFR 0x4300
1578 #define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */
1579 #define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */
1580 #define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */
1581 #define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */
1582 #define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */
1583 #define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */
1584 #define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */
1585 #define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */
1586 #define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */
1587 #define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */
1588 #define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */
1589 #define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */
1590 #define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */
1591 #define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */
1592 #define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */
1593 #define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */
1594 #define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */
1595 #define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */
1596 #define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */
1597 #define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */
1599 /* EMACx TX Status Register (SDR0_EMACxTXST)*/
1600 #define SDR0_EMAC0TXST 0x4400
1601 #define SDR0_EMAC1TXST 0x4401
1602 #define SDR0_EMAC2TXST 0x4402
1603 #define SDR0_EMAC3TXST 0x4403
1605 #define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */
1606 #define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */
1607 #define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */
1608 #define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */
1609 #define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */
1610 #define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */
1611 #define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */
1612 #define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */
1613 #define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
1614 #define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */
1615 #define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */
1616 #define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */
1617 #define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */
1618 #define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */
1619 #define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */
1620 #define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */
1621 #define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */
1622 #define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */
1623 #define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */
1624 #define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */
1625 #define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */
1626 #define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */
1627 #define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */
1628 #define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */
1630 /* EMACx RX Status Register (SDR0_EMACxRXST)*/
1631 #define SDR0_EMAC0RXST 0x4404
1632 #define SDR0_EMAC1RXST 0x4405
1633 #define SDR0_EMAC2RXST 0x4406
1634 #define SDR0_EMAC3RXST 0x4407
1636 #define SDR0_EMACxRXST_FOR 0x20000000 /* RX FIFO overrun */
1637 #define SDR0_EMACxRXST_BC 0x10000000 /* broadcast address */
1638 #define SDR0_EMACxRXST_MC 0x08000000 /* multicast address */
1639 #define SDR0_EMACxRXST_UC 0x04000000 /* unicast address */
1640 #define SDR0_EMACxRXST_UPR_MASK 0x03800000 /* user priority field */
1641 #define SDR0_EMACxRXST_UPR_ENCODE(n) ((((unsigned long)(n))&0x07)<<23)
1642 #define SDR0_EMACxRXST_VLAN 0x00400000 /* RX VLAN tagged frame */
1643 #define SDR0_EMACxRXST_LOOP 0x00200000 /* received in loop-back mode */
1644 #define SDR0_EMACxRXST_UOP 0x00100000 /* RX unsupported opcode */
1645 #define SDR0_EMACxRXST_CPF 0x00080000 /* RX control pause frame */
1646 #define SDR0_EMACxRXST_CF 0x00040000 /* RX control frame*/
1647 #define SDR0_EMACxRXST_MSIZ 0x00020000 /* 1024-MaxSize bytes recieved*/
1648 #define SDR0_EMACxRXST_1023 0x00010000 /* 512-1023 bytes received */
1649 #define SDR0_EMACxRXST_511 0x00008000 /* 128-511 bytes received */
1650 #define SDR0_EMACxRXST_255 0x00004000 /* 128-255 bytes received */
1651 #define SDR0_EMACxRXST_127 0x00002000 /* 65-127 bytes received */
1652 #define SDR0_EMACxRXST_64 0x00001000 /* 64 bytes received */
1653 #define SDR0_EMACxRXST_RUNT 0x00000800 /* runt frame */
1654 #define SDR0_EMACxRXST_SEVT 0x00000400 /* short event */
1655 #define SDR0_EMACxRXST_AERR 0x00000200 /* alignment error */
1656 #define SDR0_EMACxRXST_SERR 0x00000100 /* received with symbol error */
1657 #define SDR0_EMACxRXST_BURST 0x00000040 /* received burst */
1658 #define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */
1659 #define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */
1660 #define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */
1661 #define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */
1662 #define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */
1663 #define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */
1665 /* EMACx TX Status Register (SDR0_EMACxREJCNT)*/
1666 #define SDR0_EMAC0REJCNT 0x4408
1667 #define SDR0_EMAC1REJCNT 0x4409
1668 #define SDR0_EMAC2REJCNT 0x440A
1669 #define SDR0_EMAC3REJCNT 0x440B
1671 #define SDR0_DDR0 0x00E1
1672 #define SDR0_DDR0_DPLLRST 0x80000000
1673 #define SDR0_DDR0_DDRM_MASK 0x60000000
1674 #define SDR0_DDR0_DDRM_DDR1 0x20000000
1675 #define SDR0_DDR0_DDRM_DDR2 0x40000000
1676 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
1677 #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
1678 #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
1679 #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
1681 #define AHB_TOP 0xA4
1682 #define AHB_BOT 0xA5
1683 #define SDR0_AHB_CFG 0x370
1684 #define SDR0_USB2HOST_CFG 0x371
1685 #endif /* CONFIG_460EX || CONFIG_460GT */
1687 #define SDR0_SDCS_SDD (0x80000000 >> 31)
1689 #if defined(CONFIG_440GP)
1690 #define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
1691 #define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
1692 #endif /* defined(CONFIG_440GP) */
1693 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
1694 #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
1695 #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
1696 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
1697 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1698 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1699 #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
1700 #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
1701 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
1703 #define SDR0_UARTX_UXICS_MASK 0xF0000000
1704 #define SDR0_UARTX_UXICS_PLB 0x20000000
1705 #define SDR0_UARTX_UXEC_MASK 0x00800000
1706 #define SDR0_UARTX_UXEC_INT 0x00000000
1707 #define SDR0_UARTX_UXEC_EXT 0x00800000
1708 #define SDR0_UARTX_UXDTE_MASK 0x00400000
1709 #define SDR0_UARTX_UXDTE_DISABLE 0x00000000
1710 #define SDR0_UARTX_UXDTE_ENABLE 0x00400000
1711 #define SDR0_UARTX_UXDRE_MASK 0x00200000
1712 #define SDR0_UARTX_UXDRE_DISABLE 0x00000000
1713 #define SDR0_UARTX_UXDRE_ENABLE 0x00200000
1714 #define SDR0_UARTX_UXDC_MASK 0x00100000
1715 #define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000
1716 #define SDR0_UARTX_UXDC_CLEARED 0x00100000
1717 #define SDR0_UARTX_UXDIV_MASK 0x000000FF
1718 #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
1719 #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
1721 #define SDR0_CPU440_EARV_MASK 0x30000000
1722 #define SDR0_CPU440_EARV_EBC 0x10000000
1723 #define SDR0_CPU440_EARV_PCI 0x20000000
1724 #define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1725 #define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1726 #define SDR0_CPU440_NTO1_MASK 0x00000002
1727 #define SDR0_CPU440_NTO1_NTOP 0x00000000
1728 #define SDR0_CPU440_NTO1_NTO1 0x00000002
1729 #define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1730 #define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
1732 #define SDR0_XCR_PAE_MASK 0x80000000
1733 #define SDR0_XCR_PAE_DISABLE 0x00000000
1734 #define SDR0_XCR_PAE_ENABLE 0x80000000
1735 #define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1736 #define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1737 #define SDR0_XCR_PHCE_MASK 0x40000000
1738 #define SDR0_XCR_PHCE_DISABLE 0x00000000
1739 #define SDR0_XCR_PHCE_ENABLE 0x40000000
1740 #define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1741 #define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1742 #define SDR0_XCR_PISE_MASK 0x20000000
1743 #define SDR0_XCR_PISE_DISABLE 0x00000000
1744 #define SDR0_XCR_PISE_ENABLE 0x20000000
1745 #define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1746 #define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1747 #define SDR0_XCR_PCWE_MASK 0x10000000
1748 #define SDR0_XCR_PCWE_DISABLE 0x00000000
1749 #define SDR0_XCR_PCWE_ENABLE 0x10000000
1750 #define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
1751 #define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
1752 #define SDR0_XCR_PPIM_MASK 0x0F000000
1753 #define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
1754 #define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1755 #define SDR0_XCR_PR64E_MASK 0x00800000
1756 #define SDR0_XCR_PR64E_DISABLE 0x00000000
1757 #define SDR0_XCR_PR64E_ENABLE 0x00800000
1758 #define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
1759 #define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
1760 #define SDR0_XCR_PXFS_MASK 0x00600000
1761 #define SDR0_XCR_PXFS_HIGH 0x00000000
1762 #define SDR0_XCR_PXFS_MED 0x00200000
1763 #define SDR0_XCR_PXFS_LOW 0x00400000
1764 #define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
1765 #define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
1766 #define SDR0_XCR_PDM_MASK 0x00000040
1767 #define SDR0_XCR_PDM_MULTIPOINT 0x00000000
1768 #define SDR0_XCR_PDM_P2P 0x00000040
1769 #define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19)
1770 #define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01)
1772 #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
1773 #define SDR0_PFC0_GEIE_MASK 0x00003E00
1774 #define SDR0_PFC0_GEIE_TRE 0x00003E00
1775 #define SDR0_PFC0_GEIE_NOTRE 0x00000000
1776 #define SDR0_PFC0_TRE_MASK 0x00000100
1777 #define SDR0_PFC0_TRE_DISABLE 0x00000000
1778 #define SDR0_PFC0_TRE_ENABLE 0x00000100
1779 #define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
1780 #define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
1782 #define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
1783 #define SDR0_PFC1_EPS_MASK 0x01C00000
1784 #define SDR0_PFC1_EPS_GROUP0 0x00000000
1785 #define SDR0_PFC1_EPS_GROUP1 0x00400000
1786 #define SDR0_PFC1_EPS_GROUP2 0x00800000
1787 #define SDR0_PFC1_EPS_GROUP3 0x00C00000
1788 #define SDR0_PFC1_EPS_GROUP4 0x01000000
1789 #define SDR0_PFC1_EPS_GROUP5 0x01400000
1790 #define SDR0_PFC1_EPS_GROUP6 0x01800000
1791 #define SDR0_PFC1_EPS_GROUP7 0x01C00000
1792 #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1793 #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1794 #define SDR0_PFC1_RMII_MASK 0x00200000
1795 #define SDR0_PFC1_RMII_100MBIT 0x00000000
1796 #define SDR0_PFC1_RMII_10MBIT 0x00200000
1797 #define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21)
1798 #define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
1799 #define SDR0_PFC1_CTEMS_MASK 0x00100000
1800 #define SDR0_PFC1_CTEMS_EMS 0x00000000
1801 #define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000
1803 #define SDR0_MFR_TAH0_MASK 0x80000000
1804 #define SDR0_MFR_TAH0_ENABLE 0x00000000
1805 #define SDR0_MFR_TAH0_DISABLE 0x80000000
1806 #define SDR0_MFR_TAH1_MASK 0x40000000
1807 #define SDR0_MFR_TAH1_ENABLE 0x00000000
1808 #define SDR0_MFR_TAH1_DISABLE 0x40000000
1809 #define SDR0_MFR_PCM_MASK 0x20000000
1810 #define SDR0_MFR_PCM_PPC440GX 0x00000000
1811 #define SDR0_MFR_PCM_PPC440GP 0x20000000
1812 #define SDR0_MFR_ECS_MASK 0x10000000
1813 #define SDR0_MFR_ECS_INTERNAL 0x10000000
1815 #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
1816 #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
1817 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1818 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1819 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1820 #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
1821 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
1822 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1823 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1824 #define SDR0_MFR_ERRATA3_EN0 0x00800000
1825 #define SDR0_MFR_ERRATA3_EN1 0x00400000
1826 #if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
1827 #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
1828 #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1829 #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
1830 #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
1831 #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
1834 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1835 #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
1836 #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
1837 #define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29)
1838 #define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07)
1841 #define SDR0_MFR_ECS_MASK 0x10000000
1842 #define SDR0_MFR_ECS_INTERNAL 0x10000000
1844 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1845 #define SDR0_SRST0 0x200
1846 #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
1847 #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
1848 #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
1849 #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
1850 #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
1851 #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
1852 #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
1853 #define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
1854 #define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
1855 #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
1856 #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
1857 #define SDR0_SRST0_PCI 0x00100000 /* PCI */
1858 #define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
1859 #define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
1860 #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
1861 #define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
1862 #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
1863 #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
1864 #define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
1865 #define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
1866 #define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
1867 #define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
1868 #define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
1869 #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
1870 #define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
1871 #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
1872 #define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
1873 #define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
1874 #define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
1875 #define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
1876 #define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
1878 #define SDR0_SRST1 0x201
1879 #define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
1880 #define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
1881 #define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
1882 #define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
1883 #define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
1884 #define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
1885 #define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
1886 #define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
1887 #define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
1888 #define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
1889 #define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
1890 #define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
1891 #define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
1892 #define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
1893 #define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
1894 #define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
1895 #define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
1896 #define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
1897 #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
1898 #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
1900 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1902 #define SDR0_SRST0 0x0200
1903 #define SDR0_SRST SDR0_SRST0 /* for compatability reasons */
1904 #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
1905 #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
1906 #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
1907 #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
1908 #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
1909 #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
1910 #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
1911 #define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */
1912 #define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */
1913 #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
1914 #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
1915 #define SDR0_SRST0_PCI 0x00100000 /* PCI */
1916 #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
1917 #define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */
1918 #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/
1919 #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/
1920 #define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/
1921 #define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/
1922 #define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/
1923 #define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/
1924 #define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */
1925 #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
1926 #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
1927 #define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */
1928 #define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */
1929 #define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */
1931 #define SDR0_SRST1 0x201
1932 #define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */
1933 #define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */
1934 #define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */
1935 #define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */
1936 #define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */
1937 #define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */
1938 #define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */
1939 #define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */
1940 #define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */
1941 #define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */
1942 #define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */
1943 #define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */
1944 #define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */
1945 #define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */
1946 #define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */
1947 #define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */
1948 #define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */
1949 #define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */
1950 #define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */
1951 #define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */
1952 #define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */
1953 #define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */
1954 #define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */
1955 #define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */
1956 #define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */
1957 #define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
1958 #define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */
1959 #define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */
1960 #define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */
1961 #define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */
1962 #define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */
1963 #define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */
1965 #define SDR0_PCI0 0x1c0 /* PCI Configuration Register */
1969 #define SDR0_SRST_BGO 0x80000000
1970 #define SDR0_SRST_PLB 0x40000000
1971 #define SDR0_SRST_EBC 0x20000000
1972 #define SDR0_SRST_OPB 0x10000000
1973 #define SDR0_SRST_UART0 0x08000000
1974 #define SDR0_SRST_UART1 0x04000000
1975 #define SDR0_SRST_IIC0 0x02000000
1976 #define SDR0_SRST_IIC1 0x01000000
1977 #define SDR0_SRST_GPIO 0x00800000
1978 #define SDR0_SRST_GPT 0x00400000
1979 #define SDR0_SRST_DMC 0x00200000
1980 #define SDR0_SRST_PCI 0x00100000
1981 #define SDR0_SRST_EMAC0 0x00080000
1982 #define SDR0_SRST_EMAC1 0x00040000
1983 #define SDR0_SRST_CPM 0x00020000
1984 #define SDR0_SRST_IMU 0x00010000
1985 #define SDR0_SRST_UIC01 0x00008000
1986 #define SDR0_SRST_UICB2 0x00004000
1987 #define SDR0_SRST_SRAM 0x00002000
1988 #define SDR0_SRST_EBM 0x00001000
1989 #define SDR0_SRST_BGI 0x00000800
1990 #define SDR0_SRST_DMA 0x00000400
1991 #define SDR0_SRST_DMAC 0x00000200
1992 #define SDR0_SRST_MAL 0x00000100
1993 #define SDR0_SRST_ZMII 0x00000080
1994 #define SDR0_SRST_GPTR 0x00000040
1995 #define SDR0_SRST_PPM 0x00000020
1996 #define SDR0_SRST_EMAC2 0x00000010
1997 #define SDR0_SRST_EMAC3 0x00000008
1998 #define SDR0_SRST_RGMII 0x00000001
2002 /*-----------------------------------------------------------------------------+
2004 +-----------------------------------------------------------------------------*/
2005 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2006 defined(CONFIG_460SX)
2007 #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
2008 #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
2009 #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
2010 #define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
2011 #define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
2012 #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
2013 #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
2014 #elif !defined (CONFIG_440GX) && \
2015 !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
2016 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
2017 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
2018 #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
2019 #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
2020 #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
2021 #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
2022 #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
2023 #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
2024 #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
2025 #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
2026 #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
2027 #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
2028 #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
2029 #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
2031 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
2032 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
2033 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
2034 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
2035 #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
2036 #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
2037 #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
2038 #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
2039 #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
2040 #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
2041 #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
2042 #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
2043 #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
2044 #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
2046 #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
2047 #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
2048 #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
2049 #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
2050 #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
2051 #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
2053 #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
2054 #define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
2055 #define PRADV_MASK 0x07000000 /* Primary Divisor A */
2056 #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
2057 #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
2059 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
2060 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
2061 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
2062 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
2064 /* Strap 1 Register */
2065 #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
2066 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
2067 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
2068 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
2069 #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
2070 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
2071 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
2072 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
2073 #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
2074 #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
2075 #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
2076 #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
2077 #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
2078 #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
2079 #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
2080 #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
2081 #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
2082 #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
2083 #endif /* CONFIG_440GX */
2085 #if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
2086 /*--------------------------------------*/
2087 #define CPR0_PLLC 0x40
2088 #define CPR0_PLLC_RST_MASK 0x80000000
2089 #define CPR0_PLLC_RST_PLLLOCKED 0x00000000
2090 #define CPR0_PLLC_RST_PLLRESET 0x80000000
2091 #define CPR0_PLLC_ENG_MASK 0x40000000
2092 #define CPR0_PLLC_ENG_DISABLE 0x00000000
2093 #define CPR0_PLLC_ENG_ENABLE 0x40000000
2094 #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2095 #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2096 #define CPR0_PLLC_SRC_MASK 0x20000000
2097 #define CPR0_PLLC_SRC_PLLOUTA 0x00000000
2098 #define CPR0_PLLC_SRC_PLLOUTB 0x20000000
2099 #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2100 #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2101 #define CPR0_PLLC_SEL_MASK 0x07000000
2102 #define CPR0_PLLC_SEL_PLL 0x00000000
2103 #define CPR0_PLLC_SEL_CPU 0x01000000
2104 #define CPR0_PLLC_SEL_PER 0x05000000
2105 #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2106 #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
2107 #define CPR0_PLLC_TUNE_MASK 0x000003FF
2108 #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
2109 #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
2110 /*--------------------------------------*/
2111 #define CPR0_PLLD 0x60
2112 #define CPR0_PLLD_FBDV_MASK 0x1F000000
2113 #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
2114 #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
2115 #define CPR0_PLLD_FWDVA_MASK 0x000F0000
2116 #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
2117 #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
2118 #define CPR0_PLLD_FWDVB_MASK 0x00000700
2119 #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
2120 #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
2121 #define CPR0_PLLD_LFBDV_MASK 0x0000003F
2122 #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
2123 #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
2124 /*--------------------------------------*/
2125 #define CPR0_PRIMAD 0x80
2126 #define CPR0_PRIMAD_PRADV0_MASK 0x07000000
2127 #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2128 #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
2129 /*--------------------------------------*/
2130 #define CPR0_PRIMBD 0xA0
2131 #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
2132 #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2133 #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
2134 /*--------------------------------------*/
2136 #define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */
2137 #define CPR0_CPM0_FR 0xB1 /* CPM Force Register */
2138 #define CPR0_CPM0_SR 0xB2 /* CPM Status Register */
2139 #define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */
2140 #define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */
2141 #define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */
2142 #define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */
2143 #define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */
2144 #define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */
2145 #define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */
2146 #define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */
2147 #define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */
2148 #define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */
2149 #define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */
2150 #define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
2151 #define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
2152 #define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */
2153 #define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */
2154 #define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */
2155 #define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */
2156 #define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */
2157 #define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */
2158 #define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */
2159 #define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */
2160 #define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */
2161 #define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */
2162 #define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */
2163 #define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */
2164 #define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */
2165 #define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */
2166 #define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */
2167 #define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */
2168 #define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */
2169 #define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */
2171 /*--------------------------------------*/
2172 #define CPR0_OPBD 0xC0
2173 #define CPR0_OPBD_OPBDV0_MASK 0x03000000
2174 #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
2175 #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
2176 /*--------------------------------------*/
2177 #define CPR0_PERD 0xE0
2178 #define CPR0_PERD_PERDV0_MASK 0x07000000
2179 #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2180 #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
2181 /*--------------------------------------*/
2182 #define CPR0_MALD 0x100
2183 #define CPR0_MALD_MALDV0_MASK 0x03000000
2184 #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
2185 #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
2186 /*--------------------------------------*/
2187 #define CPR0_SPCID 0x120
2188 #define CPR0_SPCID_SPCIDV0_MASK 0x03000000
2189 #define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
2190 #define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
2191 /*--------------------------------------*/
2192 #define CPR0_ICFG 0x140
2193 #define CPR0_ICFG_RLI_MASK 0x80000000
2194 #define CPR0_ICFG_RLI_RESETCPR 0x00000000
2195 #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
2196 #define CPR0_ICFG_ICS_MASK 0x00000007
2197 #endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
2199 /*-----------------------------------------------------------------------------
2200 | IIC Register Offsets
2201 '----------------------------------------------------------------------------*/
2202 #define IICMDBUF 0x00
2203 #define IICSDBUF 0x02
2204 #define IICLMADR 0x04
2205 #define IICHMADR 0x05
2206 #define IICCNTL 0x06
2207 #define IICMDCNTL 0x07
2209 #define IICEXTSTS 0x09
2210 #define IICLSADR 0x0A
2211 #define IICHSADR 0x0B
2212 #define IICCLKDIV 0x0C
2213 #define IICINTRMSK 0x0D
2214 #define IICXFRCNT 0x0E
2215 #define IICXTCNTLSS 0x0F
2216 #define IICDIRECTCNTL 0x10
2218 /*-----------------------------------------------------------------------------
2219 | UART Register Offsets
2220 '----------------------------------------------------------------------------*/
2221 #define DATA_REG 0x00
2224 #define INT_ENABLE 0x01
2225 #define FIFO_CONTROL 0x02
2226 #define LINE_CONTROL 0x03
2227 #define MODEM_CONTROL 0x04
2228 #define LINE_STATUS 0x05
2229 #define MODEM_STATUS 0x06
2230 #define SCRATCH 0x07
2232 /*-----------------------------------------------------------------------------
2233 | PCI Internal Registers et. al. (accessed via plb)
2234 +----------------------------------------------------------------------------*/
2235 #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000)
2236 #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004)
2237 #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
2238 #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
2240 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
2241 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2243 /* PCI Local Configuration Registers
2244 --------------------------------- */
2245 #define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
2247 /* PCI Master Local Configuration Registers */
2248 #define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
2249 #define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
2250 #define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
2251 #define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
2252 #define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
2253 #define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
2254 #define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
2255 #define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
2256 #define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
2257 #define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
2258 #define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
2259 #define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
2261 /* PCI Target Local Configuration Registers */
2262 #define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
2263 #define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
2264 #define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
2265 #define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
2269 #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
2270 #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
2271 #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
2272 #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
2273 #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
2274 #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
2275 #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
2276 #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
2277 #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
2278 #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
2279 #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
2280 #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
2281 #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
2282 #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
2283 #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
2284 #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
2285 #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
2286 #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
2287 #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
2288 #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
2289 #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
2290 #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
2291 #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
2292 #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
2293 #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
2294 #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
2295 #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
2296 #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
2298 #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
2299 #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
2301 #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
2302 #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
2303 #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
2304 #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
2305 #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
2306 #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
2307 #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
2308 #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
2309 #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
2310 #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
2311 #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
2313 #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
2314 #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
2315 #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
2316 #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
2317 #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
2318 #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
2319 #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
2320 #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
2321 #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
2323 #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
2325 #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
2327 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2330 #define USB2D0_BASE CFG_USB2D0_BASE
2332 #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
2334 #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
2335 #define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
2336 #define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
2337 #define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
2338 #define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
2339 #define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
2340 #define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
2341 #define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
2342 #define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
2343 #define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
2344 #define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
2345 #define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
2346 #define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
2347 #define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
2348 #define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
2349 #define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
2350 #define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
2351 #define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
2354 /******************************************************************************
2355 * GPIO macro register defines
2356 ******************************************************************************/
2357 #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
2358 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2359 defined(CONFIG_460SX)
2360 #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
2362 #define GPIO0_OR (GPIO0_BASE+0x0)
2363 #define GPIO0_TCR (GPIO0_BASE+0x4)
2364 #define GPIO0_ODR (GPIO0_BASE+0x18)
2365 #define GPIO0_IR (GPIO0_BASE+0x1C)
2366 #endif /* CONFIG_440GP */
2368 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
2369 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
2370 defined(CONFIG_460EX) || defined(CONFIG_460GT)
2371 #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
2372 #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
2374 #define GPIO0_OR (GPIO0_BASE+0x0)
2375 #define GPIO0_TCR (GPIO0_BASE+0x4)
2376 #define GPIO0_OSRL (GPIO0_BASE+0x8)
2377 #define GPIO0_OSRH (GPIO0_BASE+0xC)
2378 #define GPIO0_TSRL (GPIO0_BASE+0x10)
2379 #define GPIO0_TSRH (GPIO0_BASE+0x14)
2380 #define GPIO0_ODR (GPIO0_BASE+0x18)
2381 #define GPIO0_IR (GPIO0_BASE+0x1C)
2382 #define GPIO0_RR1 (GPIO0_BASE+0x20)
2383 #define GPIO0_RR2 (GPIO0_BASE+0x24)
2384 #define GPIO0_RR3 (GPIO0_BASE+0x28)
2385 #define GPIO0_ISR1L (GPIO0_BASE+0x30)
2386 #define GPIO0_ISR1H (GPIO0_BASE+0x34)
2387 #define GPIO0_ISR2L (GPIO0_BASE+0x38)
2388 #define GPIO0_ISR2H (GPIO0_BASE+0x3C)
2389 #define GPIO0_ISR3L (GPIO0_BASE+0x40)
2390 #define GPIO0_ISR3H (GPIO0_BASE+0x44)
2392 #define GPIO1_OR (GPIO1_BASE+0x0)
2393 #define GPIO1_TCR (GPIO1_BASE+0x4)
2394 #define GPIO1_OSRL (GPIO1_BASE+0x8)
2395 #define GPIO1_OSRH (GPIO1_BASE+0xC)
2396 #define GPIO1_TSRL (GPIO1_BASE+0x10)
2397 #define GPIO1_TSRH (GPIO1_BASE+0x14)
2398 #define GPIO1_ODR (GPIO1_BASE+0x18)
2399 #define GPIO1_IR (GPIO1_BASE+0x1C)
2400 #define GPIO1_RR1 (GPIO1_BASE+0x20)
2401 #define GPIO1_RR2 (GPIO1_BASE+0x24)
2402 #define GPIO1_RR3 (GPIO1_BASE+0x28)
2403 #define GPIO1_ISR1L (GPIO1_BASE+0x30)
2404 #define GPIO1_ISR1H (GPIO1_BASE+0x34)
2405 #define GPIO1_ISR2L (GPIO1_BASE+0x38)
2406 #define GPIO1_ISR2H (GPIO1_BASE+0x3C)
2407 #define GPIO1_ISR3L (GPIO1_BASE+0x40)
2408 #define GPIO1_ISR3H (GPIO1_BASE+0x44)
2411 #ifndef __ASSEMBLY__
2413 static inline u32 get_mcsr(void)
2417 asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
2421 static inline void set_mcsr(u32 val)
2423 asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
2426 #endif /* _ASMLANGUAGE */
2428 #endif /* __PPC440_H__ */
projects / platform / kernel / u-boot.git / blob