1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
25 #define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
27 /*--------------------------------------------------------------------- */
28 /* Special Purpose Registers */
29 /*--------------------------------------------------------------------- */
32 #define dec 0x016 /* decrementer */
33 #define srr0 0x01a /* save/restore register 0 */
34 #define srr1 0x01b /* save/restore register 1 */
35 #define pid 0x030 /* process id */
36 #define decar 0x036 /* decrementer auto-reload */
37 #define csrr0 0x03a /* critical save/restore register 0 */
38 #define csrr1 0x03b /* critical save/restore register 1 */
39 #define dear 0x03d /* data exception address register */
40 #define esr 0x03e /* exception syndrome register */
41 #define ivpr 0x03f /* interrupt prefix register */
42 #define usprg0 0x100 /* user special purpose register general 0 */
43 #define usprg1 0x110 /* user special purpose register general 1 */
44 #define tblr 0x10c /* time base lower, read only */
45 #define tbur 0x10d /* time base upper, read only */
46 #define sprg1 0x111 /* special purpose register general 1 */
47 #define sprg2 0x112 /* special purpose register general 2 */
48 #define sprg3 0x113 /* special purpose register general 3 */
49 #define sprg4 0x114 /* special purpose register general 4 */
50 #define sprg5 0x115 /* special purpose register general 5 */
51 #define sprg6 0x116 /* special purpose register general 6 */
52 #define sprg7 0x117 /* special purpose register general 7 */
53 #define tbl 0x11c /* time base lower (supervisor)*/
54 #define tbu 0x11d /* time base upper (supervisor)*/
55 #define pir 0x11e /* processor id register */
56 /*#define pvr 0x11f processor version register */
57 #define dbsr 0x130 /* debug status register */
58 #define dbcr0 0x134 /* debug control register 0 */
59 #define dbcr1 0x135 /* debug control register 1 */
60 #define dbcr2 0x136 /* debug control register 2 */
61 #define iac1 0x138 /* instruction address compare 1 */
62 #define iac2 0x139 /* instruction address compare 2 */
63 #define iac3 0x13a /* instruction address compare 3 */
64 #define iac4 0x13b /* instruction address compare 4 */
65 #define dac1 0x13c /* data address compare 1 */
66 #define dac2 0x13d /* data address compare 2 */
67 #define dvc1 0x13e /* data value compare 1 */
68 #define dvc2 0x13f /* data value compare 2 */
69 #define tsr 0x150 /* timer status register */
70 #define tcr 0x154 /* timer control register */
71 #define ivor0 0x190 /* interrupt vector offset register 0 */
72 #define ivor1 0x191 /* interrupt vector offset register 1 */
73 #define ivor2 0x192 /* interrupt vector offset register 2 */
74 #define ivor3 0x193 /* interrupt vector offset register 3 */
75 #define ivor4 0x194 /* interrupt vector offset register 4 */
76 #define ivor5 0x195 /* interrupt vector offset register 5 */
77 #define ivor6 0x196 /* interrupt vector offset register 6 */
78 #define ivor7 0x197 /* interrupt vector offset register 7 */
79 #define ivor8 0x198 /* interrupt vector offset register 8 */
80 #define ivor9 0x199 /* interrupt vector offset register 9 */
81 #define ivor10 0x19a /* interrupt vector offset register 10 */
82 #define ivor11 0x19b /* interrupt vector offset register 11 */
83 #define ivor12 0x19c /* interrupt vector offset register 12 */
84 #define ivor13 0x19d /* interrupt vector offset register 13 */
85 #define ivor14 0x19e /* interrupt vector offset register 14 */
86 #define ivor15 0x19f /* interrupt vector offset register 15 */
87 #if defined(CONFIG_440)
88 #define mcsrr0 0x23a /* machine check save/restore register 0 */
89 #define mcsrr1 0x23b /* mahcine check save/restore register 1 */
90 #define mcsr 0x23c /* machine check status register */
92 #define inv0 0x370 /* instruction cache normal victim 0 */
93 #define inv1 0x371 /* instruction cache normal victim 1 */
94 #define inv2 0x372 /* instruction cache normal victim 2 */
95 #define inv3 0x373 /* instruction cache normal victim 3 */
96 #define itv0 0x374 /* instruction cache transient victim 0 */
97 #define itv1 0x375 /* instruction cache transient victim 1 */
98 #define itv2 0x376 /* instruction cache transient victim 2 */
99 #define itv3 0x377 /* instruction cache transient victim 3 */
100 #define dnv0 0x390 /* data cache normal victim 0 */
101 #define dnv1 0x391 /* data cache normal victim 1 */
102 #define dnv2 0x392 /* data cache normal victim 2 */
103 #define dnv3 0x393 /* data cache normal victim 3 */
104 #define dtv0 0x394 /* data cache transient victim 0 */
105 #define dtv1 0x395 /* data cache transient victim 1 */
106 #define dtv2 0x396 /* data cache transient victim 2 */
107 #define dtv3 0x397 /* data cache transient victim 3 */
108 #define dvlim 0x398 /* data cache victim limit */
109 #define ivlim 0x399 /* instruction cache victim limit */
110 #define rstcfg 0x39b /* reset configuration */
111 #define dcdbtrl 0x39c /* data cache debug tag register low */
112 #define dcdbtrh 0x39d /* data cache debug tag register high */
113 #define icdbtrl 0x39e /* instruction cache debug tag register low */
114 #define icdbtrh 0x39f /* instruction cache debug tag register high */
115 #define mmucr 0x3b2 /* mmu control register */
116 #define ccr0 0x3b3 /* core configuration register 0 */
117 #define ccr1 0x378 /* core configuration for 440x5 only */
118 #define icdbdr 0x3d3 /* instruction cache debug data register */
119 #define dbdr 0x3f3 /* debug data register */
121 /******************************************************************************
123 ******************************************************************************/
125 /*-----------------------------------------------------------------------------
126 | Clocking Controller
127 +----------------------------------------------------------------------------*/
128 /* values for clkcfga register - indirect addressing of these regs */
129 #define clk_clkukpd 0x0020
130 #define clk_pllc 0x0040
131 #define clk_plld 0x0060
132 #define clk_primad 0x0080
133 #define clk_primbd 0x00a0
134 #define clk_opbd 0x00c0
135 #define clk_perd 0x00e0
136 #define clk_mald 0x0100
137 #define clk_spcid 0x0120
138 #define clk_icfg 0x0140
140 /* 440gx sdr register definations */
141 #define sdr_sdstp0 0x0020 /* */
142 #define sdr_sdstp1 0x0021 /* */
143 #define SDR_PINSTP 0x0040
144 #define sdr_sdcs 0x0060
145 #define sdr_ecid0 0x0080
146 #define sdr_ecid1 0x0081
147 #define sdr_ecid2 0x0082
148 #define sdr_jtag 0x00c0
149 #if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
150 #define sdr_ddrdl 0x00e0
152 #define sdr_cfg 0x00e0
153 #define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/
154 #define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */
155 #define SDR_CFG_32BITS 0x00000000 /* 32 bits */
156 #define SDR_CFG_64BITS 0x01000000 /* 64 bits */
157 #define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
158 #define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */
159 #define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */
160 #endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
161 #define sdr_ebc 0x0100
162 #define sdr_uart0 0x0120 /* UART0 Config */
163 #define sdr_uart1 0x0121 /* UART1 Config */
164 #define sdr_uart2 0x0122 /* UART2 Config */
165 #define sdr_uart3 0x0123 /* UART3 Config */
166 #define sdr_cp440 0x0180
167 #define sdr_xcr 0x01c0
168 #define sdr_xpllc 0x01c1
169 #define sdr_xplld 0x01c2
170 #define sdr_srst 0x0200
171 #define sdr_slpipe 0x0220
172 #define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
173 #define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
174 #define sdr_mirq0 0x0260
175 #define sdr_mirq1 0x0261
176 #define sdr_maltbl 0x0280
177 #define sdr_malrbl 0x02a0
178 #define sdr_maltbs 0x02c0
179 #define sdr_malrbs 0x02e0
180 #define sdr_pci0 0x0300
181 #define sdr_usb0 0x0320
182 #define sdr_cust0 0x4000
183 #define sdr_cust1 0x4002
184 #define sdr_pfc0 0x4100 /* Pin Function 0 */
185 #define sdr_pfc1 0x4101 /* Pin Function 1 */
186 #define sdr_plbtr 0x4200
187 #define sdr_mfr 0x4300 /* SDR0_MFR reg */
189 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* test-only!!!! */
235 #endif /*CONFIG_440EPX*/
237 /*-----------------------------------------------------------------------------
239 +----------------------------------------------------------------------------*/
240 /* values for memcfga register - indirect addressing of these regs */
241 #define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */
242 #define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */
243 #define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */
244 #define mem_besr1_set 0x000c /* bus error status reg 1 (set) */
245 #define mem_bear 0x0010 /* bus error address reg */
246 #define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */
247 #define mem_mirq_set 0x0012 /* bus master interrupt (set) */
248 #define mem_slio 0x0018 /* ddr sdram slave interface options */
249 #define mem_cfg0 0x0020 /* ddr sdram options 0 */
250 #define mem_cfg1 0x0021 /* ddr sdram options 1 */
251 #define mem_devopt 0x0022 /* ddr sdram device options */
252 #define mem_mcsts 0x0024 /* memory controller status */
253 #define mem_rtr 0x0030 /* refresh timer register */
254 #define mem_pmit 0x0034 /* power management idle timer */
255 #define mem_uabba 0x0038 /* plb UABus base address */
256 #define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */
257 #define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */
258 #define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */
259 #define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */
260 #define mem_tr0 0x0080 /* sdram timing register 0 */
261 #define mem_tr1 0x0081 /* sdram timing register 1 */
262 #define mem_clktr 0x0082 /* ddr clock timing register */
263 #define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */
264 #define mem_dlycal 0x0084 /* delay line calibration register */
265 #define mem_eccesr 0x0098 /* ECC error status */
268 #define sdr_amp 0x0240
269 #define sdr_xpllc 0x01c1
270 #define sdr_xplld 0x01c2
271 #define sdr_xcr 0x01c0
272 #define sdr_sdstp2 0x4001
273 #define sdr_sdstp3 0x4003
274 #endif /* CONFIG_440GX */
276 /*----------------------------------------------------------------------------+
277 | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
278 +----------------------------------------------------------------------------*/
279 #define CCR0_PRE 0x40000000
280 #define CCR0_CRPE 0x08000000
281 #define CCR0_DSTG 0x00200000
282 #define CCR0_DAPUIB 0x00100000
283 #define CCR0_DTB 0x00008000
284 #define CCR0_GICBT 0x00004000
285 #define CCR0_GDCBT 0x00002000
286 #define CCR0_FLSTA 0x00000100
287 #define CCR0_ICSLC_MASK 0x0000000C
288 #define CCR0_ICSLT_MASK 0x00000003
289 #define CCR1_TCS_MASK 0x00000080
290 #define CCR1_TCS_INTCLK 0x00000000
291 #define CCR1_TCS_EXTCLK 0x00000080
292 #define MMUCR_SWOA 0x01000000
293 #define MMUCR_U1TE 0x00400000
294 #define MMUCR_U2SWOAE 0x00200000
295 #define MMUCR_DULXE 0x00800000
296 #define MMUCR_IULXE 0x00400000
297 #define MMUCR_STS 0x00100000
298 #define MMUCR_STID_MASK 0x000000FF
302 #define sdr_sdstp2 0x0022
304 #define sdr_sdstp3 0x0023
305 #define sdr_ddr0 0x00E1
306 #define sdr_uart2 0x0122
307 #define sdr_xcr0 0x01c0
308 /* #define sdr_xcr1 0x01c3 only one PCIX - SG */
309 /* #define sdr_xcr2 0x01c6 only one PCIX - SG */
310 #define sdr_xpllc0 0x01c1
311 #define sdr_xplld0 0x01c2
312 #define sdr_xpllc1 0x01c4 /*notRCW - SG */
313 #define sdr_xplld1 0x01c5 /*notRCW - SG */
314 #define sdr_xpllc2 0x01c7 /*notRCW - SG */
315 #define sdr_xplld2 0x01c8 /*notRCW - SG */
316 #define sdr_amp0 0x0240
317 #define sdr_amp1 0x0241
318 #define sdr_cust2 0x4004
319 #define sdr_cust3 0x4006
320 #define sdr_sdstp4 0x4001
321 #define sdr_sdstp5 0x4003
322 #define sdr_sdstp6 0x4005
323 #define sdr_sdstp7 0x4007
325 /******************************************************************************
326 * PCI express defines
327 ******************************************************************************/
328 #define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */
329 #define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */
330 #define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */
331 #define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */
332 #define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */
333 #define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */
334 #define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */
335 #define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */
336 #define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */
337 #define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */
338 #define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */
339 #define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */
340 #define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */
341 #define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */
342 #define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */
343 #define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */
344 #define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */
345 #define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */
346 #define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */
347 #define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */
348 #define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */
349 #define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */
350 #define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */
351 #define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */
352 #define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */
353 #define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */
354 #define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */
355 #define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */
356 #define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */
357 #define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */
358 #define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */
359 #define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */
360 #define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */
362 #define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */
363 #define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */
364 #define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */
365 #define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */
366 #define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */
367 #define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */
368 #define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */
369 #define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */
370 #define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */
371 #define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */
372 #define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */
373 #define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */
374 #define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */
375 #define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */
376 #define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */
377 #define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */
378 #define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */
379 #define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */
380 #define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */
381 #define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */
382 #define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */
383 #define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */
384 #define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */
385 #define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */
386 #define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */
387 #define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */
388 #define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */
389 #define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */
390 #define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */
391 #define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */
392 #define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */
393 #define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */
394 #define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */
395 #define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */
396 #define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */
397 #define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */
398 #define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */
399 #define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */
400 #define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */
401 #define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */
402 #define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
403 #define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
404 #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
405 #endif /* CONFIG_440SPE */
407 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
408 /*----------------------------------------------------------------------------+
410 +----------------------------------------------------------------------------*/
411 /*-----------------------------------------------------------------------------+
412 | SDRAM DLYCAL Options
413 +-----------------------------------------------------------------------------*/
414 #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
415 #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
416 #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
418 /*----------------------------------------------------------------------------+
419 | Memory queue defines
420 +----------------------------------------------------------------------------*/
421 /* A REVOIR versus RWC - SG*/
422 #define SDRAMQ_DCR_BASE 0x040
424 #define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */
425 #define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */
426 #define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */
427 #define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */
428 #define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */
429 #define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */
430 #define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */
431 #define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */
432 #define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */
433 #define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */
434 #define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */
435 #define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */
436 #define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */
437 #define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */
438 #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */
440 /*-----------------------------------------------------------------------------+
441 | Memory Bank 0-7 configuration
442 +-----------------------------------------------------------------------------*/
443 #if defined(CONFIG_440SPE)
444 #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */
445 #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFFE00000)>>2)
446 #define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFFE00000)<<2)
447 #endif /* CONFIG_440SPE */
448 #if defined(CONFIG_440SP)
449 #define SDRAM_RXBAS_SDBA_MASK 0xFF800000 /* Base address */
450 #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((unsigned long)(n))&0xFF800000))
451 #define SDRAM_RXBAS_SDBA_DECODE(n) ((((unsigned long)(n))&0xFF800000))
452 #endif /* CONFIG_440SP */
453 #define SDRAM_RXBAS_SDSZ_MASK 0x0000FFC0 /* Size */
454 #define SDRAM_RXBAS_SDSZ_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<6)
455 #define SDRAM_RXBAS_SDSZ_DECODE(n) ((((unsigned long)(n))>>6)&0x3FF)
456 #define SDRAM_RXBAS_SDSZ_0 0x00000000 /* 0M */
457 #define SDRAM_RXBAS_SDSZ_8 0x0000FFC0 /* 8M */
458 #define SDRAM_RXBAS_SDSZ_16 0x0000FF80 /* 16M */
459 #define SDRAM_RXBAS_SDSZ_32 0x0000FF00 /* 32M */
460 #define SDRAM_RXBAS_SDSZ_64 0x0000FE00 /* 64M */
461 #define SDRAM_RXBAS_SDSZ_128 0x0000FC00 /* 128M */
462 #define SDRAM_RXBAS_SDSZ_256 0x0000F800 /* 256M */
463 #define SDRAM_RXBAS_SDSZ_512 0x0000F000 /* 512M */
464 #define SDRAM_RXBAS_SDSZ_1024 0x0000E000 /* 1024M */
465 #define SDRAM_RXBAS_SDSZ_2048 0x0000C000 /* 2048M */
466 #define SDRAM_RXBAS_SDSZ_4096 0x00008000 /* 4096M */
468 /*----------------------------------------------------------------------------+
469 | Memory controller defines
470 +----------------------------------------------------------------------------*/
471 /* A REVOIR versus specs 4 bank - SG*/
472 #define SDRAM_MCSTAT 0x14 /* memory controller status */
473 #define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
474 #define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
475 #define SDRAM_MODT0 0x22 /* on die termination for bank 0 */
476 #define SDRAM_MODT1 0x23 /* on die termination for bank 1 */
477 #define SDRAM_MODT2 0x24 /* on die termination for bank 2 */
478 #define SDRAM_MODT3 0x25 /* on die termination for bank 3 */
479 #define SDRAM_CODT 0x26 /* on die termination for controller */
480 #define SDRAM_VVPR 0x27 /* variable VRef programmming */
481 #define SDRAM_OPARS 0x28 /* on chip driver control setup */
482 #define SDRAM_OPART 0x29 /* on chip driver control trigger */
483 #define SDRAM_RTR 0x30 /* refresh timer */
484 #define SDRAM_PMIT 0x34 /* power management idle timer */
485 #define SDRAM_MB0CF 0x40 /* memory bank 0 configuration */
486 #define SDRAM_MB1CF 0x44 /* memory bank 1 configuration */
487 #define SDRAM_MB2CF 0x48
488 #define SDRAM_MB3CF 0x4C
489 #define SDRAM_INITPLR0 0x50 /* manual initialization control */
490 #define SDRAM_INITPLR1 0x51 /* manual initialization control */
491 #define SDRAM_INITPLR2 0x52 /* manual initialization control */
492 #define SDRAM_INITPLR3 0x53 /* manual initialization control */
493 #define SDRAM_INITPLR4 0x54 /* manual initialization control */
494 #define SDRAM_INITPLR5 0x55 /* manual initialization control */
495 #define SDRAM_INITPLR6 0x56 /* manual initialization control */
496 #define SDRAM_INITPLR7 0x57 /* manual initialization control */
497 #define SDRAM_INITPLR8 0x58 /* manual initialization control */
498 #define SDRAM_INITPLR9 0x59 /* manual initialization control */
499 #define SDRAM_INITPLR10 0x5a /* manual initialization control */
500 #define SDRAM_INITPLR11 0x5b /* manual initialization control */
501 #define SDRAM_INITPLR12 0x5c /* manual initialization control */
502 #define SDRAM_INITPLR13 0x5d /* manual initialization control */
503 #define SDRAM_INITPLR14 0x5e /* manual initialization control */
504 #define SDRAM_INITPLR15 0x5f /* manual initialization control */
505 #define SDRAM_RQDC 0x70 /* read DQS delay control */
506 #define SDRAM_RFDC 0x74 /* read feedback delay control */
507 #define SDRAM_RDCC 0x78 /* read data capture control */
508 #define SDRAM_DLCR 0x7A /* delay line calibration */
509 #define SDRAM_CLKTR 0x80 /* DDR clock timing */
510 #define SDRAM_WRDTR 0x81 /* write data, DQS, DM clock, timing */
511 #define SDRAM_SDTR1 0x85 /* DDR SDRAM timing 1 */
512 #define SDRAM_SDTR2 0x86 /* DDR SDRAM timing 2 */
513 #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */
514 #define SDRAM_MMODE 0x88 /* memory mode */
515 #define SDRAM_MEMODE 0x89 /* memory extended mode */
516 #define SDRAM_ECCCR 0x98 /* ECC error status */
517 #define SDRAM_CID 0xA4 /* core ID */
518 #define SDRAM_RID 0xA8 /* revision ID */
520 /*-----------------------------------------------------------------------------+
521 | Memory Controller Status
522 +-----------------------------------------------------------------------------*/
523 #define SDRAM_MCSTAT_MIC_MASK 0x80000000 /* Memory init status mask */
524 #define SDRAM_MCSTAT_MIC_NOTCOMP 0x00000000 /* Mem init not complete */
525 #define SDRAM_MCSTAT_MIC_COMP 0x80000000 /* Mem init complete */
526 #define SDRAM_MCSTAT_SRMS_MASK 0x40000000 /* Mem self refresh stat mask */
527 #define SDRAM_MCSTAT_SRMS_NOT_SF 0x00000000 /* Mem not in self refresh */
528 #define SDRAM_MCSTAT_SRMS_SF 0x40000000 /* Mem in self refresh */
529 #define SDRAM_MCSTAT_IDLE_MASK 0x20000000 /* Mem self refresh stat mask */
530 #define SDRAM_MCSTAT_IDLE_NOT 0x00000000 /* Mem contr not idle */
531 #define SDRAM_MCSTAT_IDLE 0x20000000 /* Mem contr idle */
533 /*-----------------------------------------------------------------------------+
534 | Memory Controller Options 1
535 +-----------------------------------------------------------------------------*/
536 #define SDRAM_MCOPT1_MCHK_MASK 0x30000000 /* Memory data err check mask*/
537 #define SDRAM_MCOPT1_MCHK_NON 0x00000000 /* No ECC generation */
538 #define SDRAM_MCOPT1_MCHK_GEN 0x20000000 /* ECC generation */
539 #define SDRAM_MCOPT1_MCHK_CHK 0x10000000 /* ECC generation and check */
540 #define SDRAM_MCOPT1_MCHK_CHK_REP 0x30000000 /* ECC generation, chk, report*/
541 #define SDRAM_MCOPT1_MCHK_CHK_DECODE(n) ((((unsigned long)(n))>>28)&0x3)
542 #define SDRAM_MCOPT1_RDEN_MASK 0x08000000 /* Registered DIMM mask */
543 #define SDRAM_MCOPT1_RDEN 0x08000000 /* Registered DIMM enable */
544 #define SDRAM_MCOPT1_PMU_MASK 0x06000000 /* Page management unit mask */
545 #define SDRAM_MCOPT1_PMU_CLOSE 0x00000000 /* PMU Close */
546 #define SDRAM_MCOPT1_PMU_OPEN 0x04000000 /* PMU Open */
547 #define SDRAM_MCOPT1_PMU_AUTOCLOSE 0x02000000 /* PMU AutoClose */
548 #define SDRAM_MCOPT1_DMWD_MASK 0x01000000 /* DRAM width mask */
549 #define SDRAM_MCOPT1_DMWD_32 0x00000000 /* 32 bits */
550 #define SDRAM_MCOPT1_DMWD_64 0x01000000 /* 64 bits */
551 #define SDRAM_MCOPT1_UIOS_MASK 0x00C00000 /* Unused IO State */
552 #define SDRAM_MCOPT1_BCNT_MASK 0x00200000 /* Bank count */
553 #define SDRAM_MCOPT1_4_BANKS 0x00000000 /* 4 Banks */
554 #define SDRAM_MCOPT1_8_BANKS 0x00200000 /* 8 Banks */
555 #define SDRAM_MCOPT1_DDR_TYPE_MASK 0x00100000 /* DDR Memory Type mask */
556 #define SDRAM_MCOPT1_DDR1_TYPE 0x00000000 /* DDR1 Memory Type */
557 #define SDRAM_MCOPT1_DDR2_TYPE 0x00100000 /* DDR2 Memory Type */
558 #define SDRAM_MCOPT1_QDEP 0x00020000 /* 4 commands deep */
559 #define SDRAM_MCOPT1_RWOO_MASK 0x00008000 /* Out of Order Read mask */
560 #define SDRAM_MCOPT1_RWOO_DISABLED 0x00000000 /* disabled */
561 #define SDRAM_MCOPT1_RWOO_ENABLED 0x00008000 /* enabled */
562 #define SDRAM_MCOPT1_WOOO_MASK 0x00004000 /* Out of Order Write mask */
563 #define SDRAM_MCOPT1_WOOO_DISABLED 0x00000000 /* disabled */
564 #define SDRAM_MCOPT1_WOOO_ENABLED 0x00004000 /* enabled */
565 #define SDRAM_MCOPT1_DCOO_MASK 0x00002000 /* All Out of Order mask */
566 #define SDRAM_MCOPT1_DCOO_DISABLED 0x00002000 /* disabled */
567 #define SDRAM_MCOPT1_DCOO_ENABLED 0x00000000 /* enabled */
568 #define SDRAM_MCOPT1_DREF_MASK 0x00001000 /* Deferred refresh mask */
569 #define SDRAM_MCOPT1_DREF_NORMAL 0x00000000 /* normal refresh */
570 #define SDRAM_MCOPT1_DREF_DEFER_4 0x00001000 /* defer up to 4 refresh cmd */
572 /*-----------------------------------------------------------------------------+
573 | Memory Controller Options 2
574 +-----------------------------------------------------------------------------*/
575 #define SDRAM_MCOPT2_SREN_MASK 0x80000000 /* Self Test mask */
576 #define SDRAM_MCOPT2_SREN_EXIT 0x00000000 /* Self Test exit */
577 #define SDRAM_MCOPT2_SREN_ENTER 0x80000000 /* Self Test enter */
578 #define SDRAM_MCOPT2_PMEN_MASK 0x40000000 /* Power Management mask */
579 #define SDRAM_MCOPT2_PMEN_DISABLE 0x00000000 /* disable */
580 #define SDRAM_MCOPT2_PMEN_ENABLE 0x40000000 /* enable */
581 #define SDRAM_MCOPT2_IPTR_MASK 0x20000000 /* Init Trigger Reg mask */
582 #define SDRAM_MCOPT2_IPTR_IDLE 0x00000000 /* idle */
583 #define SDRAM_MCOPT2_IPTR_EXECUTE 0x20000000 /* execute preloaded init */
584 #define SDRAM_MCOPT2_XSRP_MASK 0x10000000 /* Exit Self Refresh Prevent */
585 #define SDRAM_MCOPT2_XSRP_ALLOW 0x00000000 /* allow self refresh exit */
586 #define SDRAM_MCOPT2_XSRP_PREVENT 0x10000000 /* prevent self refresh exit */
587 #define SDRAM_MCOPT2_DCEN_MASK 0x08000000 /* SDRAM Controller Enable */
588 #define SDRAM_MCOPT2_DCEN_DISABLE 0x00000000 /* SDRAM Controller Enable */
589 #define SDRAM_MCOPT2_DCEN_ENABLE 0x08000000 /* SDRAM Controller Enable */
590 #define SDRAM_MCOPT2_ISIE_MASK 0x04000000 /* Init Seq Interruptable mas*/
591 #define SDRAM_MCOPT2_ISIE_DISABLE 0x00000000 /* disable */
592 #define SDRAM_MCOPT2_ISIE_ENABLE 0x04000000 /* enable */
594 /*-----------------------------------------------------------------------------+
595 | SDRAM Refresh Timer Register
596 +-----------------------------------------------------------------------------*/
597 #define SDRAM_RTR_RINT_MASK 0xFFF80000
598 #define SDRAM_RTR_RINT_ENCODE(n) ((((unsigned long)(n))&0xFFF8)<<16)
599 #define SDRAM_RTR_RINT_DECODE(n) ((((unsigned long)(n))>>16)&0xFFF8)
601 /*-----------------------------------------------------------------------------+
602 | SDRAM Read DQS Delay Control Register
603 +-----------------------------------------------------------------------------*/
604 #define SDRAM_RQDC_RQDE_MASK 0x80000000
605 #define SDRAM_RQDC_RQDE_DISABLE 0x00000000
606 #define SDRAM_RQDC_RQDE_ENABLE 0x80000000
607 #define SDRAM_RQDC_RQFD_MASK 0x000001FF
608 #define SDRAM_RQDC_RQFD_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
610 #define SDRAM_RQDC_RQFD_MAX 0x1FF
612 /*-----------------------------------------------------------------------------+
613 | SDRAM Read Data Capture Control Register
614 +-----------------------------------------------------------------------------*/
615 #define SDRAM_RDCC_RDSS_MASK 0xC0000000
616 #define SDRAM_RDCC_RDSS_T1 0x00000000
617 #define SDRAM_RDCC_RDSS_T2 0x40000000
618 #define SDRAM_RDCC_RDSS_T3 0x80000000
619 #define SDRAM_RDCC_RDSS_T4 0xC0000000
620 #define SDRAM_RDCC_RSAE_MASK 0x00000001
621 #define SDRAM_RDCC_RSAE_DISABLE 0x00000001
622 #define SDRAM_RDCC_RSAE_ENABLE 0x00000000
624 /*-----------------------------------------------------------------------------+
625 | SDRAM Read Feedback Delay Control Register
626 +-----------------------------------------------------------------------------*/
627 #define SDRAM_RFDC_ARSE_MASK 0x80000000
628 #define SDRAM_RFDC_ARSE_DISABLE 0x80000000
629 #define SDRAM_RFDC_ARSE_ENABLE 0x00000000
630 #define SDRAM_RFDC_RFOS_MASK 0x007F0000
631 #define SDRAM_RFDC_RFOS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16)
632 #define SDRAM_RFDC_RFFD_MASK 0x000003FF
633 #define SDRAM_RFDC_RFFD_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
635 #define SDRAM_RFDC_RFFD_MAX 0x7FF
637 /*-----------------------------------------------------------------------------+
638 | SDRAM Delay Line Calibration Register
639 +-----------------------------------------------------------------------------*/
640 #define SDRAM_DLCR_DCLM_MASK 0x80000000
641 #define SDRAM_DLCR_DCLM_MANUEL 0x80000000
642 #define SDRAM_DLCR_DCLM_AUTO 0x00000000
643 #define SDRAM_DLCR_DLCR_MASK 0x08000000
644 #define SDRAM_DLCR_DLCR_CALIBRATE 0x08000000
645 #define SDRAM_DLCR_DLCR_IDLE 0x00000000
646 #define SDRAM_DLCR_DLCS_MASK 0x07000000
647 #define SDRAM_DLCR_DLCS_NOT_RUN 0x00000000
648 #define SDRAM_DLCR_DLCS_IN_PROGRESS 0x01000000
649 #define SDRAM_DLCR_DLCS_COMPLETE 0x02000000
650 #define SDRAM_DLCR_DLCS_CONT_DONE 0x03000000
651 #define SDRAM_DLCR_DLCS_ERROR 0x04000000
652 #define SDRAM_DLCR_DLCV_MASK 0x000001FF
653 #define SDRAM_DLCR_DLCV_ENCODE(n) ((((unsigned long)(n))&0x1FF)<<0)
654 #define SDRAM_DLCR_DLCV_DECODE(n) ((((unsigned long)(n))>>0)&0x1FF)
656 /*-----------------------------------------------------------------------------+
657 | SDRAM Controller On Die Termination Register
658 +-----------------------------------------------------------------------------*/
659 #define SDRAM_CODT_ODT_ON 0x80000000
660 #define SDRAM_CODT_ODT_OFF 0x00000000
661 #define SDRAM_CODT_DQS_VOLTAGE_DDR_MASK 0x00000020
662 #define SDRAM_CODT_DQS_2_5_V_DDR1 0x00000000
663 #define SDRAM_CODT_DQS_1_8_V_DDR2 0x00000020
664 #define SDRAM_CODT_DQS_MASK 0x00000010
665 #define SDRAM_CODT_DQS_DIFFERENTIAL 0x00000000
666 #define SDRAM_CODT_DQS_SINGLE_END 0x00000010
667 #define SDRAM_CODT_CKSE_DIFFERENTIAL 0x00000000
668 #define SDRAM_CODT_CKSE_SINGLE_END 0x00000008
669 #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004
670 #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002
671 #define SDRAM_CODT_IO_HIZ 0x00000000
672 #define SDRAM_CODT_IO_NMODE 0x00000001
674 /*-----------------------------------------------------------------------------+
675 | SDRAM Mode Register
676 +-----------------------------------------------------------------------------*/
677 #define SDRAM_MMODE_WR_MASK 0x00000E00
678 #define SDRAM_MMODE_WR_DDR1 0x00000000
679 #define SDRAM_MMODE_WR_DDR2_3_CYC 0x00000400
680 #define SDRAM_MMODE_WR_DDR2_4_CYC 0x00000600
681 #define SDRAM_MMODE_WR_DDR2_5_CYC 0x00000800
682 #define SDRAM_MMODE_WR_DDR2_6_CYC 0x00000A00
683 #define SDRAM_MMODE_DCL_MASK 0x00000070
684 #define SDRAM_MMODE_DCL_DDR1_2_0_CLK 0x00000020
685 #define SDRAM_MMODE_DCL_DDR1_2_5_CLK 0x00000060
686 #define SDRAM_MMODE_DCL_DDR1_3_0_CLK 0x00000030
687 #define SDRAM_MMODE_DCL_DDR2_2_0_CLK 0x00000020
688 #define SDRAM_MMODE_DCL_DDR2_3_0_CLK 0x00000030
689 #define SDRAM_MMODE_DCL_DDR2_4_0_CLK 0x00000040
690 #define SDRAM_MMODE_DCL_DDR2_5_0_CLK 0x00000050
691 #define SDRAM_MMODE_DCL_DDR2_6_0_CLK 0x00000060
692 #define SDRAM_MMODE_DCL_DDR2_7_0_CLK 0x00000070
694 /*-----------------------------------------------------------------------------+
695 | SDRAM Extended Mode Register
696 +-----------------------------------------------------------------------------*/
697 #define SDRAM_MEMODE_DIC_MASK 0x00000002
698 #define SDRAM_MEMODE_DIC_NORMAL 0x00000000
699 #define SDRAM_MEMODE_DIC_WEAK 0x00000002
700 #define SDRAM_MEMODE_DLL_MASK 0x00000001
701 #define SDRAM_MEMODE_DLL_DISABLE 0x00000001
702 #define SDRAM_MEMODE_DLL_ENABLE 0x00000000
703 #define SDRAM_MEMODE_RTT_MASK 0x00000044
704 #define SDRAM_MEMODE_RTT_DISABLED 0x00000000
705 #define SDRAM_MEMODE_RTT_75OHM 0x00000004
706 #define SDRAM_MEMODE_RTT_150OHM 0x00000040
707 #define SDRAM_MEMODE_DQS_MASK 0x00000400
708 #define SDRAM_MEMODE_DQS_DISABLE 0x00000400
709 #define SDRAM_MEMODE_DQS_ENABLE 0x00000000
711 /*-----------------------------------------------------------------------------+
712 | SDRAM Clock Timing Register
713 +-----------------------------------------------------------------------------*/
714 #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
715 #define SDRAM_CLKTR_CLKP_0_DEG 0x00000000
716 #define SDRAM_CLKTR_CLKP_180_DEG_ADV 0x80000000
718 /*-----------------------------------------------------------------------------+
719 | SDRAM Write Timing Register
720 +-----------------------------------------------------------------------------*/
721 #define SDRAM_WRDTR_LLWP_MASK 0x10000000
722 #define SDRAM_WRDTR_LLWP_DIS 0x10000000
723 #define SDRAM_WRDTR_LLWP_1_CYC 0x00000000
724 #define SDRAM_WRDTR_WTR_MASK 0x0E000000
725 #define SDRAM_WRDTR_WTR_0_DEG 0x06000000
726 #define SDRAM_WRDTR_WTR_90_DEG_ADV 0x04000000
727 #define SDRAM_WRDTR_WTR_180_DEG_ADV 0x02000000
728 #define SDRAM_WRDTR_WTR_270_DEG_ADV 0x00000000
730 /*-----------------------------------------------------------------------------+
731 | SDRAM SDTR1 Options
732 +-----------------------------------------------------------------------------*/
733 #define SDRAM_SDTR1_LDOF_MASK 0x80000000
734 #define SDRAM_SDTR1_LDOF_1_CLK 0x00000000
735 #define SDRAM_SDTR1_LDOF_2_CLK 0x80000000
736 #define SDRAM_SDTR1_RTW_MASK 0x00F00000
737 #define SDRAM_SDTR1_RTW_2_CLK 0x00200000
738 #define SDRAM_SDTR1_RTW_3_CLK 0x00300000
739 #define SDRAM_SDTR1_WTWO_MASK 0x000F0000
740 #define SDRAM_SDTR1_WTWO_0_CLK 0x00000000
741 #define SDRAM_SDTR1_WTWO_1_CLK 0x00010000
742 #define SDRAM_SDTR1_RTRO_MASK 0x0000F000
743 #define SDRAM_SDTR1_RTRO_1_CLK 0x00001000
744 #define SDRAM_SDTR1_RTRO_2_CLK 0x00002000
746 /*-----------------------------------------------------------------------------+
747 | SDRAM SDTR2 Options
748 +-----------------------------------------------------------------------------*/
749 #define SDRAM_SDTR2_RCD_MASK 0xF0000000
750 #define SDRAM_SDTR2_RCD_1_CLK 0x10000000
751 #define SDRAM_SDTR2_RCD_2_CLK 0x20000000
752 #define SDRAM_SDTR2_RCD_3_CLK 0x30000000
753 #define SDRAM_SDTR2_RCD_4_CLK 0x40000000
754 #define SDRAM_SDTR2_RCD_5_CLK 0x50000000
755 #define SDRAM_SDTR2_WTR_MASK 0x0F000000
756 #define SDRAM_SDTR2_WTR_1_CLK 0x01000000
757 #define SDRAM_SDTR2_WTR_2_CLK 0x02000000
758 #define SDRAM_SDTR2_WTR_3_CLK 0x03000000
759 #define SDRAM_SDTR2_WTR_4_CLK 0x04000000
760 #define SDRAM_SDTR3_WTR_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
761 #define SDRAM_SDTR2_XSNR_MASK 0x00FF0000
762 #define SDRAM_SDTR2_XSNR_8_CLK 0x00080000
763 #define SDRAM_SDTR2_XSNR_16_CLK 0x00100000
764 #define SDRAM_SDTR2_XSNR_32_CLK 0x00200000
765 #define SDRAM_SDTR2_XSNR_64_CLK 0x00400000
766 #define SDRAM_SDTR2_WPC_MASK 0x0000F000
767 #define SDRAM_SDTR2_WPC_2_CLK 0x00002000
768 #define SDRAM_SDTR2_WPC_3_CLK 0x00003000
769 #define SDRAM_SDTR2_WPC_4_CLK 0x00004000
770 #define SDRAM_SDTR2_WPC_5_CLK 0x00005000
771 #define SDRAM_SDTR2_WPC_6_CLK 0x00006000
772 #define SDRAM_SDTR3_WPC_ENCODE(n) ((((unsigned long)(n))&0xF)<<12)
773 #define SDRAM_SDTR2_RPC_MASK 0x00000F00
774 #define SDRAM_SDTR2_RPC_2_CLK 0x00000200
775 #define SDRAM_SDTR2_RPC_3_CLK 0x00000300
776 #define SDRAM_SDTR2_RPC_4_CLK 0x00000400
777 #define SDRAM_SDTR2_RP_MASK 0x000000F0
778 #define SDRAM_SDTR2_RP_3_CLK 0x00000030
779 #define SDRAM_SDTR2_RP_4_CLK 0x00000040
780 #define SDRAM_SDTR2_RP_5_CLK 0x00000050
781 #define SDRAM_SDTR2_RP_6_CLK 0x00000060
782 #define SDRAM_SDTR2_RP_7_CLK 0x00000070
783 #define SDRAM_SDTR2_RRD_MASK 0x0000000F
784 #define SDRAM_SDTR2_RRD_2_CLK 0x00000002
785 #define SDRAM_SDTR2_RRD_3_CLK 0x00000003
787 /*-----------------------------------------------------------------------------+
788 | SDRAM SDTR3 Options
789 +-----------------------------------------------------------------------------*/
790 #define SDRAM_SDTR3_RAS_MASK 0x1F000000
791 #define SDRAM_SDTR3_RAS_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
792 #define SDRAM_SDTR3_RC_MASK 0x001F0000
793 #define SDRAM_SDTR3_RC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16)
794 #define SDRAM_SDTR3_XCS_MASK 0x00001F00
795 #define SDRAM_SDTR3_XCS 0x00000D00
796 #define SDRAM_SDTR3_RFC_MASK 0x0000003F
797 #define SDRAM_SDTR3_RFC_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
799 /*-----------------------------------------------------------------------------+
800 | Memory Bank 0-1 configuration
801 +-----------------------------------------------------------------------------*/
802 #define SDRAM_BXCF_M_AM_MASK 0x00000F00 /* Addressing mode */
803 #define SDRAM_BXCF_M_AM_0 0x00000000 /* Mode 0 */
804 #define SDRAM_BXCF_M_AM_1 0x00000100 /* Mode 1 */
805 #define SDRAM_BXCF_M_AM_2 0x00000200 /* Mode 2 */
806 #define SDRAM_BXCF_M_AM_3 0x00000300 /* Mode 3 */
807 #define SDRAM_BXCF_M_AM_4 0x00000400 /* Mode 4 */
808 #define SDRAM_BXCF_M_AM_5 0x00000500 /* Mode 5 */
809 #define SDRAM_BXCF_M_AM_6 0x00000600 /* Mode 6 */
810 #define SDRAM_BXCF_M_AM_7 0x00000700 /* Mode 7 */
811 #define SDRAM_BXCF_M_AM_8 0x00000800 /* Mode 8 */
812 #define SDRAM_BXCF_M_AM_9 0x00000900 /* Mode 9 */
813 #define SDRAM_BXCF_M_BE_MASK 0x00000001 /* Memory Bank Enable */
814 #define SDRAM_BXCF_M_BE_DISABLE 0x00000000 /* Memory Bank Enable */
815 #define SDRAM_BXCF_M_BE_ENABLE 0x00000001 /* Memory Bank Enable */
817 #define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */
818 #endif /* CONFIG_440SPE */
820 /*-----------------------------------------------------------------------------
821 | External Bus Controller
822 +----------------------------------------------------------------------------*/
823 /* values for ebccfga register - indirect addressing of these regs */
824 #define pb0cr 0x00 /* periph bank 0 config reg */
825 #define pb1cr 0x01 /* periph bank 1 config reg */
826 #define pb2cr 0x02 /* periph bank 2 config reg */
827 #define pb3cr 0x03 /* periph bank 3 config reg */
828 #define pb4cr 0x04 /* periph bank 4 config reg */
829 #define pb5cr 0x05 /* periph bank 5 config reg */
830 #define pb6cr 0x06 /* periph bank 6 config reg */
831 #define pb7cr 0x07 /* periph bank 7 config reg */
832 #define pb0ap 0x10 /* periph bank 0 access parameters */
833 #define pb1ap 0x11 /* periph bank 1 access parameters */
834 #define pb2ap 0x12 /* periph bank 2 access parameters */
835 #define pb3ap 0x13 /* periph bank 3 access parameters */
836 #define pb4ap 0x14 /* periph bank 4 access parameters */
837 #define pb5ap 0x15 /* periph bank 5 access parameters */
838 #define pb6ap 0x16 /* periph bank 6 access parameters */
839 #define pb7ap 0x17 /* periph bank 7 access parameters */
840 #define pbear 0x20 /* periph bus error addr reg */
841 #define pbesr 0x21 /* periph bus error status reg */
842 #define xbcfg 0x23 /* external bus configuration reg */
843 #define EBC0_CFG 0x23 /* external bus configuration reg */
844 #define xbcid 0x24 /* external bus core id reg */
846 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
847 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
849 /* PLB4 to PLB3 Bridge OUT */
850 #define P4P3_DCR_BASE 0x020
851 #define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
852 #define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
853 #define p4p3_eadr (P4P3_DCR_BASE+0x2)
854 #define p4p3_euadr (P4P3_DCR_BASE+0x3)
855 #define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
856 #define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
857 #define p4p3_confg (P4P3_DCR_BASE+0x6)
858 #define p4p3_pic (P4P3_DCR_BASE+0x7)
859 #define p4p3_peir (P4P3_DCR_BASE+0x8)
860 #define p4p3_rev (P4P3_DCR_BASE+0xA)
862 /* PLB3 to PLB4 Bridge IN */
863 #define P3P4_DCR_BASE 0x030
864 #define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
865 #define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
866 #define p3p4_eadr (P3P4_DCR_BASE+0x2)
867 #define p3p4_euadr (P3P4_DCR_BASE+0x3)
868 #define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
869 #define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
870 #define p3p4_confg (P3P4_DCR_BASE+0x6)
871 #define p3p4_pic (P3P4_DCR_BASE+0x7)
872 #define p3p4_peir (P3P4_DCR_BASE+0x8)
873 #define p3p4_rev (P3P4_DCR_BASE+0xA)
876 #define PLB3_DCR_BASE 0x070
877 #define plb3_revid (PLB3_DCR_BASE+0x2)
878 #define plb3_besr (PLB3_DCR_BASE+0x3)
879 #define plb3_bear (PLB3_DCR_BASE+0x6)
880 #define plb3_acr (PLB3_DCR_BASE+0x7)
882 /* PLB4 Arbiter - PowerPC440EP Pass1 */
883 #define PLB4_DCR_BASE 0x080
884 #define plb4_acr (PLB4_DCR_BASE+0x1)
885 #define plb4_revid (PLB4_DCR_BASE+0x2)
886 #define plb4_besr (PLB4_DCR_BASE+0x4)
887 #define plb4_bearl (PLB4_DCR_BASE+0x6)
888 #define plb4_bearh (PLB4_DCR_BASE+0x7)
890 #define PLB4_ACR_WRP (0x80000000 >> 7)
892 /* Nebula PLB4 Arbiter - PowerPC440EP */
893 #define PLB_ARBITER_BASE 0x80
895 #define plb0_revid (PLB_ARBITER_BASE+ 0x00)
896 #define plb0_acr (PLB_ARBITER_BASE+ 0x01)
897 #define plb0_acr_ppm_mask 0xF0000000
898 #define plb0_acr_ppm_fixed 0x00000000
899 #define plb0_acr_ppm_fair 0xD0000000
900 #define plb0_acr_hbu_mask 0x08000000
901 #define plb0_acr_hbu_disabled 0x00000000
902 #define plb0_acr_hbu_enabled 0x08000000
903 #define plb0_acr_rdp_mask 0x06000000
904 #define plb0_acr_rdp_disabled 0x00000000
905 #define plb0_acr_rdp_2deep 0x02000000
906 #define plb0_acr_rdp_3deep 0x04000000
907 #define plb0_acr_rdp_4deep 0x06000000
908 #define plb0_acr_wrp_mask 0x01000000
909 #define plb0_acr_wrp_disabled 0x00000000
910 #define plb0_acr_wrp_2deep 0x01000000
912 #define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
913 #define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
914 #define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
915 #define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
916 #define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
918 #define plb1_acr (PLB_ARBITER_BASE+ 0x09)
919 #define plb1_acr_ppm_mask 0xF0000000
920 #define plb1_acr_ppm_fixed 0x00000000
921 #define plb1_acr_ppm_fair 0xD0000000
922 #define plb1_acr_hbu_mask 0x08000000
923 #define plb1_acr_hbu_disabled 0x00000000
924 #define plb1_acr_hbu_enabled 0x08000000
925 #define plb1_acr_rdp_mask 0x06000000
926 #define plb1_acr_rdp_disabled 0x00000000
927 #define plb1_acr_rdp_2deep 0x02000000
928 #define plb1_acr_rdp_3deep 0x04000000
929 #define plb1_acr_rdp_4deep 0x06000000
930 #define plb1_acr_wrp_mask 0x01000000
931 #define plb1_acr_wrp_disabled 0x00000000
932 #define plb1_acr_wrp_2deep 0x01000000
934 #define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
935 #define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
936 #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
937 #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
939 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
940 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
941 /* Pin Function Control Register 1 */
942 #define SDR0_PFC1 0x4101
943 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
944 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
945 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
946 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
947 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
948 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
949 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
950 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
951 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
952 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
953 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
954 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
955 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
956 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
957 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
958 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
959 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
960 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
961 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
962 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
963 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
964 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
965 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
966 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
968 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
969 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
970 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
971 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
973 /* USB Control Register */
974 #define SDR0_USB0 0x0320
975 #define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
976 #define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
977 #define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
978 #define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
979 #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
980 #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
982 /* Miscealleneaous Function Reg. */
983 #define SDR0_MFR 0x4300
984 #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
985 #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
986 #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
987 #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
988 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
989 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
990 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
991 #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
992 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
993 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
994 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
995 #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
996 #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
998 #define SDR0_MFR_ERRATA3_EN0 0x00800000
999 #define SDR0_MFR_ERRATA3_EN1 0x00400000
1000 #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
1001 #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1002 #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
1003 #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
1004 #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
1006 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
1008 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1009 #define SDR0_USB2D0CR 0x0320
1010 #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
1011 #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
1012 #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
1014 #define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
1015 #define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
1016 #define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
1018 #define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
1019 #define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
1020 #define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
1022 /* USB2 Host Control Register */
1023 #define SDR0_USB2H0CR 0x0340
1024 #define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
1025 #define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
1026 #define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
1027 #define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
1029 /* Pin Function Control Register 1 */
1030 #define SDR0_PFC1 0x4101
1031 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1032 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1033 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1035 #define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
1036 #define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
1037 #define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
1038 #define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
1039 #define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
1040 #define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
1041 #define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
1042 #define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
1044 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1045 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1046 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1047 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1048 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
1049 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
1050 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1051 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1052 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1053 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
1054 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
1055 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
1056 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
1057 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
1058 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
1059 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
1060 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
1061 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
1062 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
1063 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
1064 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
1066 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
1067 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
1068 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
1069 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
1071 /* Ethernet PLL Configuration Register */
1072 #define SDR0_PFC2 0x4102
1073 #define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
1074 #define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
1075 #define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
1076 #define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
1078 #define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
1079 #define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
1080 #define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
1081 #define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
1082 #define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
1083 #define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
1084 #define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
1085 #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
1087 #define SDR0_PFC4 0x4104
1089 /* USB2PHY0 Control Register */
1090 #define SDR0_USB2PHY0CR 0x4103
1091 #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
1092 #define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
1093 #define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
1095 #define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
1096 #define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
1097 #define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
1099 #define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
1100 #define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
1101 #define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
1103 #define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
1104 #define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
1105 #define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
1107 #define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
1108 #define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
1109 #define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
1111 #define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
1112 #define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
1113 #define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
1115 #define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
1116 #define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
1117 #define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
1119 #define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
1120 #define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
1121 #define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
1123 #define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
1124 #define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
1125 #define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
1127 #define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
1128 #define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
1129 #define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
1130 #define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
1132 /* Miscealleneaous Function Reg. */
1133 #define SDR0_MFR 0x4300
1134 #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
1135 #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
1136 #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
1137 #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
1138 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
1139 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
1140 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
1141 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
1142 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
1143 #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
1144 #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
1146 #define SDR0_MFR_ERRATA3_EN0 0x00800000
1147 #define SDR0_MFR_ERRATA3_EN1 0x00400000
1148 #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
1149 #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
1150 #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
1151 #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
1152 #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
1154 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
1156 /* CUST0 Customer Configuration Register0 */
1157 #define SDR0_CUST0 0x4000
1158 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
1159 #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
1160 #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
1161 #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
1163 #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
1164 #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
1165 #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
1167 #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
1168 #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
1169 #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
1171 #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
1172 #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
1173 #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
1175 #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
1176 #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
1177 #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
1179 #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
1180 #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
1181 #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
1183 #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
1184 #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
1185 #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
1187 #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
1188 #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
1189 #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
1191 #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
1192 #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
1193 #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
1194 #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
1195 #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
1196 #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
1197 #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
1199 /* CUST1 Customer Configuration Register1 */
1200 #define SDR0_CUST1 0x4002
1201 #define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
1202 #define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
1203 #define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
1205 /* Pin Function Control Register 0 */
1206 #define SDR0_PFC0 0x4100
1207 #define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
1208 #define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
1209 #define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
1210 #define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
1211 #define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
1213 /* Pin Function Control Register 1 */
1214 #define SDR0_PFC1 0x4101
1215 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
1216 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
1217 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
1218 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
1219 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
1220 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
1221 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
1222 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
1223 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
1224 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
1225 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
1226 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
1227 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
1228 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
1229 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
1230 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
1231 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
1232 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
1233 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
1234 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
1235 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
1236 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
1237 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
1238 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
1240 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
1241 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
1242 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
1243 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
1245 /*-----------------------------------------------------------------------------
1247 +----------------------------------------------------------------------------*/
1248 #define ISRAM0_DCR_BASE 0x380
1249 #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
1250 #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
1251 #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
1252 #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
1253 #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
1254 #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
1255 #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
1256 #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
1260 /*-----------------------------------------------------------------------------
1262 +----------------------------------------------------------------------------*/
1263 #define ISRAM0_DCR_BASE 0x020
1264 #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
1265 #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
1266 #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
1267 #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
1268 #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
1269 #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
1270 #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
1271 #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
1272 #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
1273 #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
1274 #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
1276 /*-----------------------------------------------------------------------------
1278 +----------------------------------------------------------------------------*/
1279 #if defined (CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1280 #define L2_CACHE_BASE 0x030
1281 #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
1282 #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
1283 #define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
1284 #define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
1285 #define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
1286 #define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
1287 #define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
1288 #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
1290 #endif /* CONFIG_440GX */
1291 #endif /* !CONFIG_440EP !CONFIG_440GR*/
1293 /*-----------------------------------------------------------------------------
1295 +----------------------------------------------------------------------------*/
1296 /* TODO: as needed */
1298 /*-----------------------------------------------------------------------------
1299 | Clocking, Power Management and Chip Control
1300 +----------------------------------------------------------------------------*/
1301 #define CNTRL_DCR_BASE 0x0b0
1302 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1303 #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
1304 #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
1305 #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
1307 #define cpc0_sr (CNTRL_DCR_BASE+0x00) /* CPM status register */
1308 #define cpc0_er (CNTRL_DCR_BASE+0x01) /* CPM enable register */
1309 #define cpc0_fr (CNTRL_DCR_BASE+0x02) /* CPM force register */
1312 #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
1313 #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
1314 #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
1315 #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
1317 #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
1318 #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
1319 #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
1320 #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
1322 #define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
1324 #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
1325 #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
1327 /*-----------------------------------------------------------------------------
1328 | Universal interrupt controller
1329 +----------------------------------------------------------------------------*/
1330 #define UIC0_DCR_BASE 0xc0
1331 #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
1332 #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
1333 #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
1334 #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
1335 #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
1336 #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
1337 #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
1338 #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
1340 #define UIC1_DCR_BASE 0xd0
1341 #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
1342 #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
1343 #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
1344 #define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
1345 #define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
1346 #define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
1347 #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
1348 #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
1350 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1351 #define UIC2_DCR_BASE 0xe0
1352 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
1353 #define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
1354 #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
1355 #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
1356 #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
1357 #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
1358 #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
1359 #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
1360 #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
1362 #define UIC3_DCR_BASE 0xf0
1363 #define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
1364 #define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
1365 #define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
1366 #define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
1367 #define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
1368 #define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
1369 #define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
1370 #define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
1371 #define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
1372 #endif /* CONFIG_440SPE */
1374 #if defined(CONFIG_440GX)
1375 #define UIC2_DCR_BASE 0x210
1376 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
1377 #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
1378 #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
1379 #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
1380 #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
1381 #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
1382 #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
1383 #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
1386 #define UIC_DCR_BASE 0x200
1387 #define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
1388 #define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
1389 #define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
1390 #define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
1391 #define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
1392 #define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
1393 #define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
1394 #define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
1395 #endif /* CONFIG_440GX */
1397 /* The following is for compatibility with 405 code */
1398 #define uicsr uic0sr
1399 #define uicer uic0er
1400 #define uiccr uic0cr
1401 #define uicpr uic0pr
1402 #define uictr uic0tr
1403 #define uicmsr uic0msr
1404 #define uicvr uic0vr
1405 #define uicvcr uic0vcr
1407 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
1408 /*----------------------------------------------------------------------------+
1409 | Clock / Power-on-reset DCR's.
1410 +----------------------------------------------------------------------------*/
1411 #define CPR0_CLKUPD 0x20
1412 #define CPR0_CLKUPD_BSY_MASK 0x80000000
1413 #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
1414 #define CPR0_CLKUPD_BSY_BUSY 0x80000000
1415 #define CPR0_CLKUPD_CUI_MASK 0x80000000
1416 #define CPR0_CLKUPD_CUI_DISABLE 0x00000000
1417 #define CPR0_CLKUPD_CUI_ENABLE 0x80000000
1418 #define CPR0_CLKUPD_CUD_MASK 0x40000000
1419 #define CPR0_CLKUPD_CUD_DISABLE 0x00000000
1420 #define CPR0_CLKUPD_CUD_ENABLE 0x40000000
1422 #define CPR0_PLLC 0x40
1423 #define CPR0_PLLC_RST_MASK 0x80000000
1424 #define CPR0_PLLC_RST_PLLLOCKED 0x00000000
1425 #define CPR0_PLLC_RST_PLLRESET 0x80000000
1426 #define CPR0_PLLC_ENG_MASK 0x40000000
1427 #define CPR0_PLLC_ENG_DISABLE 0x00000000
1428 #define CPR0_PLLC_ENG_ENABLE 0x40000000
1429 #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1430 #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1431 #define CPR0_PLLC_SRC_MASK 0x20000000
1432 #define CPR0_PLLC_SRC_PLLOUTA 0x00000000
1433 #define CPR0_PLLC_SRC_PLLOUTB 0x20000000
1434 #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
1435 #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
1436 #define CPR0_PLLC_SEL_MASK 0x07000000
1437 #define CPR0_PLLC_SEL_PLLOUT 0x00000000
1438 #define CPR0_PLLC_SEL_CPU 0x01000000
1439 #define CPR0_PLLC_SEL_EBC 0x05000000
1440 #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1441 #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
1442 #define CPR0_PLLC_TUNE_MASK 0x000003FF
1443 #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
1444 #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
1446 #define CPR0_PLLD 0x60
1447 #define CPR0_PLLD_FBDV_MASK 0x1F000000
1448 #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
1449 #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
1450 #define CPR0_PLLD_FWDVA_MASK 0x000F0000
1451 #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
1452 #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
1453 #define CPR0_PLLD_FWDVB_MASK 0x00000700
1454 #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
1455 #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
1456 #define CPR0_PLLD_LFBDV_MASK 0x0000003F
1457 #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1458 #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1460 #define CPR0_PRIMAD 0x80
1461 #define CPR0_PRIMAD_PRADV0_MASK 0x07000000
1462 #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1463 #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1465 #define CPR0_PRIMBD 0xA0
1466 #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
1467 #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1468 #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1470 #define CPR0_OPBD 0xC0
1471 #define CPR0_OPBD_OPBDV0_MASK 0x03000000
1472 #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1473 #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1475 #define CPR0_PERD 0xE0
1476 #if !defined(CONFIG_440EPX)
1477 #define CPR0_PERD_PERDV0_MASK 0x03000000
1478 #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1479 #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1482 #define CPR0_MALD 0x100
1483 #define CPR0_MALD_MALDV0_MASK 0x03000000
1484 #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1485 #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1487 #define CPR0_ICFG 0x140
1488 #define CPR0_ICFG_RLI_MASK 0x80000000
1489 #define CPR0_ICFG_RLI_RESETCPR 0x00000000
1490 #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
1491 #define CPR0_ICFG_ICS_MASK 0x00000007
1492 #define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1493 #define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1495 /************************/
1497 /************************/
1498 #define IIC0_MMIO_BASE 0xA0000400
1499 #define IIC1_MMIO_BASE 0xA0000500
1501 #endif /* CONFIG_440SP */
1503 /*-----------------------------------------------------------------------------
1505 +----------------------------------------------------------------------------*/
1506 #define DMA_DCR_BASE 0x100
1507 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
1508 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
1509 #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
1510 #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
1511 #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
1512 #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
1513 #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
1514 #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
1515 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
1516 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
1517 #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
1518 #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
1519 #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
1520 #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
1521 #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
1522 #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
1523 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
1524 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
1525 #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
1526 #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
1527 #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
1528 #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
1529 #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
1530 #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
1531 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
1532 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
1533 #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
1534 #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
1535 #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
1536 #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
1537 #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
1538 #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
1539 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
1540 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
1541 #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
1542 #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
1544 /*-----------------------------------------------------------------------------
1545 | Memory Access Layer
1546 +----------------------------------------------------------------------------*/
1547 #define MAL_DCR_BASE 0x180
1548 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
1549 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
1550 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
1551 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
1552 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
1553 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
1554 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
1555 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
1556 #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
1557 #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
1558 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
1559 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
1560 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
1561 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
1562 #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
1563 #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
1564 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
1565 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
1566 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
1567 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
1568 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
1569 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
1570 #if defined(CONFIG_440GX)
1571 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
1572 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
1573 #endif /* CONFIG_440GX */
1574 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
1575 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
1576 #if defined(CONFIG_440GX)
1577 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
1578 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
1579 #endif /* CONFIG_440GX */
1582 /*---------------------------------------------------------------------------+
1583 | Universal interrupt controller 0 interrupts (UIC0)
1584 +---------------------------------------------------------------------------*/
1585 #if defined(CONFIG_440SP)
1586 #define UIC_U0 0x80000000 /* UART 0 */
1587 #define UIC_U1 0x40000000 /* UART 1 */
1588 #define UIC_IIC0 0x20000000 /* IIC */
1589 #define UIC_IIC1 0x10000000 /* IIC */
1590 #define UIC_PIM 0x08000000 /* PCI0 inbound message */
1591 #define UIC_PCRW 0x04000000 /* PCI0 command write register */
1592 #define UIC_PPM 0x02000000 /* PCI0 power management */
1593 #define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
1594 #define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
1595 #define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
1596 #define UIC_P1CRW 0x00200000 /* PCI1 command write register */
1597 #define UIC_P1PM 0x00100000 /* PCI1 power management */
1598 #define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
1599 #define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
1600 #define UIC_P2IM 0x00020000 /* PCI2 inbound message */
1601 #define UIC_P2CRW 0x00010000 /* PCI2 command register write */
1602 #define UIC_P2PM 0x00008000 /* PCI2 power management */
1603 #define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
1604 #define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
1605 #define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
1606 #define UIC_D0CSF 0x00000800 /* DMA0 command status */
1607 #define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
1608 #define UIC_D1CSF 0x00000200 /* DMA1 command status */
1609 #define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
1610 #define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
1611 #define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
1612 #define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
1613 #define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
1614 #define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
1615 #define UIC_GPTCT 0x00000004 /* GPT count timer */
1616 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1617 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1618 #elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
1619 #define UIC_U0 0x80000000 /* UART 0 */
1620 #define UIC_U1 0x40000000 /* UART 1 */
1621 #define UIC_IIC0 0x20000000 /* IIC */
1622 #define UIC_IIC1 0x10000000 /* IIC */
1623 #define UIC_PIM 0x08000000 /* PCI inbound message */
1624 #define UIC_PCRW 0x04000000 /* PCI command register write */
1625 #define UIC_PPM 0x02000000 /* PCI power management */
1626 #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
1627 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
1628 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
1629 #define UIC_MTE 0x00200000 /* MAL TXEOB */
1630 #define UIC_MRE 0x00100000 /* MAL RXEOB */
1631 #define UIC_D0 0x00080000 /* DMA channel 0 */
1632 #define UIC_D1 0x00040000 /* DMA channel 1 */
1633 #define UIC_D2 0x00020000 /* DMA channel 2 */
1634 #define UIC_D3 0x00010000 /* DMA channel 3 */
1635 #define UIC_RSVD0 0x00008000 /* Reserved */
1636 #define UIC_RSVD1 0x00004000 /* Reserved */
1637 #define UIC_CT0 0x00002000 /* GPT compare timer 0 */
1638 #define UIC_CT1 0x00001000 /* GPT compare timer 1 */
1639 #define UIC_CT2 0x00000800 /* GPT compare timer 2 */
1640 #define UIC_CT3 0x00000400 /* GPT compare timer 3 */
1641 #define UIC_CT4 0x00000200 /* GPT compare timer 4 */
1642 #define UIC_EIR0 0x00000100 /* External interrupt 0 */
1643 #define UIC_EIR1 0x00000080 /* External interrupt 1 */
1644 #define UIC_EIR2 0x00000040 /* External interrupt 2 */
1645 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
1646 #define UIC_EIR4 0x00000010 /* External interrupt 4 */
1647 #define UIC_EIR5 0x00000008 /* External interrupt 5 */
1648 #define UIC_EIR6 0x00000004 /* External interrupt 6 */
1649 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1650 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1652 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1654 #define UIC_U0 0x80000000 /* UART 0 */
1655 #define UIC_U1 0x40000000 /* UART 1 */
1656 #define UIC_IIC0 0x20000000 /* IIC */
1657 #define UIC_KRD 0x10000000 /* Kasumi Ready for data */
1658 #define UIC_KDA 0x08000000 /* Kasumi Data Available */
1659 #define UIC_PCRW 0x04000000 /* PCI command register write */
1660 #define UIC_PPM 0x02000000 /* PCI power management */
1661 #define UIC_IIC1 0x01000000 /* IIC */
1662 #define UIC_SPI 0x00800000 /* SPI */
1663 #define UIC_EPCISER 0x00400000 /* External PCI SERR */
1664 #define UIC_MTE 0x00200000 /* MAL TXEOB */
1665 #define UIC_MRE 0x00100000 /* MAL RXEOB */
1666 #define UIC_D0 0x00080000 /* DMA channel 0 */
1667 #define UIC_D1 0x00040000 /* DMA channel 1 */
1668 #define UIC_D2 0x00020000 /* DMA channel 2 */
1669 #define UIC_D3 0x00010000 /* DMA channel 3 */
1670 #define UIC_UD0 0x00008000 /* UDMA irq 0 */
1671 #define UIC_UD1 0x00004000 /* UDMA irq 1 */
1672 #define UIC_UD2 0x00002000 /* UDMA irq 2 */
1673 #define UIC_UD3 0x00001000 /* UDMA irq 3 */
1674 #define UIC_HSB2D 0x00000800 /* USB2.0 Device */
1675 #define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */
1676 #define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */
1677 #define UIC_EIP94 0x00000100 /* Security EIP94 */
1678 #define UIC_ETH0 0x00000080 /* Emac 0 */
1679 #define UIC_ETH1 0x00000040 /* Emac 1 */
1680 #define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */
1681 #define UIC_EIR4 0x00000010 /* External interrupt 4 */
1682 #define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */
1683 #define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */
1684 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1685 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1687 /* For compatibility with 405 code */
1688 #define UIC_MAL_TXEOB UIC_MTE
1689 #define UIC_MAL_RXEOB UIC_MRE
1691 #elif !defined(CONFIG_440SPE)
1692 #define UIC_U0 0x80000000 /* UART 0 */
1693 #define UIC_U1 0x40000000 /* UART 1 */
1694 #define UIC_IIC0 0x20000000 /* IIC */
1695 #define UIC_IIC1 0x10000000 /* IIC */
1696 #define UIC_PIM 0x08000000 /* PCI inbound message */
1697 #define UIC_PCRW 0x04000000 /* PCI command register write */
1698 #define UIC_PPM 0x02000000 /* PCI power management */
1699 #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
1700 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
1701 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
1702 #define UIC_MTE 0x00200000 /* MAL TXEOB */
1703 #define UIC_MRE 0x00100000 /* MAL RXEOB */
1704 #define UIC_D0 0x00080000 /* DMA channel 0 */
1705 #define UIC_D1 0x00040000 /* DMA channel 1 */
1706 #define UIC_D2 0x00020000 /* DMA channel 2 */
1707 #define UIC_D3 0x00010000 /* DMA channel 3 */
1708 #define UIC_RSVD0 0x00008000 /* Reserved */
1709 #define UIC_RSVD1 0x00004000 /* Reserved */
1710 #define UIC_CT0 0x00002000 /* GPT compare timer 0 */
1711 #define UIC_CT1 0x00001000 /* GPT compare timer 1 */
1712 #define UIC_CT2 0x00000800 /* GPT compare timer 2 */
1713 #define UIC_CT3 0x00000400 /* GPT compare timer 3 */
1714 #define UIC_CT4 0x00000200 /* GPT compare timer 4 */
1715 #define UIC_EIR0 0x00000100 /* External interrupt 0 */
1716 #define UIC_EIR1 0x00000080 /* External interrupt 1 */
1717 #define UIC_EIR2 0x00000040 /* External interrupt 2 */
1718 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
1719 #define UIC_EIR4 0x00000010 /* External interrupt 4 */
1720 #define UIC_EIR5 0x00000008 /* External interrupt 5 */
1721 #define UIC_EIR6 0x00000004 /* External interrupt 6 */
1722 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1723 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1724 #endif /* CONFIG_440GX */
1726 /* For compatibility with 405 code */
1727 #define UIC_MAL_TXEOB UIC_MTE
1728 #define UIC_MAL_RXEOB UIC_MRE
1730 /*---------------------------------------------------------------------------+
1731 | Universal interrupt controller 1 interrupts (UIC1)
1732 +---------------------------------------------------------------------------*/
1733 #if defined(CONFIG_440SP)
1734 #define UIC_EIR0 0x80000000 /* External interrupt 0 */
1735 #define UIC_MS 0x40000000 /* MAL SERR */
1736 #define UIC_MTDE 0x20000000 /* MAL TXDE */
1737 #define UIC_MRDE 0x10000000 /* MAL RXDE */
1738 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1739 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1740 #define UIC_MTE 0x02000000 /* MAL TXEOB */
1741 #define UIC_MRE 0x01000000 /* MAL RXEOB */
1742 #define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
1743 #define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
1744 #define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
1745 #define UIC_L2C 0x00100000 /* L2 cache */
1746 #define UIC_CT0 0x00080000 /* GPT compare timer 0 */
1747 #define UIC_CT1 0x00040000 /* GPT compare timer 1 */
1748 #define UIC_CT2 0x00020000 /* GPT compare timer 2 */
1749 #define UIC_CT3 0x00010000 /* GPT compare timer 3 */
1750 #define UIC_CT4 0x00008000 /* GPT compare timer 4 */
1751 #define UIC_EIR1 0x00004000 /* External interrupt 1 */
1752 #define UIC_EIR2 0x00002000 /* External interrupt 2 */
1753 #define UIC_EIR3 0x00001000 /* External interrupt 3 */
1754 #define UIC_EIR4 0x00000800 /* External interrupt 4 */
1755 #define UIC_EIR5 0x00000400 /* External interrupt 5 */
1756 #define UIC_DMAE 0x00000200 /* DMA error */
1757 #define UIC_I2OE 0x00000100 /* I2O error */
1758 #define UIC_SRE 0x00000080 /* Serial ROM error */
1759 #define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
1760 #define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
1761 #define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
1762 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1763 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1764 #define UIC_ETH1 0x00000002 /* Reserved */
1765 #define UIC_XOR 0x00000001 /* XOR */
1766 #elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
1767 #define UIC_MS 0x80000000 /* MAL SERR */
1768 #define UIC_MTDE 0x40000000 /* MAL TXDE */
1769 #define UIC_MRDE 0x20000000 /* MAL RXDE */
1770 #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
1771 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1772 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1773 #define UIC_EBMI 0x02000000 /* EBMI interrupt status */
1774 #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
1775 #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
1776 #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
1777 #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
1778 #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
1779 #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
1780 #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
1781 #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
1782 #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
1783 #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
1784 #define UIC_PPMI 0x00004000 /* PPM interrupt status */
1785 #define UIC_EIR7 0x00002000 /* External interrupt 7 */
1786 #define UIC_EIR8 0x00001000 /* External interrupt 8 */
1787 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
1788 #define UIC_EIR10 0x00000400 /* External interrupt 10 */
1789 #define UIC_EIR11 0x00000200 /* External interrupt 11 */
1790 #define UIC_EIR12 0x00000100 /* External interrupt 12 */
1791 #define UIC_SRE 0x00000080 /* Serial ROM error */
1792 #define UIC_RSVD2 0x00000040 /* Reserved */
1793 #define UIC_RSVD3 0x00000020 /* Reserved */
1794 #define UIC_PAE 0x00000010 /* PCI asynchronous error */
1795 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1796 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1797 #define UIC_ETH1 0x00000002 /* Ethernet 1 */
1798 #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
1800 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1802 #define UIC_MS 0x80000000 /* MAL SERR */
1803 #define UIC_MTDE 0x40000000 /* MAL TXDE */
1804 #define UIC_MRDE 0x20000000 /* MAL RXDE */
1805 #define UIC_U2 0x10000000 /* UART 2 */
1806 #define UIC_U3 0x08000000 /* UART 3 */
1807 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1808 #define UIC_NDFC 0x02000000 /* NDFC */
1809 #define UIC_KSLE 0x01000000 /* KASUMI slave error */
1810 #define UIC_CT5 0x00800000 /* GPT compare timer 5 */
1811 #define UIC_CT6 0x00400000 /* GPT compare timer 6 */
1812 #define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */
1813 #define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */
1814 #define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */
1815 #define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */
1816 #define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */
1817 #define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */
1818 #define UIC_CT0 0x00008000 /* GPT compare timer 0 */
1819 #define UIC_CT1 0x00004000 /* GPT compare timer 1 */
1820 #define UIC_EIR7 0x00002000 /* External interrupt 7 */
1821 #define UIC_EIR8 0x00001000 /* External interrupt 8 */
1822 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
1823 #define UIC_CT2 0x00000400 /* GPT compare timer 2 */
1824 #define UIC_CT3 0x00000200 /* GPT compare timer 3 */
1825 #define UIC_CT4 0x00000100 /* GPT compare timer 4 */
1826 #define UIC_SRE 0x00000080 /* Serial ROM error */
1827 #define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */
1828 #define UIC_RSVD0 0x00000020 /* Reserved */
1829 #define UIC_EPCIPER 0x00000010 /* External PCI PERR */
1830 #define UIC_EIR0 0x00000008 /* External interrupt 0 */
1831 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1832 #define UIC_EIR1 0x00000002 /* External interrupt 1 */
1833 #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
1835 /* For compatibility with 405 code */
1836 #define UIC_MAL_SERR UIC_MS
1837 #define UIC_MAL_TXDE UIC_MTDE
1838 #define UIC_MAL_RXDE UIC_MRDE
1839 #define UIC_ENET UIC_ETH0
1841 #elif !defined(CONFIG_440SPE)
1842 #define UIC_MS 0x80000000 /* MAL SERR */
1843 #define UIC_MTDE 0x40000000 /* MAL TXDE */
1844 #define UIC_MRDE 0x20000000 /* MAL RXDE */
1845 #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
1846 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1847 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1848 #define UIC_EBMI 0x02000000 /* EBMI interrupt status */
1849 #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
1850 #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
1851 #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
1852 #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
1853 #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
1854 #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
1855 #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
1856 #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
1857 #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
1858 #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
1859 #define UIC_PPMI 0x00004000 /* PPM interrupt status */
1860 #define UIC_EIR7 0x00002000 /* External interrupt 7 */
1861 #define UIC_EIR8 0x00001000 /* External interrupt 8 */
1862 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
1863 #define UIC_EIR10 0x00000400 /* External interrupt 10 */
1864 #define UIC_EIR11 0x00000200 /* External interrupt 11 */
1865 #define UIC_EIR12 0x00000100 /* External interrupt 12 */
1866 #define UIC_SRE 0x00000080 /* Serial ROM error */
1867 #define UIC_RSVD2 0x00000040 /* Reserved */
1868 #define UIC_RSVD3 0x00000020 /* Reserved */
1869 #define UIC_PAE 0x00000010 /* PCI asynchronous error */
1870 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1871 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1872 #define UIC_ETH1 0x00000002 /* Ethernet 1 */
1873 #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
1874 #endif /* CONFIG_440SP */
1876 /* For compatibility with 405 code */
1877 #define UIC_MAL_SERR UIC_MS
1878 #define UIC_MAL_TXDE UIC_MTDE
1879 #define UIC_MAL_RXDE UIC_MRDE
1880 #define UIC_ENET UIC_ETH0
1882 /*---------------------------------------------------------------------------+
1883 | Universal interrupt controller 2 interrupts (UIC2)
1884 +---------------------------------------------------------------------------*/
1885 #if defined(CONFIG_440GX)
1886 #define UIC_ETH2 0x80000000 /* Ethernet 2 */
1887 #define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
1888 #define UIC_ETH3 0x20000000 /* Ethernet 3 */
1889 #define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */
1890 #define UIC_TAH0 0x08000000 /* TAH 0 */
1891 #define UIC_TAH1 0x04000000 /* TAH 1 */
1892 #define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */
1893 #define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */
1894 #define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */
1895 #define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */
1896 #define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */
1897 #define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */
1898 #define UIC_IMUTO 0x00080000 /* IMU timeout */
1899 #define UIC_MSI12 0x00040000 /* PCI MSI level 12 */
1900 #define UIC_MSI13 0x00020000 /* PCI MSI level 13 */
1901 #define UIC_MSI14 0x00010000 /* PCI MSI level 14 */
1902 #define UIC_MSI15 0x00008000 /* PCI MSI level 15 */
1903 #define UIC_EIR13 0x00004000 /* External interrupt 13 */
1904 #define UIC_EIR14 0x00002000 /* External interrupt 14 */
1905 #define UIC_EIR15 0x00001000 /* External interrupt 15 */
1906 #define UIC_EIR16 0x00000800 /* External interrupt 16 */
1907 #define UIC_EIR17 0x00000400 /* External interrupt 17 */
1908 #define UIC_PCIVPD 0x00000200 /* PCI VPD */
1909 #define UIC_L2C 0x00000100 /* L2 Cache */
1910 #define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */
1911 #define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */
1912 #define UIC_RSVD26 0x00000020 /* Reserved */
1913 #define UIC_RSVD27 0x00000010 /* Reserved */
1914 #define UIC_RSVD28 0x00000008 /* Reserved */
1915 #define UIC_RSVD29 0x00000004 /* Reserved */
1916 #define UIC_RSVD30 0x00000002 /* Reserved */
1917 #define UIC_RSVD31 0x00000001 /* Reserved */
1919 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
1921 #define UIC_EIR5 0x80000000 /* External interrupt 5 */
1922 #define UIC_EIR6 0x40000000 /* External interrupt 6 */
1923 #define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */
1924 #define UIC_EIR2 0x10000000 /* External interrupt 2 */
1925 #define UIC_EIR3 0x08000000 /* External interrupt 3 */
1926 #define UIC_DDR2 0x04000000 /* DDR2 sdram */
1927 #define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */
1928 #define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */
1929 #define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */
1930 #define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */
1932 #endif /* CONFIG_440GX */
1934 /*---------------------------------------------------------------------------+
1935 | Universal interrupt controller Base 0 interrupts (UICB0)
1936 +---------------------------------------------------------------------------*/
1937 #if defined(CONFIG_440GX)
1938 #define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
1939 #define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
1940 #define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
1941 #define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */
1942 #define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */
1943 #define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */
1945 #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
1946 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
1948 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1950 #define UICB0_UIC1CI 0x00000000 /* UIC1 Critical Interrupt */
1951 #define UICB0_UIC1NCI 0x00000000 /* UIC1 Noncritical Interrupt */
1952 #define UICB0_UIC2CI 0x00000000 /* UIC2 Critical Interrupt */
1953 #define UICB0_UIC2NCI 0x00000000 /* UIC2 Noncritical Interrupt */
1955 #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
1956 UICB0_UIC1CI | UICB0_UIC2NCI)
1958 #endif /* CONFIG_440GX */
1959 /*---------------------------------------------------------------------------+
1960 | Universal interrupt controller interrupts
1961 +---------------------------------------------------------------------------*/
1962 #if defined(CONFIG_440SPE)
1963 /*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */
1964 /*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */
1965 #define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */
1966 #define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */
1967 #define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */
1968 #define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */
1969 #define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */
1970 #define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */
1972 #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
1973 UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
1974 /*---------------------------------------------------------------------------+
1975 | Universal interrupt controller 0 interrupts (UIC0)
1976 +---------------------------------------------------------------------------*/
1977 #define UIC_U0 0x80000000 /* UART 0 */
1978 #define UIC_U1 0x40000000 /* UART 1 */
1979 #define UIC_IIC0 0x20000000 /* IIC */
1980 #define UIC_IIC1 0x10000000 /* IIC */
1981 #define UIC_PIM 0x08000000 /* PCI inbound message */
1982 #define UIC_PCRW 0x04000000 /* PCI command register write */
1983 #define UIC_PPM 0x02000000 /* PCI power management */
1984 #define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */
1985 #define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */
1986 #define UIC_EIR15 0x00400000 /* External intp 15 */
1987 #define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */
1988 #define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */
1989 #define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */
1990 #define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */
1991 #define UIC_EIR14 0x00002000 /* External interrupt 14 */
1992 #define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */
1993 #define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */
1994 #define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
1995 #define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
1996 #define UIC_I2OID 0x00000100 /* I2O inbound door bell */
1997 #define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
1998 #define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
1999 #define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
2000 #define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
2001 #define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
2002 #define UIC_CPTCNT 0x00000004 /* GPT Count Timer */
2003 /*---------------------------------------------------------------------------+
2004 | Universal interrupt controller 1 interrupts (UIC1)
2005 +---------------------------------------------------------------------------*/
2006 #define UIC_EIR13 0x80000000 /* externei intp 13 */
2007 #define UIC_MS 0x40000000 /* MAL SERR */
2008 #define UIC_MTDE 0x20000000 /* MAL TXDE */
2009 #define UIC_MRDE 0x10000000 /* MAL RXDE */
2010 #define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
2011 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
2012 #define UIC_MTE 0x02000000 /* MAL TXEOB */
2013 #define UIC_MRE 0x01000000 /* MAL RXEOB */
2014 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
2015 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
2016 #define UIC_MSI3 0x00200000 /* PCI MSI level 3 */
2017 #define UIC_L2C 0x00100000 /* L2 cache */
2018 #define UIC_CT0 0x00080000 /* GPT compare timer 0 */
2019 #define UIC_CT1 0x00040000 /* GPT compare timer 1 */
2020 #define UIC_CT2 0x00020000 /* GPT compare timer 2 */
2021 #define UIC_CT3 0x00010000 /* GPT compare timer 3 */
2022 #define UIC_CT4 0x00008000 /* GPT compare timer 4 */
2023 #define UIC_EIR12 0x00004000 /* External interrupt 12 */
2024 #define UIC_EIR11 0x00002000 /* External interrupt 11 */
2025 #define UIC_EIR10 0x00001000 /* External interrupt 10 */
2026 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
2027 #define UIC_EIR8 0x00000400 /* External interrupt 8 */
2028 #define UIC_DMAE 0x00000200 /* dma error */
2029 #define UIC_I2OE 0x00000100 /* i2o error */
2030 #define UIC_SRE 0x00000080 /* Serial ROM error */
2031 #define UIC_PCIXAE 0x00000040 /* Pcix0 async error */
2032 #define UIC_EIR7 0x00000020 /* External interrupt 7 */
2033 #define UIC_EIR6 0x00000010 /* External interrupt 6 */
2034 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
2035 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
2036 #define UIC_ETH1 0x00000002 /* reserved */
2037 #define UIC_XOR 0x00000001 /* xor */
2039 /*---------------------------------------------------------------------------+
2040 | Universal interrupt controller 2 interrupts (UIC2)
2041 +---------------------------------------------------------------------------*/
2042 #define UIC_PEOAL 0x80000000 /* PE0 AL */
2043 #define UIC_PEOVA 0x40000000 /* PE0 VPD access */
2044 #define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */
2045 #define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */
2046 #define UIC_PE0TCR 0x08000000 /* PE0 TCR */
2047 #define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */
2048 #define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */
2049 #define UIC_PE1AL 0x00800000 /* PE1 AL */
2050 #define UIC_PE1VA 0x00400000 /* PE1 VPD access */
2051 #define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */
2052 #define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */
2053 #define UIC_PE1TCR 0x00080000 /* PE1 TCR */
2054 #define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */
2055 #define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */
2056 #define UIC_PE2AL 0x00008000 /* PE2 AL */
2057 #define UIC_PE2VA 0x00004000 /* PE2 VPD access */
2058 #define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */
2059 #define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */
2060 #define UIC_PE2TCR 0x00000800 /* PE2 TCR */
2061 #define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */
2062 #define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */
2063 #define UIC_EIR5 0x00000080 /* External interrupt 5 */
2064 #define UIC_EIR4 0x00000040 /* External interrupt 4 */
2065 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
2066 #define UIC_EIR2 0x00000010 /* External interrupt 2 */
2067 #define UIC_EIR1 0x00000008 /* External interrupt 1 */
2068 #define UIC_EIR0 0x00000004 /* External interrupt 0 */
2069 #endif /* CONFIG_440SPE */
2071 /*-----------------------------------------------------------------------------+
2072 | External Bus Controller Bit Settings
2073 +-----------------------------------------------------------------------------*/
2074 #define EBC_CFGADDR_MASK 0x0000003F
2076 #define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
2077 #define EBC_BXCR_BS_MASK 0x000E0000
2078 #define EBC_BXCR_BS_1MB 0x00000000
2079 #define EBC_BXCR_BS_2MB 0x00020000
2080 #define EBC_BXCR_BS_4MB 0x00040000
2081 #define EBC_BXCR_BS_8MB 0x00060000
2082 #define EBC_BXCR_BS_16MB 0x00080000
2083 #define EBC_BXCR_BS_32MB 0x000A0000
2084 #define EBC_BXCR_BS_64MB 0x000C0000
2085 #define EBC_BXCR_BS_128MB 0x000E0000
2086 #define EBC_BXCR_BU_MASK 0x00018000
2087 #define EBC_BXCR_BU_R 0x00008000
2088 #define EBC_BXCR_BU_W 0x00010000
2089 #define EBC_BXCR_BU_RW 0x00018000
2090 #define EBC_BXCR_BW_MASK 0x00006000
2091 #define EBC_BXCR_BW_8BIT 0x00000000
2092 #define EBC_BXCR_BW_16BIT 0x00002000
2093 #define EBC_BXCR_BW_32BIT 0x00006000
2094 #define EBC_BXAP_BME_ENABLED 0x80000000
2095 #define EBC_BXAP_BME_DISABLED 0x00000000
2096 #define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
2097 #define EBC_BXAP_BCE_DISABLE 0x00000000
2098 #define EBC_BXAP_BCE_ENABLE 0x00400000
2099 #define EBC_BXAP_BCT_MASK 0x00300000
2100 #define EBC_BXAP_BCT_2TRANS 0x00000000
2101 #define EBC_BXAP_BCT_4TRANS 0x00100000
2102 #define EBC_BXAP_BCT_8TRANS 0x00200000
2103 #define EBC_BXAP_BCT_16TRANS 0x00300000
2104 #define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
2105 #define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
2106 #define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
2107 #define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12)
2108 #define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9)
2109 #define EBC_BXAP_RE_ENABLED 0x00000100
2110 #define EBC_BXAP_RE_DISABLED 0x00000000
2111 #define EBC_BXAP_SOR_DELAYED 0x00000000
2112 #define EBC_BXAP_SOR_NONDELAYED 0x00000080
2113 #define EBC_BXAP_BEM_WRITEONLY 0x00000000
2114 #define EBC_BXAP_BEM_RW 0x00000040
2115 #define EBC_BXAP_PEN_DISABLED 0x00000000
2117 #define EBC_CFG_LE_MASK 0x80000000
2118 #define EBC_CFG_LE_UNLOCK 0x00000000
2119 #define EBC_CFG_LE_LOCK 0x80000000
2120 #define EBC_CFG_PTD_MASK 0x40000000
2121 #define EBC_CFG_PTD_ENABLE 0x00000000
2122 #define EBC_CFG_PTD_DISABLE 0x40000000
2123 #define EBC_CFG_RTC_MASK 0x38000000
2124 #define EBC_CFG_RTC_16PERCLK 0x00000000
2125 #define EBC_CFG_RTC_32PERCLK 0x08000000
2126 #define EBC_CFG_RTC_64PERCLK 0x10000000
2127 #define EBC_CFG_RTC_128PERCLK 0x18000000
2128 #define EBC_CFG_RTC_256PERCLK 0x20000000
2129 #define EBC_CFG_RTC_512PERCLK 0x28000000
2130 #define EBC_CFG_RTC_1024PERCLK 0x30000000
2131 #define EBC_CFG_RTC_2048PERCLK 0x38000000
2132 #define EBC_CFG_ATC_MASK 0x04000000
2133 #define EBC_CFG_ATC_HI 0x00000000
2134 #define EBC_CFG_ATC_PREVIOUS 0x04000000
2135 #define EBC_CFG_DTC_MASK 0x02000000
2136 #define EBC_CFG_DTC_HI 0x00000000
2137 #define EBC_CFG_DTC_PREVIOUS 0x02000000
2138 #define EBC_CFG_CTC_MASK 0x01000000
2139 #define EBC_CFG_CTC_HI 0x00000000
2140 #define EBC_CFG_CTC_PREVIOUS 0x01000000
2141 #define EBC_CFG_OEO_MASK 0x00800000
2142 #define EBC_CFG_OEO_HI 0x00000000
2143 #define EBC_CFG_OEO_PREVIOUS 0x00800000
2144 #define EBC_CFG_EMC_MASK 0x00400000
2145 #define EBC_CFG_EMC_NONDEFAULT 0x00000000
2146 #define EBC_CFG_EMC_DEFAULT 0x00400000
2147 #define EBC_CFG_PME_MASK 0x00200000
2148 #define EBC_CFG_PME_DISABLE 0x00000000
2149 #define EBC_CFG_PME_ENABLE 0x00200000
2150 #define EBC_CFG_PMT_MASK 0x001F0000
2151 #define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
2152 #define EBC_CFG_PR_MASK 0x0000C000
2153 #define EBC_CFG_PR_16 0x00000000
2154 #define EBC_CFG_PR_32 0x00004000
2155 #define EBC_CFG_PR_64 0x00008000
2156 #define EBC_CFG_PR_128 0x0000C000
2158 /*-----------------------------------------------------------------------------+
2160 +-----------------------------------------------------------------------------*/
2161 #if defined(CONFIG_440SP)
2162 #define SDR0_SRST 0x0200
2164 #define SDR0_DDR0 0x00E1
2165 #define SDR0_DDR0_DPLLRST 0x80000000
2166 #define SDR0_DDR0_DDRM_MASK 0x60000000
2167 #define SDR0_DDR0_DDRM_DDR1 0x20000000
2168 #define SDR0_DDR0_DDRM_DDR2 0x40000000
2169 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
2170 #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
2171 #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
2172 #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
2175 #if defined(CONFIG_440SPE)
2176 #define SDR0_CP440 0x0180
2177 #define SDR0_CP440_ERPN_MASK 0x30000000
2178 #define SDR0_CP440_ERPN_MASK_HI 0x3000
2179 #define SDR0_CP440_ERPN_MASK_LO 0x0000
2180 #define SDR0_CP440_ERPN_EBC 0x10000000
2181 #define SDR0_CP440_ERPN_EBC_HI 0x1000
2182 #define SDR0_CP440_ERPN_EBC_LO 0x0000
2183 #define SDR0_CP440_ERPN_PCI 0x20000000
2184 #define SDR0_CP440_ERPN_PCI_HI 0x2000
2185 #define SDR0_CP440_ERPN_PCI_LO 0x0000
2186 #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
2187 #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
2188 #define SDR0_CP440_NTO1_MASK 0x00000002
2189 #define SDR0_CP440_NTO1_NTOP 0x00000000
2190 #define SDR0_CP440_NTO1_NTO1 0x00000002
2191 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
2192 #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
2194 #define SDR0_SDSTP0 0x0020
2195 #define SDR0_SDSTP0_ENG_MASK 0x80000000
2196 #define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
2197 #define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
2198 #define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2199 #define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2200 #define SDR0_SDSTP0_SRC_MASK 0x40000000
2201 #define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
2202 #define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
2203 #define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2204 #define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2205 #define SDR0_SDSTP0_SEL_MASK 0x38000000
2206 #define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
2207 #define SDR0_SDSTP0_SEL_CPU 0x08000000
2208 #define SDR0_SDSTP0_SEL_EBC 0x28000000
2209 #define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
2210 #define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
2211 #define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
2212 #define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
2213 #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
2214 #define SDR0_SDSTP0_FBDV_MASK 0x0001F000
2215 #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
2216 #define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
2217 #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
2218 #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
2219 #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
2220 #define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
2221 #define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
2222 #define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
2223 #define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
2224 #define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
2225 #define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
2226 #define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
2227 #define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
2228 #define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
2231 #define SDR0_SDSTP1 0x0021
2232 #define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
2233 #define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
2234 #define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
2235 #define SDR0_SDSTP1_PERDV0_MASK 0x03000000
2236 #define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
2237 #define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
2238 #define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
2239 #define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
2240 #define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
2241 #define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
2242 #define SDR0_SDSTP1_DDR1_MODE 0x00100000
2243 #define SDR0_SDSTP1_DDR2_MODE 0x00200000
2244 #define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
2245 #define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
2246 #define SDR0_SDSTP1_ERPN_MASK 0x00080000
2247 #define SDR0_SDSTP1_ERPN_EBC 0x00000000
2248 #define SDR0_SDSTP1_ERPN_PCI 0x00080000
2249 #define SDR0_SDSTP1_PAE_MASK 0x00040000
2250 #define SDR0_SDSTP1_PAE_DISABLE 0x00000000
2251 #define SDR0_SDSTP1_PAE_ENABLE 0x00040000
2252 #define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
2253 #define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
2254 #define SDR0_SDSTP1_PHCE_MASK 0x00020000
2255 #define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
2256 #define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
2257 #define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
2258 #define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
2259 #define SDR0_SDSTP1_PISE_MASK 0x00010000
2260 #define SDR0_SDSTP1_PISE_DISABLE 0x00000000
2261 #define SDR0_SDSTP1_PISE_ENABLE 0x00001000
2262 #define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
2263 #define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
2264 #define SDR0_SDSTP1_PCWE_MASK 0x00008000
2265 #define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
2266 #define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
2267 #define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
2268 #define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
2269 #define SDR0_SDSTP1_PPIM_MASK 0x00007800
2270 #define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
2271 #define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
2272 #define SDR0_SDSTP1_PR64E_MASK 0x00000400
2273 #define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
2274 #define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
2275 #define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
2276 #define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
2277 #define SDR0_SDSTP1_PXFS_MASK 0x00000300
2278 #define SDR0_SDSTP1_PXFS_100_133 0x00000000
2279 #define SDR0_SDSTP1_PXFS_66_100 0x00000100
2280 #define SDR0_SDSTP1_PXFS_50_66 0x00000200
2281 #define SDR0_SDSTP1_PXFS_0_50 0x00000300
2282 #define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
2283 #define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
2284 #define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
2285 #define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
2286 #define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
2287 #define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
2288 #define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
2289 #define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
2290 #define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
2291 #define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
2292 #define SDR0_SDSTP1_ETH_MASK 0x00000004
2293 #define SDR0_SDSTP1_ETH_10_100 0x00000000
2294 #define SDR0_SDSTP1_ETH_GIGA 0x00000004
2295 #define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
2296 #define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
2297 #define SDR0_SDSTP1_NTO1_MASK 0x00000001
2298 #define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
2299 #define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
2300 #define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
2301 #define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
2303 #define SDR0_SDSTP2 0x0022
2304 #define SDR0_SDSTP2_P1AE_MASK 0x80000000
2305 #define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
2306 #define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
2307 #define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2308 #define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2309 #define SDR0_SDSTP2_P1HCE_MASK 0x40000000
2310 #define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
2311 #define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
2312 #define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2313 #define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2314 #define SDR0_SDSTP2_P1ISE_MASK 0x20000000
2315 #define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
2316 #define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
2317 #define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2318 #define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2319 #define SDR0_SDSTP2_P1CWE_MASK 0x10000000
2320 #define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
2321 #define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
2322 #define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2323 #define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2324 #define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
2325 #define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2326 #define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2327 #define SDR0_SDSTP2_P1R64E_MASK 0x00800000
2328 #define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
2329 #define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
2330 #define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2331 #define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2332 #define SDR0_SDSTP2_P1XFS_MASK 0x00600000
2333 #define SDR0_SDSTP2_P1XFS_100_133 0x00000000
2334 #define SDR0_SDSTP2_P1XFS_66_100 0x00200000
2335 #define SDR0_SDSTP2_P1XFS_50_66 0x00400000
2336 #define SDR0_SDSTP2_P1XFS_0_50 0x00600000
2337 #define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2338 #define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2339 #define SDR0_SDSTP2_P2AE_MASK 0x00040000
2340 #define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
2341 #define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
2342 #define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
2343 #define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
2344 #define SDR0_SDSTP2_P2HCE_MASK 0x00020000
2345 #define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
2346 #define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
2347 #define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
2348 #define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
2349 #define SDR0_SDSTP2_P2ISE_MASK 0x00010000
2350 #define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
2351 #define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
2352 #define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
2353 #define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
2354 #define SDR0_SDSTP2_P2CWE_MASK 0x00008000
2355 #define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
2356 #define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
2357 #define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
2358 #define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
2359 #define SDR0_SDSTP2_P2PIM_MASK 0x00007800
2360 #define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
2361 #define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
2362 #define SDR0_SDSTP2_P2XFS_MASK 0x00000300
2363 #define SDR0_SDSTP2_P2XFS_100_133 0x00000000
2364 #define SDR0_SDSTP2_P2XFS_66_100 0x00000100
2365 #define SDR0_SDSTP2_P2XFS_50_66 0x00000200
2366 #define SDR0_SDSTP2_P2XFS_0_50 0x00000100
2367 #define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
2368 #define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
2370 #define SDR0_SDSTP3 0x0023
2372 #define SDR0_PINSTP 0x0040
2373 #define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
2374 #define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
2375 #define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
2376 #define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
2377 #define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
2378 #define SDR0_SDCS 0x0060
2379 #define SDR0_ECID0 0x0080
2380 #define SDR0_ECID1 0x0081
2381 #define SDR0_ECID2 0x0082
2382 #define SDR0_JTAG 0x00C0
2384 #define SDR0_DDR0 0x00E1
2385 #define SDR0_DDR0_DPLLRST 0x80000000
2386 #define SDR0_DDR0_DDRM_MASK 0x60000000
2387 #define SDR0_DDR0_DDRM_DDR1 0x20000000
2388 #define SDR0_DDR0_DDRM_DDR2 0x40000000
2389 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
2390 #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
2391 #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
2392 #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
2394 #define SDR0_UART0 0x0120
2395 #define SDR0_UART1 0x0121
2396 #define SDR0_UART2 0x0122
2397 #define SDR0_UARTX_UXICS_MASK 0xF0000000
2398 #define SDR0_UARTX_UXICS_PLB 0x20000000
2399 #define SDR0_UARTX_UXEC_MASK 0x00800000
2400 #define SDR0_UARTX_UXEC_INT 0x00000000
2401 #define SDR0_UARTX_UXEC_EXT 0x00800000
2402 #define SDR0_UARTX_UXDIV_MASK 0x000000FF
2403 #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
2404 #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
2406 #define SDR0_CP440 0x0180
2407 #define SDR0_CP440_ERPN_MASK 0x30000000
2408 #define SDR0_CP440_ERPN_MASK_HI 0x3000
2409 #define SDR0_CP440_ERPN_MASK_LO 0x0000
2410 #define SDR0_CP440_ERPN_EBC 0x10000000
2411 #define SDR0_CP440_ERPN_EBC_HI 0x1000
2412 #define SDR0_CP440_ERPN_EBC_LO 0x0000
2413 #define SDR0_CP440_ERPN_PCI 0x20000000
2414 #define SDR0_CP440_ERPN_PCI_HI 0x2000
2415 #define SDR0_CP440_ERPN_PCI_LO 0x0000
2416 #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
2417 #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
2418 #define SDR0_CP440_NTO1_MASK 0x00000002
2419 #define SDR0_CP440_NTO1_NTOP 0x00000000
2420 #define SDR0_CP440_NTO1_NTO1 0x00000002
2421 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
2422 #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
2424 #define SDR0_XCR0 0x01C0
2425 #define SDR0_XCR1 0x01C3
2426 #define SDR0_XCR2 0x01C6
2427 #define SDR0_XCRn_PAE_MASK 0x80000000
2428 #define SDR0_XCRn_PAE_DISABLE 0x00000000
2429 #define SDR0_XCRn_PAE_ENABLE 0x80000000
2430 #define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2431 #define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2432 #define SDR0_XCRn_PHCE_MASK 0x40000000
2433 #define SDR0_XCRn_PHCE_DISABLE 0x00000000
2434 #define SDR0_XCRn_PHCE_ENABLE 0x40000000
2435 #define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2436 #define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2437 #define SDR0_XCRn_PISE_MASK 0x20000000
2438 #define SDR0_XCRn_PISE_DISABLE 0x00000000
2439 #define SDR0_XCRn_PISE_ENABLE 0x20000000
2440 #define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2441 #define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2442 #define SDR0_XCRn_PCWE_MASK 0x10000000
2443 #define SDR0_XCRn_PCWE_DISABLE 0x00000000
2444 #define SDR0_XCRn_PCWE_ENABLE 0x10000000
2445 #define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2446 #define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2447 #define SDR0_XCRn_PPIM_MASK 0x0F000000
2448 #define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2449 #define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2450 #define SDR0_XCRn_PR64E_MASK 0x00800000
2451 #define SDR0_XCRn_PR64E_DISABLE 0x00000000
2452 #define SDR0_XCRn_PR64E_ENABLE 0x00800000
2453 #define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2454 #define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2455 #define SDR0_XCRn_PXFS_MASK 0x00600000
2456 #define SDR0_XCRn_PXFS_100_133 0x00000000
2457 #define SDR0_XCRn_PXFS_66_100 0x00200000
2458 #define SDR0_XCRn_PXFS_50_66 0x00400000
2459 #define SDR0_XCRn_PXFS_0_33 0x00600000
2460 #define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2461 #define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2463 #define SDR0_XPLLC0 0x01C1
2464 #define SDR0_XPLLD0 0x01C2
2465 #define SDR0_XPLLC1 0x01C4
2466 #define SDR0_XPLLD1 0x01C5
2467 #define SDR0_XPLLC2 0x01C7
2468 #define SDR0_XPLLD2 0x01C8
2469 #define SDR0_SRST 0x0200
2470 #define SDR0_SLPIPE 0x0220
2472 #define SDR0_AMP0 0x0240
2473 #define SDR0_AMP0_PRIORITY 0xFFFF0000
2474 #define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
2475 #define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
2477 #define SDR0_AMP1 0x0241
2478 #define SDR0_AMP1_PRIORITY 0xFC000000
2479 #define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
2480 #define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
2482 #define SDR0_MIRQ0 0x0260
2483 #define SDR0_MIRQ1 0x0261
2484 #define SDR0_MALTBL 0x0280
2485 #define SDR0_MALRBL 0x02A0
2486 #define SDR0_MALTBS 0x02C0
2487 #define SDR0_MALRBS 0x02E0
2489 /* Reserved for Customer Use */
2490 #define SDR0_CUST0 0x4000
2491 #define SDR0_CUST0_AUTONEG_MASK 0x8000000
2492 #define SDR0_CUST0_NO_AUTONEG 0x0000000
2493 #define SDR0_CUST0_AUTONEG 0x8000000
2494 #define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
2495 #define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
2496 #define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
2497 #define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
2498 #define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
2499 #define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
2500 #define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
2502 #define SDR0_SDSTP4 0x4001
2503 #define SDR0_CUST1 0x4002
2504 #define SDR0_SDSTP5 0x4003
2505 #define SDR0_CUST2 0x4004
2506 #define SDR0_SDSTP6 0x4005
2507 #define SDR0_CUST3 0x4006
2508 #define SDR0_SDSTP7 0x4007
2510 #define SDR0_PFC0 0x4100
2511 #define SDR0_PFC0_GPIO_0 0x80000000
2512 #define SDR0_PFC0_PCIX0REQ2_N 0x00000000
2513 #define SDR0_PFC0_GPIO_1 0x40000000
2514 #define SDR0_PFC0_PCIX0REQ3_N 0x00000000
2515 #define SDR0_PFC0_GPIO_2 0x20000000
2516 #define SDR0_PFC0_PCIX0GNT2_N 0x00000000
2517 #define SDR0_PFC0_GPIO_3 0x10000000
2518 #define SDR0_PFC0_PCIX0GNT3_N 0x00000000
2519 #define SDR0_PFC0_GPIO_4 0x08000000
2520 #define SDR0_PFC0_PCIX1REQ2_N 0x00000000
2521 #define SDR0_PFC0_GPIO_5 0x04000000
2522 #define SDR0_PFC0_PCIX1REQ3_N 0x00000000
2523 #define SDR0_PFC0_GPIO_6 0x02000000
2524 #define SDR0_PFC0_PCIX1GNT2_N 0x00000000
2525 #define SDR0_PFC0_GPIO_7 0x01000000
2526 #define SDR0_PFC0_PCIX1GNT3_N 0x00000000
2527 #define SDR0_PFC0_GPIO_8 0x00800000
2528 #define SDR0_PFC0_PERREADY 0x00000000
2529 #define SDR0_PFC0_GPIO_9 0x00400000
2530 #define SDR0_PFC0_PERCS1_N 0x00000000
2531 #define SDR0_PFC0_GPIO_10 0x00200000
2532 #define SDR0_PFC0_PERCS2_N 0x00000000
2533 #define SDR0_PFC0_GPIO_11 0x00100000
2534 #define SDR0_PFC0_IRQ0 0x00000000
2535 #define SDR0_PFC0_GPIO_12 0x00080000
2536 #define SDR0_PFC0_IRQ1 0x00000000
2537 #define SDR0_PFC0_GPIO_13 0x00040000
2538 #define SDR0_PFC0_IRQ2 0x00000000
2539 #define SDR0_PFC0_GPIO_14 0x00020000
2540 #define SDR0_PFC0_IRQ3 0x00000000
2541 #define SDR0_PFC0_GPIO_15 0x00010000
2542 #define SDR0_PFC0_IRQ4 0x00000000
2543 #define SDR0_PFC0_GPIO_16 0x00008000
2544 #define SDR0_PFC0_IRQ5 0x00000000
2545 #define SDR0_PFC0_GPIO_17 0x00004000
2546 #define SDR0_PFC0_PERBE0_N 0x00000000
2547 #define SDR0_PFC0_GPIO_18 0x00002000
2548 #define SDR0_PFC0_PCI0GNT0_N 0x00000000
2549 #define SDR0_PFC0_GPIO_19 0x00001000
2550 #define SDR0_PFC0_PCI0GNT1_N 0x00000000
2551 #define SDR0_PFC0_GPIO_20 0x00000800
2552 #define SDR0_PFC0_PCI0REQ0_N 0x00000000
2553 #define SDR0_PFC0_GPIO_21 0x00000400
2554 #define SDR0_PFC0_PCI0REQ1_N 0x00000000
2555 #define SDR0_PFC0_GPIO_22 0x00000200
2556 #define SDR0_PFC0_PCI1GNT0_N 0x00000000
2557 #define SDR0_PFC0_GPIO_23 0x00000100
2558 #define SDR0_PFC0_PCI1GNT1_N 0x00000000
2559 #define SDR0_PFC0_GPIO_24 0x00000080
2560 #define SDR0_PFC0_PCI1REQ0_N 0x00000000
2561 #define SDR0_PFC0_GPIO_25 0x00000040
2562 #define SDR0_PFC0_PCI1REQ1_N 0x00000000
2563 #define SDR0_PFC0_GPIO_26 0x00000020
2564 #define SDR0_PFC0_PCI2GNT0_N 0x00000000
2565 #define SDR0_PFC0_GPIO_27 0x00000010
2566 #define SDR0_PFC0_PCI2GNT1_N 0x00000000
2567 #define SDR0_PFC0_GPIO_28 0x00000008
2568 #define SDR0_PFC0_PCI2REQ0_N 0x00000000
2569 #define SDR0_PFC0_GPIO_29 0x00000004
2570 #define SDR0_PFC0_PCI2REQ1_N 0x00000000
2571 #define SDR0_PFC0_GPIO_30 0x00000002
2572 #define SDR0_PFC0_UART1RX 0x00000000
2573 #define SDR0_PFC0_GPIO_31 0x00000001
2574 #define SDR0_PFC0_UART1TX 0x00000000
2576 #define SDR0_PFC1 0x4101
2577 #define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
2578 #define SDR0_PFC1_UART1_DSR_DTR 0x00000000
2579 #define SDR0_PFC1_UART1_CTS_RTS 0x02000000
2580 #define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
2581 #define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
2582 #define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
2583 #define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
2584 #define SDR0_PFC1_ETH_10_100 0x00000000
2585 #define SDR0_PFC1_ETH_GIGA 0x00200000
2586 #define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
2587 #define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
2588 #define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
2589 #define SDR0_PFC1_CPU_NO_TRACE 0x00000000
2590 #define SDR0_PFC1_CPU_TRACE 0x00080000
2591 #define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
2592 #define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
2594 #define SDR0_MFR 0x4300
2595 #endif /* CONFIG_440SPE */
2598 #define SDR0_SDCS_SDD (0x80000000 >> 31)
2600 #if defined(CONFIG_440GP)
2601 #define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
2602 #define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
2603 #endif /* defined(CONFIG_440GP) */
2604 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
2605 #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
2606 #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
2607 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
2608 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
2609 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2610 #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
2611 #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
2612 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
2614 #define SDR0_UARTX_UXICS_MASK 0xF0000000
2615 #define SDR0_UARTX_UXICS_PLB 0x20000000
2616 #define SDR0_UARTX_UXEC_MASK 0x00800000
2617 #define SDR0_UARTX_UXEC_INT 0x00000000
2618 #define SDR0_UARTX_UXEC_EXT 0x00800000
2619 #define SDR0_UARTX_UXDTE_MASK 0x00400000
2620 #define SDR0_UARTX_UXDTE_DISABLE 0x00000000
2621 #define SDR0_UARTX_UXDTE_ENABLE 0x00400000
2622 #define SDR0_UARTX_UXDRE_MASK 0x00200000
2623 #define SDR0_UARTX_UXDRE_DISABLE 0x00000000
2624 #define SDR0_UARTX_UXDRE_ENABLE 0x00200000
2625 #define SDR0_UARTX_UXDC_MASK 0x00100000
2626 #define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000
2627 #define SDR0_UARTX_UXDC_CLEARED 0x00100000
2628 #define SDR0_UARTX_UXDIV_MASK 0x000000FF
2629 #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
2630 #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
2632 #define SDR0_CPU440_EARV_MASK 0x30000000
2633 #define SDR0_CPU440_EARV_EBC 0x10000000
2634 #define SDR0_CPU440_EARV_PCI 0x20000000
2635 #define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
2636 #define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
2637 #define SDR0_CPU440_NTO1_MASK 0x00000002
2638 #define SDR0_CPU440_NTO1_NTOP 0x00000000
2639 #define SDR0_CPU440_NTO1_NTO1 0x00000002
2640 #define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
2641 #define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
2643 #define SDR0_XCR_PAE_MASK 0x80000000
2644 #define SDR0_XCR_PAE_DISABLE 0x00000000
2645 #define SDR0_XCR_PAE_ENABLE 0x80000000
2646 #define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2647 #define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2648 #define SDR0_XCR_PHCE_MASK 0x40000000
2649 #define SDR0_XCR_PHCE_DISABLE 0x00000000
2650 #define SDR0_XCR_PHCE_ENABLE 0x40000000
2651 #define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2652 #define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2653 #define SDR0_XCR_PISE_MASK 0x20000000
2654 #define SDR0_XCR_PISE_DISABLE 0x00000000
2655 #define SDR0_XCR_PISE_ENABLE 0x20000000
2656 #define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2657 #define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2658 #define SDR0_XCR_PCWE_MASK 0x10000000
2659 #define SDR0_XCR_PCWE_DISABLE 0x00000000
2660 #define SDR0_XCR_PCWE_ENABLE 0x10000000
2661 #define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2662 #define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2663 #define SDR0_XCR_PPIM_MASK 0x0F000000
2664 #define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2665 #define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2666 #define SDR0_XCR_PR64E_MASK 0x00800000
2667 #define SDR0_XCR_PR64E_DISABLE 0x00000000
2668 #define SDR0_XCR_PR64E_ENABLE 0x00800000
2669 #define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2670 #define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2671 #define SDR0_XCR_PXFS_MASK 0x00600000
2672 #define SDR0_XCR_PXFS_HIGH 0x00000000
2673 #define SDR0_XCR_PXFS_MED 0x00200000
2674 #define SDR0_XCR_PXFS_LOW 0x00400000
2675 #define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2676 #define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2677 #define SDR0_XCR_PDM_MASK 0x00000040
2678 #define SDR0_XCR_PDM_MULTIPOINT 0x00000000
2679 #define SDR0_XCR_PDM_P2P 0x00000040
2680 #define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19)
2681 #define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01)
2683 #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
2684 #define SDR0_PFC0_GEIE_MASK 0x00003E00
2685 #define SDR0_PFC0_GEIE_TRE 0x00003E00
2686 #define SDR0_PFC0_GEIE_NOTRE 0x00000000
2687 #define SDR0_PFC0_TRE_MASK 0x00000100
2688 #define SDR0_PFC0_TRE_DISABLE 0x00000000
2689 #define SDR0_PFC0_TRE_ENABLE 0x00000100
2690 #define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
2691 #define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
2693 #define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
2694 #define SDR0_PFC1_EPS_MASK 0x01C00000
2695 #define SDR0_PFC1_EPS_GROUP0 0x00000000
2696 #define SDR0_PFC1_EPS_GROUP1 0x00400000
2697 #define SDR0_PFC1_EPS_GROUP2 0x00800000
2698 #define SDR0_PFC1_EPS_GROUP3 0x00C00000
2699 #define SDR0_PFC1_EPS_GROUP4 0x01000000
2700 #define SDR0_PFC1_EPS_GROUP5 0x01400000
2701 #define SDR0_PFC1_EPS_GROUP6 0x01800000
2702 #define SDR0_PFC1_EPS_GROUP7 0x01C00000
2703 #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
2704 #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
2705 #define SDR0_PFC1_RMII_MASK 0x00200000
2706 #define SDR0_PFC1_RMII_100MBIT 0x00000000
2707 #define SDR0_PFC1_RMII_10MBIT 0x00200000
2708 #define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21)
2709 #define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
2710 #define SDR0_PFC1_CTEMS_MASK 0x00100000
2711 #define SDR0_PFC1_CTEMS_EMS 0x00000000
2712 #define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000
2714 #define SDR0_MFR_TAH0_MASK 0x80000000
2715 #define SDR0_MFR_TAH0_ENABLE 0x00000000
2716 #define SDR0_MFR_TAH0_DISABLE 0x80000000
2717 #define SDR0_MFR_TAH1_MASK 0x40000000
2718 #define SDR0_MFR_TAH1_ENABLE 0x00000000
2719 #define SDR0_MFR_TAH1_DISABLE 0x40000000
2720 #define SDR0_MFR_PCM_MASK 0x20000000
2721 #define SDR0_MFR_PCM_PPC440GX 0x00000000
2722 #define SDR0_MFR_PCM_PPC440GP 0x20000000
2723 #define SDR0_MFR_ECS_MASK 0x10000000
2724 #define SDR0_MFR_ECS_INTERNAL 0x10000000
2726 #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
2727 #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
2728 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
2729 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
2730 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
2731 #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
2732 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
2733 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
2734 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
2735 #define SDR0_MFR_ERRATA3_EN0 0x00800000
2736 #define SDR0_MFR_ERRATA3_EN1 0x00400000
2737 #if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
2738 #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
2739 #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
2740 #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
2741 #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
2742 #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
2745 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2746 #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
2747 #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
2748 #define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29)
2749 #define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07)
2752 #define SDR0_MFR_ECS_MASK 0x10000000
2753 #define SDR0_MFR_ECS_INTERNAL 0x10000000
2755 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2756 #define SDR0_SRST0 0x200
2757 #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
2758 #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
2759 #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
2760 #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
2761 #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
2762 #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
2763 #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
2764 #define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
2765 #define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
2766 #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
2767 #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
2768 #define SDR0_SRST0_PCI 0x00100000 /* PCI */
2769 #define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
2770 #define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
2771 #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
2772 #define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
2773 #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
2774 #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
2775 #define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
2776 #define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
2777 #define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
2778 #define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
2779 #define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
2780 #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
2781 #define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
2782 #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
2783 #define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
2784 #define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
2785 #define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
2786 #define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
2787 #define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
2789 #define SDR0_SRST1 0x201
2790 #define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
2791 #define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
2792 #define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
2793 #define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
2794 #define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
2795 #define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
2796 #define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
2797 #define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
2798 #define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
2799 #define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
2800 #define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
2801 #define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
2802 #define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
2803 #define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
2804 #define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
2805 #define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
2806 #define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
2807 #define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
2808 #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
2809 #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
2813 #define SDR0_SRST_BGO 0x80000000
2814 #define SDR0_SRST_PLB 0x40000000
2815 #define SDR0_SRST_EBC 0x20000000
2816 #define SDR0_SRST_OPB 0x10000000
2817 #define SDR0_SRST_UART0 0x08000000
2818 #define SDR0_SRST_UART1 0x04000000
2819 #define SDR0_SRST_IIC0 0x02000000
2820 #define SDR0_SRST_IIC1 0x01000000
2821 #define SDR0_SRST_GPIO 0x00800000
2822 #define SDR0_SRST_GPT 0x00400000
2823 #define SDR0_SRST_DMC 0x00200000
2824 #define SDR0_SRST_PCI 0x00100000
2825 #define SDR0_SRST_EMAC0 0x00080000
2826 #define SDR0_SRST_EMAC1 0x00040000
2827 #define SDR0_SRST_CPM 0x00020000
2828 #define SDR0_SRST_IMU 0x00010000
2829 #define SDR0_SRST_UIC01 0x00008000
2830 #define SDR0_SRST_UICB2 0x00004000
2831 #define SDR0_SRST_SRAM 0x00002000
2832 #define SDR0_SRST_EBM 0x00001000
2833 #define SDR0_SRST_BGI 0x00000800
2834 #define SDR0_SRST_DMA 0x00000400
2835 #define SDR0_SRST_DMAC 0x00000200
2836 #define SDR0_SRST_MAL 0x00000100
2837 #define SDR0_SRST_ZMII 0x00000080
2838 #define SDR0_SRST_GPTR 0x00000040
2839 #define SDR0_SRST_PPM 0x00000020
2840 #define SDR0_SRST_EMAC2 0x00000010
2841 #define SDR0_SRST_EMAC3 0x00000008
2842 #define SDR0_SRST_RGMII 0x00000001
2846 /*-----------------------------------------------------------------------------+
2848 +-----------------------------------------------------------------------------*/
2849 #if !defined (CONFIG_440GX) && \
2850 !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
2851 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
2852 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
2853 #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
2854 #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
2855 #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
2856 #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
2857 #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
2858 #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
2859 #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
2860 #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
2861 #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
2862 #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
2863 #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
2864 #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
2866 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
2867 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
2868 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
2869 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
2870 #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
2871 #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
2872 #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
2873 #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
2874 #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
2875 #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
2876 #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
2877 #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
2878 #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
2879 #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
2881 #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
2882 #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
2883 #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
2884 #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
2885 #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
2886 #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
2888 #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
2889 #define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
2890 #define PRADV_MASK 0x07000000 /* Primary Divisor A */
2891 #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
2892 #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
2894 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
2895 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
2896 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
2897 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
2899 /* Strap 1 Register */
2900 #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
2901 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
2902 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
2903 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
2904 #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
2905 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
2906 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
2907 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
2908 #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
2909 #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
2910 #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
2911 #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
2912 #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
2913 #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
2914 #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
2915 #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
2916 #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
2917 #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
2918 #endif /* CONFIG_440GX */
2920 #if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
2921 /*--------------------------------------*/
2922 #define CPR0_PLLC 0x40
2923 #define CPR0_PLLC_RST_MASK 0x80000000
2924 #define CPR0_PLLC_RST_PLLLOCKED 0x00000000
2925 #define CPR0_PLLC_RST_PLLRESET 0x80000000
2926 #define CPR0_PLLC_ENG_MASK 0x40000000
2927 #define CPR0_PLLC_ENG_DISABLE 0x00000000
2928 #define CPR0_PLLC_ENG_ENABLE 0x40000000
2929 #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2930 #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2931 #define CPR0_PLLC_SRC_MASK 0x20000000
2932 #define CPR0_PLLC_SRC_PLLOUTA 0x00000000
2933 #define CPR0_PLLC_SRC_PLLOUTB 0x20000000
2934 #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2935 #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2936 #define CPR0_PLLC_SEL_MASK 0x07000000
2937 #define CPR0_PLLC_SEL_PLL 0x00000000
2938 #define CPR0_PLLC_SEL_CPU 0x01000000
2939 #define CPR0_PLLC_SEL_PER 0x05000000
2940 #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2941 #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
2942 #define CPR0_PLLC_TUNE_MASK 0x000003FF
2943 #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
2944 #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
2945 /*--------------------------------------*/
2946 #define CPR0_PLLD 0x60
2947 #define CPR0_PLLD_FBDV_MASK 0x1F000000
2948 #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
2949 #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
2950 #define CPR0_PLLD_FWDVA_MASK 0x000F0000
2951 #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
2952 #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
2953 #define CPR0_PLLD_FWDVB_MASK 0x00000700
2954 #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
2955 #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
2956 #define CPR0_PLLD_LFBDV_MASK 0x0000003F
2957 #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
2958 #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
2959 /*--------------------------------------*/
2960 #define CPR0_PRIMAD 0x80
2961 #define CPR0_PRIMAD_PRADV0_MASK 0x07000000
2962 #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2963 #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
2964 /*--------------------------------------*/
2965 #define CPR0_PRIMBD 0xA0
2966 #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
2967 #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2968 #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
2969 /*--------------------------------------*/
2971 #define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */
2972 #define CPR0_CPM0_FR 0xB1 /* CPM Force Register */
2973 #define CPR0_CPM0_SR 0xB2 /* CPM Status Register */
2974 #define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */
2975 #define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */
2976 #define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */
2977 #define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */
2978 #define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */
2979 #define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */
2980 #define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */
2981 #define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */
2982 #define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */
2983 #define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */
2984 #define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */
2985 #define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
2986 #define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
2987 #define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */
2988 #define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */
2989 #define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */
2990 #define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */
2991 #define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */
2992 #define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */
2993 #define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */
2994 #define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */
2995 #define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */
2996 #define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */
2997 #define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */
2998 #define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */
2999 #define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */
3000 #define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */
3001 #define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */
3002 #define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */
3003 #define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */
3004 #define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */
3006 /*--------------------------------------*/
3007 #define CPR0_OPBD 0xC0
3008 #define CPR0_OPBD_OPBDV0_MASK 0x03000000
3009 #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
3010 #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
3011 /*--------------------------------------*/
3012 #define CPR0_PERD 0xE0
3013 #define CPR0_PERD_PERDV0_MASK 0x07000000
3014 #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
3015 #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
3016 /*--------------------------------------*/
3017 #define CPR0_MALD 0x100
3018 #define CPR0_MALD_MALDV0_MASK 0x03000000
3019 #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
3020 #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
3021 /*--------------------------------------*/
3022 #define CPR0_SPCID 0x120
3023 #define CPR0_SPCID_SPCIDV0_MASK 0x03000000
3024 #define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
3025 #define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
3026 /*--------------------------------------*/
3027 #define CPR0_ICFG 0x140
3028 #define CPR0_ICFG_RLI_MASK 0x80000000
3029 #define CPR0_ICFG_RLI_RESETCPR 0x00000000
3030 #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
3031 #define CPR0_ICFG_ICS_MASK 0x00000007
3032 #endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
3034 /*-----------------------------------------------------------------------------
3035 | IIC Register Offsets
3036 '----------------------------------------------------------------------------*/
3037 #define IICMDBUF 0x00
3038 #define IICSDBUF 0x02
3039 #define IICLMADR 0x04
3040 #define IICHMADR 0x05
3041 #define IICCNTL 0x06
3042 #define IICMDCNTL 0x07
3044 #define IICEXTSTS 0x09
3045 #define IICLSADR 0x0A
3046 #define IICHSADR 0x0B
3047 #define IICCLKDIV 0x0C
3048 #define IICINTRMSK 0x0D
3049 #define IICXFRCNT 0x0E
3050 #define IICXTCNTLSS 0x0F
3051 #define IICDIRECTCNTL 0x10
3053 /*-----------------------------------------------------------------------------
3054 | UART Register Offsets
3055 '----------------------------------------------------------------------------*/
3056 #define DATA_REG 0x00
3059 #define INT_ENABLE 0x01
3060 #define FIFO_CONTROL 0x02
3061 #define LINE_CONTROL 0x03
3062 #define MODEM_CONTROL 0x04
3063 #define LINE_STATUS 0x05
3064 #define MODEM_STATUS 0x06
3065 #define SCRATCH 0x07
3067 /*-----------------------------------------------------------------------------
3068 | PCI Internal Registers et. al. (accessed via plb)
3069 +----------------------------------------------------------------------------*/
3070 #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000)
3071 #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004)
3072 #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
3073 #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
3075 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
3076 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3078 /* PCI Local Configuration Registers
3079 --------------------------------- */
3080 #define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
3082 /* PCI Master Local Configuration Registers */
3083 #define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
3084 #define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
3085 #define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
3086 #define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
3087 #define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
3088 #define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
3089 #define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
3090 #define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
3091 #define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
3092 #define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
3093 #define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
3094 #define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
3096 /* PCI Target Local Configuration Registers */
3097 #define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
3098 #define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
3099 #define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
3100 #define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
3104 #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
3105 #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
3106 #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
3107 #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
3108 #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
3109 #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
3110 #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
3111 #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
3112 #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
3113 #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
3114 #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
3115 #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
3116 #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
3117 #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
3118 #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
3119 #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
3120 #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
3121 #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
3122 #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
3123 #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
3124 #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
3125 #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
3126 #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
3127 #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
3128 #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
3129 #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
3130 #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
3131 #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
3133 #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
3134 #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
3136 #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
3137 #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
3138 #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
3139 #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
3140 #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
3141 #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
3142 #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
3143 #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
3144 #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
3145 #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
3146 #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
3148 #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
3149 #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
3150 #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
3151 #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
3152 #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
3153 #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
3154 #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
3155 #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
3156 #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
3158 #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
3160 #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
3162 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3165 #define USB2D0_BASE CFG_USB2D0_BASE
3167 #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
3169 #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
3170 #define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
3171 #define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
3172 #define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
3173 #define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
3174 #define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
3175 #define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
3176 #define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
3177 #define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
3178 #define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
3179 #define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
3180 #define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
3181 #define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
3182 #define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
3183 #define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
3184 #define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
3185 #define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
3186 #define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
3189 /******************************************************************************
3190 * GPIO macro register defines
3191 ******************************************************************************/
3192 #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
3193 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
3194 #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
3196 #define GPIO0_OR (GPIO0_BASE+0x0)
3197 #define GPIO0_TCR (GPIO0_BASE+0x4)
3198 #define GPIO0_ODR (GPIO0_BASE+0x18)
3199 #define GPIO0_IR (GPIO0_BASE+0x1C)
3200 #endif /* CONFIG_440GP */
3202 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
3203 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3204 #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
3205 #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
3207 #define GPIO0_OR (GPIO0_BASE+0x0)
3208 #define GPIO0_TCR (GPIO0_BASE+0x4)
3209 #define GPIO0_OSRL (GPIO0_BASE+0x8)
3210 #define GPIO0_OSRH (GPIO0_BASE+0xC)
3211 #define GPIO0_TSRL (GPIO0_BASE+0x10)
3212 #define GPIO0_TSRH (GPIO0_BASE+0x14)
3213 #define GPIO0_ODR (GPIO0_BASE+0x18)
3214 #define GPIO0_IR (GPIO0_BASE+0x1C)
3215 #define GPIO0_RR1 (GPIO0_BASE+0x20)
3216 #define GPIO0_RR2 (GPIO0_BASE+0x24)
3217 #define GPIO0_RR3 (GPIO0_BASE+0x28)
3218 #define GPIO0_ISR1L (GPIO0_BASE+0x30)
3219 #define GPIO0_ISR1H (GPIO0_BASE+0x34)
3220 #define GPIO0_ISR2L (GPIO0_BASE+0x38)
3221 #define GPIO0_ISR2H (GPIO0_BASE+0x3C)
3222 #define GPIO0_ISR3L (GPIO0_BASE+0x40)
3223 #define GPIO0_ISR3H (GPIO0_BASE+0x44)
3225 #define GPIO1_OR (GPIO1_BASE+0x0)
3226 #define GPIO1_TCR (GPIO1_BASE+0x4)
3227 #define GPIO1_OSRL (GPIO1_BASE+0x8)
3228 #define GPIO1_OSRH (GPIO1_BASE+0xC)
3229 #define GPIO1_TSRL (GPIO1_BASE+0x10)
3230 #define GPIO1_TSRH (GPIO1_BASE+0x14)
3231 #define GPIO1_ODR (GPIO1_BASE+0x18)
3232 #define GPIO1_IR (GPIO1_BASE+0x1C)
3233 #define GPIO1_RR1 (GPIO1_BASE+0x20)
3234 #define GPIO1_RR2 (GPIO1_BASE+0x24)
3235 #define GPIO1_RR3 (GPIO1_BASE+0x28)
3236 #define GPIO1_ISR1L (GPIO1_BASE+0x30)
3237 #define GPIO1_ISR1H (GPIO1_BASE+0x34)
3238 #define GPIO1_ISR2L (GPIO1_BASE+0x38)
3239 #define GPIO1_ISR2H (GPIO1_BASE+0x3C)
3240 #define GPIO1_ISR3L (GPIO1_BASE+0x40)
3241 #define GPIO1_ISR3H (GPIO1_BASE+0x44)
3244 #ifndef __ASSEMBLY__
3246 static inline u32 get_mcsr(void)
3250 asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
3254 static inline void set_mcsr(u32 val)
3256 asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
3259 #endif /* _ASMLANGUAGE */
3261 #endif /* __PPC440_H__ */
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