1 /*----------------------------------------------------------------------------+
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
5 | copyrights to use it in any way he or she deems fit, including
6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
18 | COPYRIGHT I B M CORPORATION 1999
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +----------------------------------------------------------------------------*/
24 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
25 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
26 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
27 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
28 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License as
32 * published by the Free Software Foundation; either version 2 of
33 * the License, or (at your option) any later version.
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
49 #define CFG_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
51 /*--------------------------------------------------------------------- */
52 /* Special Purpose Registers */
53 /*--------------------------------------------------------------------- */
56 #define dec 0x016 /* decrementer */
57 #define srr0 0x01a /* save/restore register 0 */
58 #define srr1 0x01b /* save/restore register 1 */
59 #define pid 0x030 /* process id */
60 #define decar 0x036 /* decrementer auto-reload */
61 #define csrr0 0x03a /* critical save/restore register 0 */
62 #define csrr1 0x03b /* critical save/restore register 1 */
63 #define dear 0x03d /* data exception address register */
64 #define esr 0x03e /* exception syndrome register */
65 #define ivpr 0x03f /* interrupt prefix register */
66 #define usprg0 0x100 /* user special purpose register general 0 */
67 #define usprg1 0x110 /* user special purpose register general 1 */
68 #define tblr 0x10c /* time base lower, read only */
69 #define tbur 0x10d /* time base upper, read only */
70 #define sprg1 0x111 /* special purpose register general 1 */
71 #define sprg2 0x112 /* special purpose register general 2 */
72 #define sprg3 0x113 /* special purpose register general 3 */
73 #define sprg4 0x114 /* special purpose register general 4 */
74 #define sprg5 0x115 /* special purpose register general 5 */
75 #define sprg6 0x116 /* special purpose register general 6 */
76 #define sprg7 0x117 /* special purpose register general 7 */
77 #define tbl 0x11c /* time base lower (supervisor)*/
78 #define tbu 0x11d /* time base upper (supervisor)*/
79 #define pir 0x11e /* processor id register */
80 /*#define pvr 0x11f processor version register */
81 #define dbsr 0x130 /* debug status register */
82 #define dbcr0 0x134 /* debug control register 0 */
83 #define dbcr1 0x135 /* debug control register 1 */
84 #define dbcr2 0x136 /* debug control register 2 */
85 #define iac1 0x138 /* instruction address compare 1 */
86 #define iac2 0x139 /* instruction address compare 2 */
87 #define iac3 0x13a /* instruction address compare 3 */
88 #define iac4 0x13b /* instruction address compare 4 */
89 #define dac1 0x13c /* data address compare 1 */
90 #define dac2 0x13d /* data address compare 2 */
91 #define dvc1 0x13e /* data value compare 1 */
92 #define dvc2 0x13f /* data value compare 2 */
93 #define tsr 0x150 /* timer status register */
94 #define tcr 0x154 /* timer control register */
95 #define ivor0 0x190 /* interrupt vector offset register 0 */
96 #define ivor1 0x191 /* interrupt vector offset register 1 */
97 #define ivor2 0x192 /* interrupt vector offset register 2 */
98 #define ivor3 0x193 /* interrupt vector offset register 3 */
99 #define ivor4 0x194 /* interrupt vector offset register 4 */
100 #define ivor5 0x195 /* interrupt vector offset register 5 */
101 #define ivor6 0x196 /* interrupt vector offset register 6 */
102 #define ivor7 0x197 /* interrupt vector offset register 7 */
103 #define ivor8 0x198 /* interrupt vector offset register 8 */
104 #define ivor9 0x199 /* interrupt vector offset register 9 */
105 #define ivor10 0x19a /* interrupt vector offset register 10 */
106 #define ivor11 0x19b /* interrupt vector offset register 11 */
107 #define ivor12 0x19c /* interrupt vector offset register 12 */
108 #define ivor13 0x19d /* interrupt vector offset register 13 */
109 #define ivor14 0x19e /* interrupt vector offset register 14 */
110 #define ivor15 0x19f /* interrupt vector offset register 15 */
111 #if defined(CONFIG_440)
112 #define mcsrr0 0x23a /* machine check save/restore register 0 */
113 #define mcsrr1 0x23b /* mahcine check save/restore register 1 */
114 #define mcsr 0x23c /* machine check status register */
116 #define inv0 0x370 /* instruction cache normal victim 0 */
117 #define inv1 0x371 /* instruction cache normal victim 1 */
118 #define inv2 0x372 /* instruction cache normal victim 2 */
119 #define inv3 0x373 /* instruction cache normal victim 3 */
120 #define itv0 0x374 /* instruction cache transient victim 0 */
121 #define itv1 0x375 /* instruction cache transient victim 1 */
122 #define itv2 0x376 /* instruction cache transient victim 2 */
123 #define itv3 0x377 /* instruction cache transient victim 3 */
124 #define dnv0 0x390 /* data cache normal victim 0 */
125 #define dnv1 0x391 /* data cache normal victim 1 */
126 #define dnv2 0x392 /* data cache normal victim 2 */
127 #define dnv3 0x393 /* data cache normal victim 3 */
128 #define dtv0 0x394 /* data cache transient victim 0 */
129 #define dtv1 0x395 /* data cache transient victim 1 */
130 #define dtv2 0x396 /* data cache transient victim 2 */
131 #define dtv3 0x397 /* data cache transient victim 3 */
132 #define dvlim 0x398 /* data cache victim limit */
133 #define ivlim 0x399 /* instruction cache victim limit */
134 #define rstcfg 0x39b /* reset configuration */
135 #define dcdbtrl 0x39c /* data cache debug tag register low */
136 #define dcdbtrh 0x39d /* data cache debug tag register high */
137 #define icdbtrl 0x39e /* instruction cache debug tag register low */
138 #define icdbtrh 0x39f /* instruction cache debug tag register high */
139 #define mmucr 0x3b2 /* mmu control register */
140 #define ccr0 0x3b3 /* core configuration register 0 */
141 #define ccr1 0x378 /* core configuration for 440x5 only */
142 #define icdbdr 0x3d3 /* instruction cache debug data register */
143 #define dbdr 0x3f3 /* debug data register */
145 /******************************************************************************
147 ******************************************************************************/
149 /*-----------------------------------------------------------------------------
150 | Clocking Controller
151 +----------------------------------------------------------------------------*/
152 /* values for clkcfga register - indirect addressing of these regs */
153 #define clk_clkukpd 0x0020
154 #define clk_pllc 0x0040
155 #define clk_plld 0x0060
156 #define clk_primad 0x0080
157 #define clk_primbd 0x00a0
158 #define clk_opbd 0x00c0
159 #define clk_perd 0x00e0
160 #define clk_mald 0x0100
161 #define clk_spcid 0x0120
162 #define clk_icfg 0x0140
164 /* 440gx sdr register definations */
165 #define sdr_sdstp0 0x0020 /* */
166 #define sdr_sdstp1 0x0021 /* */
167 #define SDR_PINSTP 0x0040
168 #define sdr_sdcs 0x0060
169 #define sdr_ecid0 0x0080
170 #define sdr_ecid1 0x0081
171 #define sdr_ecid2 0x0082
172 #define sdr_jtag 0x00c0
173 #if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
174 #define sdr_ddrdl 0x00e0
176 #define sdr_cfg 0x00e0
177 #define SDR_CFG_LT2_MASK 0x01000000 /* Leakage test 2*/
178 #define SDR_CFG_64_32BITS_MASK 0x01000000 /* Switch DDR 64 bits or 32 bits */
179 #define SDR_CFG_32BITS 0x00000000 /* 32 bits */
180 #define SDR_CFG_64BITS 0x01000000 /* 64 bits */
181 #define SDR_CFG_MC_V2518_MASK 0x02000000 /* Low VDD2518 (2.5 or 1.8V) */
182 #define SDR_CFG_MC_V25 0x00000000 /* 2.5 V */
183 #define SDR_CFG_MC_V18 0x02000000 /* 1.8 V */
184 #endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */
185 #define sdr_ebc 0x0100
186 #define sdr_uart0 0x0120 /* UART0 Config */
187 #define sdr_uart1 0x0121 /* UART1 Config */
188 #define sdr_uart2 0x0122 /* UART2 Config */
189 #define sdr_uart3 0x0123 /* UART3 Config */
190 #define sdr_cp440 0x0180
191 #define sdr_xcr 0x01c0
192 #define sdr_xpllc 0x01c1
193 #define sdr_xplld 0x01c2
194 #define sdr_srst 0x0200
195 #define sdr_slpipe 0x0220
196 #define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */
197 #define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */
198 #define sdr_mirq0 0x0260
199 #define sdr_mirq1 0x0261
200 #define sdr_maltbl 0x0280
201 #define sdr_malrbl 0x02a0
202 #define sdr_maltbs 0x02c0
203 #define sdr_malrbs 0x02e0
204 #define sdr_pci0 0x0300
205 #define sdr_usb0 0x0320
206 #define sdr_cust0 0x4000
207 #define sdr_cust1 0x4002
208 #define sdr_pfc0 0x4100 /* Pin Function 0 */
209 #define sdr_pfc1 0x4101 /* Pin Function 1 */
210 #define sdr_plbtr 0x4200
211 #define sdr_mfr 0x4300 /* SDR0_MFR reg */
214 #define sdr_amp 0x0240
215 #define sdr_xpllc 0x01c1
216 #define sdr_xplld 0x01c2
217 #define sdr_xcr 0x01c0
218 #define sdr_sdstp2 0x4001
219 #define sdr_sdstp3 0x4003
220 #endif /* CONFIG_440GX */
222 /*----------------------------------------------------------------------------+
223 | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only).
224 +----------------------------------------------------------------------------*/
225 #define CCR0_PRE 0x40000000
226 #define CCR0_CRPE 0x08000000
227 #define CCR0_DSTG 0x00200000
228 #define CCR0_DAPUIB 0x00100000
229 #define CCR0_DTB 0x00008000
230 #define CCR0_GICBT 0x00004000
231 #define CCR0_GDCBT 0x00002000
232 #define CCR0_FLSTA 0x00000100
233 #define CCR0_ICSLC_MASK 0x0000000C
234 #define CCR0_ICSLT_MASK 0x00000003
235 #define CCR1_TCS_MASK 0x00000080
236 #define CCR1_TCS_INTCLK 0x00000000
237 #define CCR1_TCS_EXTCLK 0x00000080
238 #define MMUCR_SWOA 0x01000000
239 #define MMUCR_U1TE 0x00400000
240 #define MMUCR_U2SWOAE 0x00200000
241 #define MMUCR_DULXE 0x00800000
242 #define MMUCR_IULXE 0x00400000
243 #define MMUCR_STS 0x00100000
244 #define MMUCR_STID_MASK 0x000000FF
248 #define sdr_sdstp2 0x0022
250 #define sdr_sdstp3 0x0023
251 #define sdr_ddr0 0x00E1
252 #define sdr_uart2 0x0122
253 #define sdr_xcr0 0x01c0
254 /* #define sdr_xcr1 0x01c3 only one PCIX - SG */
255 /* #define sdr_xcr2 0x01c6 only one PCIX - SG */
256 #define sdr_xpllc0 0x01c1
257 #define sdr_xplld0 0x01c2
258 #define sdr_xpllc1 0x01c4 /*notRCW - SG */
259 #define sdr_xplld1 0x01c5 /*notRCW - SG */
260 #define sdr_xpllc2 0x01c7 /*notRCW - SG */
261 #define sdr_xplld2 0x01c8 /*notRCW - SG */
262 #define sdr_amp0 0x0240
263 #define sdr_amp1 0x0241
264 #define sdr_cust2 0x4004
265 #define sdr_cust3 0x4006
266 #define sdr_sdstp4 0x4001
267 #define sdr_sdstp5 0x4003
268 #define sdr_sdstp6 0x4005
269 #define sdr_sdstp7 0x4007
271 /******************************************************************************
272 * PCI express defines
273 ******************************************************************************/
274 #define SDR0_PE0UTLSET1 0x00000300 /* PE0 Upper transaction layer conf setting */
275 #define SDR0_PE0UTLSET2 0x00000301 /* PE0 Upper transaction layer conf setting 2 */
276 #define SDR0_PE0DLPSET 0x00000302 /* PE0 Data link & logical physical configuration */
277 #define SDR0_PE0LOOP 0x00000303 /* PE0 Loopback interface status */
278 #define SDR0_PE0RCSSET 0x00000304 /* PE0 Reset, clock & shutdown setting */
279 #define SDR0_PE0RCSSTS 0x00000305 /* PE0 Reset, clock & shutdown status */
280 #define SDR0_PE0HSSSET1L0 0x00000306 /* PE0 HSS Control Setting 1: Lane 0 */
281 #define SDR0_PE0HSSSET2L0 0x00000307 /* PE0 HSS Control Setting 2: Lane 0 */
282 #define SDR0_PE0HSSSTSL0 0x00000308 /* PE0 HSS Control Status : Lane 0 */
283 #define SDR0_PE0HSSSET1L1 0x00000309 /* PE0 HSS Control Setting 1: Lane 1 */
284 #define SDR0_PE0HSSSET2L1 0x0000030A /* PE0 HSS Control Setting 2: Lane 1 */
285 #define SDR0_PE0HSSSTSL1 0x0000030B /* PE0 HSS Control Status : Lane 1 */
286 #define SDR0_PE0HSSSET1L2 0x0000030C /* PE0 HSS Control Setting 1: Lane 2 */
287 #define SDR0_PE0HSSSET2L2 0x0000030D /* PE0 HSS Control Setting 2: Lane 2 */
288 #define SDR0_PE0HSSSTSL2 0x0000030E /* PE0 HSS Control Status : Lane 2 */
289 #define SDR0_PE0HSSSET1L3 0x0000030F /* PE0 HSS Control Setting 1: Lane 3 */
290 #define SDR0_PE0HSSSET2L3 0x00000310 /* PE0 HSS Control Setting 2: Lane 3 */
291 #define SDR0_PE0HSSSTSL3 0x00000311 /* PE0 HSS Control Status : Lane 3 */
292 #define SDR0_PE0HSSSET1L4 0x00000312 /* PE0 HSS Control Setting 1: Lane 4 */
293 #define SDR0_PE0HSSSET2L4 0x00000313 /* PE0 HSS Control Setting 2: Lane 4 */
294 #define SDR0_PE0HSSSTSL4 0x00000314 /* PE0 HSS Control Status : Lane 4 */
295 #define SDR0_PE0HSSSET1L5 0x00000315 /* PE0 HSS Control Setting 1: Lane 5 */
296 #define SDR0_PE0HSSSET2L5 0x00000316 /* PE0 HSS Control Setting 2: Lane 5 */
297 #define SDR0_PE0HSSSTSL5 0x00000317 /* PE0 HSS Control Status : Lane 5 */
298 #define SDR0_PE0HSSSET1L6 0x00000318 /* PE0 HSS Control Setting 1: Lane 6 */
299 #define SDR0_PE0HSSSET2L6 0x00000319 /* PE0 HSS Control Setting 2: Lane 6 */
300 #define SDR0_PE0HSSSTSL6 0x0000031A /* PE0 HSS Control Status : Lane 6 */
301 #define SDR0_PE0HSSSET1L7 0x0000031B /* PE0 HSS Control Setting 1: Lane 7 */
302 #define SDR0_PE0HSSSET2L7 0x0000031C /* PE0 HSS Control Setting 2: Lane 7 */
303 #define SDR0_PE0HSSSTSL7 0x0000031D /* PE0 HSS Control Status : Lane 7 */
304 #define SDR0_PE0HSSSEREN 0x0000031E /* PE0 Serdes Transmitter Enable */
305 #define SDR0_PE0LANEABCD 0x0000031F /* PE0 Lanes ABCD affectation */
306 #define SDR0_PE0LANEEFGH 0x00000320 /* PE0 Lanes EFGH affectation */
308 #define SDR0_PE1UTLSET1 0x00000340 /* PE1 Upper transaction layer conf setting */
309 #define SDR0_PE1UTLSET2 0x00000341 /* PE1 Upper transaction layer conf setting 2 */
310 #define SDR0_PE1DLPSET 0x00000342 /* PE1 Data link & logical physical configuration */
311 #define SDR0_PE1LOOP 0x00000343 /* PE1 Loopback interface status */
312 #define SDR0_PE1RCSSET 0x00000344 /* PE1 Reset, clock & shutdown setting */
313 #define SDR0_PE1RCSSTS 0x00000345 /* PE1 Reset, clock & shutdown status */
314 #define SDR0_PE1HSSSET1L0 0x00000346 /* PE1 HSS Control Setting 1: Lane 0 */
315 #define SDR0_PE1HSSSET2L0 0x00000347 /* PE1 HSS Control Setting 2: Lane 0 */
316 #define SDR0_PE1HSSSTSL0 0x00000348 /* PE1 HSS Control Status : Lane 0 */
317 #define SDR0_PE1HSSSET1L1 0x00000349 /* PE1 HSS Control Setting 1: Lane 1 */
318 #define SDR0_PE1HSSSET2L1 0x0000034A /* PE1 HSS Control Setting 2: Lane 1 */
319 #define SDR0_PE1HSSSTSL1 0x0000034B /* PE1 HSS Control Status : Lane 1 */
320 #define SDR0_PE1HSSSET1L2 0x0000034C /* PE1 HSS Control Setting 1: Lane 2 */
321 #define SDR0_PE1HSSSET2L2 0x0000034D /* PE1 HSS Control Setting 2: Lane 2 */
322 #define SDR0_PE1HSSSTSL2 0x0000034E /* PE1 HSS Control Status : Lane 2 */
323 #define SDR0_PE1HSSSET1L3 0x0000034F /* PE1 HSS Control Setting 1: Lane 3 */
324 #define SDR0_PE1HSSSET2L3 0x00000350 /* PE1 HSS Control Setting 2: Lane 3 */
325 #define SDR0_PE1HSSSTSL3 0x00000351 /* PE1 HSS Control Status : Lane 3 */
326 #define SDR0_PE1HSSSEREN 0x00000352 /* PE1 Serdes Transmitter Enable */
327 #define SDR0_PE1LANEABCD 0x00000353 /* PE1 Lanes ABCD affectation */
328 #define SDR0_PE2UTLSET1 0x00000370 /* PE2 Upper transaction layer conf setting */
329 #define SDR0_PE2UTLSET2 0x00000371 /* PE2 Upper transaction layer conf setting 2 */
330 #define SDR0_PE2DLPSET 0x00000372 /* PE2 Data link & logical physical configuration */
331 #define SDR0_PE2LOOP 0x00000373 /* PE2 Loopback interface status */
332 #define SDR0_PE2RCSSET 0x00000374 /* PE2 Reset, clock & shutdown setting */
333 #define SDR0_PE2RCSSTS 0x00000375 /* PE2 Reset, clock & shutdown status */
334 #define SDR0_PE2HSSSET1L0 0x00000376 /* PE2 HSS Control Setting 1: Lane 0 */
335 #define SDR0_PE2HSSSET2L0 0x00000377 /* PE2 HSS Control Setting 2: Lane 0 */
336 #define SDR0_PE2HSSSTSL0 0x00000378 /* PE2 HSS Control Status : Lane 0 */
337 #define SDR0_PE2HSSSET1L1 0x00000379 /* PE2 HSS Control Setting 1: Lane 1 */
338 #define SDR0_PE2HSSSET2L1 0x0000037A /* PE2 HSS Control Setting 2: Lane 1 */
339 #define SDR0_PE2HSSSTSL1 0x0000037B /* PE2 HSS Control Status : Lane 1 */
340 #define SDR0_PE2HSSSET1L2 0x0000037C /* PE2 HSS Control Setting 1: Lane 2 */
341 #define SDR0_PE2HSSSET2L2 0x0000037D /* PE2 HSS Control Setting 2: Lane 2 */
342 #define SDR0_PE2HSSSTSL2 0x0000037E /* PE2 HSS Control Status : Lane 2 */
343 #define SDR0_PE2HSSSET1L3 0x0000037F /* PE2 HSS Control Setting 1: Lane 3 */
344 #define SDR0_PE2HSSSET2L3 0x00000380 /* PE2 HSS Control Setting 2: Lane 3 */
345 #define SDR0_PE2HSSSTSL3 0x00000381 /* PE2 HSS Control Status : Lane 3 */
346 #define SDR0_PE2HSSSEREN 0x00000382 /* PE2 Serdes Transmitter Enable */
347 #define SDR0_PE2LANEABCD 0x00000383 /* PE2 Lanes ABCD affectation */
348 #define SDR0_PEGPLLSET1 0x000003A0 /* PE Pll LC Tank Setting1 */
349 #define SDR0_PEGPLLSET2 0x000003A1 /* PE Pll LC Tank Setting2 */
350 #define SDR0_PEGPLLSTS 0x000003A2 /* PE Pll LC Tank Status */
351 #endif /* CONFIG_440SPE */
353 /*-----------------------------------------------------------------------------
354 | External Bus Controller
355 +----------------------------------------------------------------------------*/
356 /* values for ebccfga register - indirect addressing of these regs */
357 #define pb0cr 0x00 /* periph bank 0 config reg */
358 #define pb1cr 0x01 /* periph bank 1 config reg */
359 #define pb2cr 0x02 /* periph bank 2 config reg */
360 #define pb3cr 0x03 /* periph bank 3 config reg */
361 #define pb4cr 0x04 /* periph bank 4 config reg */
362 #define pb5cr 0x05 /* periph bank 5 config reg */
363 #define pb6cr 0x06 /* periph bank 6 config reg */
364 #define pb7cr 0x07 /* periph bank 7 config reg */
365 #define pb0ap 0x10 /* periph bank 0 access parameters */
366 #define pb1ap 0x11 /* periph bank 1 access parameters */
367 #define pb2ap 0x12 /* periph bank 2 access parameters */
368 #define pb3ap 0x13 /* periph bank 3 access parameters */
369 #define pb4ap 0x14 /* periph bank 4 access parameters */
370 #define pb5ap 0x15 /* periph bank 5 access parameters */
371 #define pb6ap 0x16 /* periph bank 6 access parameters */
372 #define pb7ap 0x17 /* periph bank 7 access parameters */
373 #define pbear 0x20 /* periph bus error addr reg */
374 #define pbesr 0x21 /* periph bus error status reg */
375 #define xbcfg 0x23 /* external bus configuration reg */
376 #define EBC0_CFG 0x23 /* external bus configuration reg */
377 #define xbcid 0x24 /* external bus core id reg */
379 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
380 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
382 /* PLB4 to PLB3 Bridge OUT */
383 #define P4P3_DCR_BASE 0x020
384 #define p4p3_esr0_read (P4P3_DCR_BASE+0x0)
385 #define p4p3_esr0_write (P4P3_DCR_BASE+0x1)
386 #define p4p3_eadr (P4P3_DCR_BASE+0x2)
387 #define p4p3_euadr (P4P3_DCR_BASE+0x3)
388 #define p4p3_esr1_read (P4P3_DCR_BASE+0x4)
389 #define p4p3_esr1_write (P4P3_DCR_BASE+0x5)
390 #define p4p3_confg (P4P3_DCR_BASE+0x6)
391 #define p4p3_pic (P4P3_DCR_BASE+0x7)
392 #define p4p3_peir (P4P3_DCR_BASE+0x8)
393 #define p4p3_rev (P4P3_DCR_BASE+0xA)
395 /* PLB3 to PLB4 Bridge IN */
396 #define P3P4_DCR_BASE 0x030
397 #define p3p4_esr0_read (P3P4_DCR_BASE+0x0)
398 #define p3p4_esr0_write (P3P4_DCR_BASE+0x1)
399 #define p3p4_eadr (P3P4_DCR_BASE+0x2)
400 #define p3p4_euadr (P3P4_DCR_BASE+0x3)
401 #define p3p4_esr1_read (P3P4_DCR_BASE+0x4)
402 #define p3p4_esr1_write (P3P4_DCR_BASE+0x5)
403 #define p3p4_confg (P3P4_DCR_BASE+0x6)
404 #define p3p4_pic (P3P4_DCR_BASE+0x7)
405 #define p3p4_peir (P3P4_DCR_BASE+0x8)
406 #define p3p4_rev (P3P4_DCR_BASE+0xA)
409 #define PLB3_DCR_BASE 0x070
410 #define plb3_revid (PLB3_DCR_BASE+0x2)
411 #define plb3_besr (PLB3_DCR_BASE+0x3)
412 #define plb3_bear (PLB3_DCR_BASE+0x6)
413 #define plb3_acr (PLB3_DCR_BASE+0x7)
415 /* PLB4 Arbiter - PowerPC440EP Pass1 */
416 #define PLB4_DCR_BASE 0x080
417 #define plb4_acr (PLB4_DCR_BASE+0x1)
418 #define plb4_revid (PLB4_DCR_BASE+0x2)
419 #define plb4_besr (PLB4_DCR_BASE+0x4)
420 #define plb4_bearl (PLB4_DCR_BASE+0x6)
421 #define plb4_bearh (PLB4_DCR_BASE+0x7)
423 #define PLB4_ACR_WRP (0x80000000 >> 7)
425 /* Nebula PLB4 Arbiter - PowerPC440EP */
426 #define PLB_ARBITER_BASE 0x80
428 #define plb0_revid (PLB_ARBITER_BASE+ 0x00)
429 #define plb0_acr (PLB_ARBITER_BASE+ 0x01)
430 #define plb0_acr_ppm_mask 0xF0000000
431 #define plb0_acr_ppm_fixed 0x00000000
432 #define plb0_acr_ppm_fair 0xD0000000
433 #define plb0_acr_hbu_mask 0x08000000
434 #define plb0_acr_hbu_disabled 0x00000000
435 #define plb0_acr_hbu_enabled 0x08000000
436 #define plb0_acr_rdp_mask 0x06000000
437 #define plb0_acr_rdp_disabled 0x00000000
438 #define plb0_acr_rdp_2deep 0x02000000
439 #define plb0_acr_rdp_3deep 0x04000000
440 #define plb0_acr_rdp_4deep 0x06000000
441 #define plb0_acr_wrp_mask 0x01000000
442 #define plb0_acr_wrp_disabled 0x00000000
443 #define plb0_acr_wrp_2deep 0x01000000
445 #define plb0_besrl (PLB_ARBITER_BASE+ 0x02)
446 #define plb0_besrh (PLB_ARBITER_BASE+ 0x03)
447 #define plb0_bearl (PLB_ARBITER_BASE+ 0x04)
448 #define plb0_bearh (PLB_ARBITER_BASE+ 0x05)
449 #define plb0_ccr (PLB_ARBITER_BASE+ 0x08)
451 #define plb1_acr (PLB_ARBITER_BASE+ 0x09)
452 #define plb1_acr_ppm_mask 0xF0000000
453 #define plb1_acr_ppm_fixed 0x00000000
454 #define plb1_acr_ppm_fair 0xD0000000
455 #define plb1_acr_hbu_mask 0x08000000
456 #define plb1_acr_hbu_disabled 0x00000000
457 #define plb1_acr_hbu_enabled 0x08000000
458 #define plb1_acr_rdp_mask 0x06000000
459 #define plb1_acr_rdp_disabled 0x00000000
460 #define plb1_acr_rdp_2deep 0x02000000
461 #define plb1_acr_rdp_3deep 0x04000000
462 #define plb1_acr_rdp_4deep 0x06000000
463 #define plb1_acr_wrp_mask 0x01000000
464 #define plb1_acr_wrp_disabled 0x00000000
465 #define plb1_acr_wrp_2deep 0x01000000
467 #define plb1_besrl (PLB_ARBITER_BASE+ 0x0A)
468 #define plb1_besrh (PLB_ARBITER_BASE+ 0x0B)
469 #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C)
470 #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D)
472 /* Pin Function Control Register 1 */
473 #define SDR0_PFC1 0x4101
474 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
475 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
476 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
477 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
478 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
479 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
480 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
481 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
482 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
483 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
484 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
485 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
486 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
487 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
488 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
489 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
490 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
491 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
492 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
493 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
494 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
495 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
496 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
497 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
499 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
500 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
501 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
502 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
504 /* USB Control Register */
505 #define SDR0_USB0 0x0320
506 #define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */
507 #define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
508 #define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
509 #define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */
510 #define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
511 #define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
513 /* Miscealleneaous Function Reg. */
514 #define SDR0_MFR 0x4300
515 #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
516 #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
517 #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
518 #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
519 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
520 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
521 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
522 #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
523 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
524 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
525 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
526 #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
527 #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
529 #define SDR0_MFR_ERRATA3_EN0 0x00800000
530 #define SDR0_MFR_ERRATA3_EN1 0x00400000
531 #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
532 #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
533 #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
534 #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
535 #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
537 #define GPT0_COMP6 0x00000098
538 #define GPT0_COMP5 0x00000094
539 #define GPT0_COMP4 0x00000090
540 #define GPT0_COMP3 0x0000008C
541 #define GPT0_COMP2 0x00000088
542 #define GPT0_COMP1 0x00000084
544 #define GPT0_MASK6 0x000000D8
545 #define GPT0_MASK5 0x000000D4
546 #define GPT0_MASK4 0x000000D0
547 #define GPT0_MASK3 0x000000CC
548 #define GPT0_MASK2 0x000000C8
549 #define GPT0_MASK1 0x000000C4
551 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
552 #define SDR0_USB2D0CR 0x0320
553 #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */
554 #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */
555 #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */
557 #define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */
558 #define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */
559 #define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */
561 #define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */
562 #define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */
563 #define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */
565 /* USB2 Host Control Register */
566 #define SDR0_USB2H0CR 0x0340
567 #define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */
568 #define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */
569 #define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */
570 #define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */
572 /* Pin Function Control Register 1 */
573 #define SDR0_PFC1 0x4101
574 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
575 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
576 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
578 #define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */
579 #define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */
580 #define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
581 #define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */
582 #define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */
583 #define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */
584 #define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */
585 #define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */
587 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
588 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
589 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
590 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
591 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
592 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
593 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
594 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
595 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
596 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
597 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
598 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
599 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
600 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
601 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
602 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
603 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
604 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
605 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
606 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
607 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
609 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
610 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
611 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
612 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
614 /* Ethernet PLL Configuration Register */
615 #define SDR0_PFC2 0x4102
616 #define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */
617 #define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */
618 #define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */
619 #define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */
621 #define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */
622 #define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */
623 #define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */
624 #define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */
625 #define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */
626 #define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */
627 #define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */
628 #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */
630 #define SDR0_PFC4 0x4104
632 /* USB2PHY0 Control Register */
633 #define SDR0_USB2PHY0CR 0x4103
634 #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */
635 #define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */
636 #define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */
638 #define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */
639 #define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */
640 #define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */
642 #define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */
643 #define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */
644 #define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */
646 #define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */
647 #define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */
648 #define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */
650 #define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */
651 #define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */
652 #define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */
654 #define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */
655 #define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */
656 #define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */
658 #define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */
659 #define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */
660 #define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */
662 #define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */
663 #define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */
664 #define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */
666 #define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */
667 #define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */
668 #define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */
670 #define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */
671 #define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/
672 #define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/
673 #define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/
675 /* Miscealleneaous Function Reg. */
676 #define SDR0_MFR 0x4300
677 #define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */
678 #define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000
679 #define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */
680 #define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000
681 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
682 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
683 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
684 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
685 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
686 #define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24)
687 #define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3)
689 #define SDR0_MFR_ERRATA3_EN0 0x00800000
690 #define SDR0_MFR_ERRATA3_EN1 0x00400000
691 #define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */
692 #define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */
693 #define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */
694 #define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */
695 #define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */
697 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */
699 /* CUST1 Customer Configuration Register1 */
700 #define SDR0_CUST1 0x4002
701 #define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */
702 #define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16)
703 #define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF)
705 /* Pin Function Control Register 0 */
706 #define SDR0_PFC0 0x4100
707 #define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */
708 #define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */
709 #define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */
710 #define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
711 #define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
713 /* Pin Function Control Register 1 */
714 #define SDR0_PFC1 0x4101
715 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
716 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
717 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
718 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
719 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
720 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
721 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
722 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */
723 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */
724 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
725 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
726 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
727 #define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */
728 #define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */
729 #define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */
730 #define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */
731 #define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */
732 #define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */
733 #define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */
734 #define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */
735 #define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */
736 #define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */
737 #define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */
738 #define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */
740 #define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */
741 #define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */
742 #define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */
743 #define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */
745 #endif /* 440EP || 440GR || 440EPX || 440GRX */
747 /*-----------------------------------------------------------------------------
749 +----------------------------------------------------------------------------*/
750 #if defined (CONFIG_440GX) || \
751 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
752 defined(CONFIG_460EX) || defined(CONFIG_460GT)
753 #define L2_CACHE_BASE 0x030
754 #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */
755 #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */
756 #define l2_cache_addr (L2_CACHE_BASE+0x02) /* L2 Cache Address */
757 #define l2_cache_data (L2_CACHE_BASE+0x03) /* L2 Cache Data */
758 #define l2_cache_stat (L2_CACHE_BASE+0x04) /* L2 Cache Status */
759 #define l2_cache_cver (L2_CACHE_BASE+0x05) /* L2 Cache Revision ID */
760 #define l2_cache_snp0 (L2_CACHE_BASE+0x06) /* L2 Cache Snoop reg 0 */
761 #define l2_cache_snp1 (L2_CACHE_BASE+0x07) /* L2 Cache Snoop reg 1 */
763 #endif /* CONFIG_440GX */
765 /*-----------------------------------------------------------------------------
767 +----------------------------------------------------------------------------*/
768 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
769 #define ISRAM0_DCR_BASE 0x380
771 #define ISRAM0_DCR_BASE 0x020
773 #define isram0_sb0cr (ISRAM0_DCR_BASE+0x00) /* SRAM bank config 0*/
774 #define isram0_sb1cr (ISRAM0_DCR_BASE+0x01) /* SRAM bank config 1*/
775 #define isram0_sb2cr (ISRAM0_DCR_BASE+0x02) /* SRAM bank config 2*/
776 #define isram0_sb3cr (ISRAM0_DCR_BASE+0x03) /* SRAM bank config 3*/
777 #define isram0_bear (ISRAM0_DCR_BASE+0x04) /* SRAM bus error addr reg */
778 #define isram0_besr0 (ISRAM0_DCR_BASE+0x05) /* SRAM bus error status reg 0 */
779 #define isram0_besr1 (ISRAM0_DCR_BASE+0x06) /* SRAM bus error status reg 1 */
780 #define isram0_pmeg (ISRAM0_DCR_BASE+0x07) /* SRAM power management */
781 #define isram0_cid (ISRAM0_DCR_BASE+0x08) /* SRAM bus core id reg */
782 #define isram0_revid (ISRAM0_DCR_BASE+0x09) /* SRAM bus revision id reg */
783 #define isram0_dpc (ISRAM0_DCR_BASE+0x0a) /* SRAM data parity check reg */
785 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
786 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
787 defined(CONFIG_460EX) || defined(CONFIG_460GT)
788 /* CUST0 Customer Configuration Register0 */
789 #define SDR0_CUST0 0x4000
790 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
791 #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
792 #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
793 #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
795 #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
796 #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
797 #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
799 #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
800 #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
801 #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
803 #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
804 #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
805 #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
807 #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
808 #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
809 #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
811 #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
812 #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
813 #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
815 #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
816 #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
817 #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
819 #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
820 #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
821 #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
823 #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
824 #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
825 #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
826 #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
827 #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
828 #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
829 #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
832 /*-----------------------------------------------------------------------------
834 +----------------------------------------------------------------------------*/
835 /* TODO: as needed */
837 /*-----------------------------------------------------------------------------
838 | Clocking, Power Management and Chip Control
839 +----------------------------------------------------------------------------*/
840 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
841 #define CNTRL_DCR_BASE 0x160
843 #define CNTRL_DCR_BASE 0x0b0
846 #define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */
847 #define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */
848 #define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */
850 #define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */
851 #define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */
852 #define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */
853 #define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */
855 #define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */
856 #define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */
857 #define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */
858 #define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */
860 #define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */
862 #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
863 #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
865 /*-----------------------------------------------------------------------------
866 | Universal interrupt controller
867 +----------------------------------------------------------------------------*/
868 #define UIC_SR 0x0 /* UIC status */
869 #define UIC_ER 0x2 /* UIC enable */
870 #define UIC_CR 0x3 /* UIC critical */
871 #define UIC_PR 0x4 /* UIC polarity */
872 #define UIC_TR 0x5 /* UIC triggering */
873 #define UIC_MSR 0x6 /* UIC masked status */
874 #define UIC_VR 0x7 /* UIC vector */
875 #define UIC_VCR 0x8 /* UIC vector configuration */
877 #define UIC0_DCR_BASE 0xc0
878 #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
879 #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
880 #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
881 #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
882 #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
883 #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
884 #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
885 #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
887 #define UIC1_DCR_BASE 0xd0
888 #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
889 #define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
890 #define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
891 #define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
892 #define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
893 #define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
894 #define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
895 #define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
897 #if defined(CONFIG_440SPE) || \
898 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
899 defined(CONFIG_460EX) || defined(CONFIG_460GT)
900 #define UIC2_DCR_BASE 0xe0
901 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
902 #define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
903 #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
904 #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
905 #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
906 #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
907 #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
908 #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
909 #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
911 #define UIC3_DCR_BASE 0xf0
912 #define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
913 #define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
914 #define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
915 #define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
916 #define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
917 #define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
918 #define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
919 #define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
920 #define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
921 #endif /* CONFIG_440SPE */
923 #if defined(CONFIG_440GX)
924 #define UIC2_DCR_BASE 0x210
925 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
926 #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
927 #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
928 #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
929 #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
930 #define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
931 #define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
932 #define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
935 #define UIC_DCR_BASE 0x200
936 #define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
937 #define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
938 #define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
939 #define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
940 #define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
941 #define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
942 #define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
943 #define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
944 #endif /* CONFIG_440GX */
946 /* The following is for compatibility with 405 code */
952 #define uicmsr uic0msr
954 #define uicvcr uic0vcr
956 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
957 /*----------------------------------------------------------------------------+
958 | Clock / Power-on-reset DCR's.
959 +----------------------------------------------------------------------------*/
960 #define CPR0_CLKUPD 0x20
961 #define CPR0_CLKUPD_BSY_MASK 0x80000000
962 #define CPR0_CLKUPD_BSY_COMPLETED 0x00000000
963 #define CPR0_CLKUPD_BSY_BUSY 0x80000000
964 #define CPR0_CLKUPD_CUI_MASK 0x80000000
965 #define CPR0_CLKUPD_CUI_DISABLE 0x00000000
966 #define CPR0_CLKUPD_CUI_ENABLE 0x80000000
967 #define CPR0_CLKUPD_CUD_MASK 0x40000000
968 #define CPR0_CLKUPD_CUD_DISABLE 0x00000000
969 #define CPR0_CLKUPD_CUD_ENABLE 0x40000000
971 #define CPR0_PLLC 0x40
972 #define CPR0_PLLC_RST_MASK 0x80000000
973 #define CPR0_PLLC_RST_PLLLOCKED 0x00000000
974 #define CPR0_PLLC_RST_PLLRESET 0x80000000
975 #define CPR0_PLLC_ENG_MASK 0x40000000
976 #define CPR0_PLLC_ENG_DISABLE 0x00000000
977 #define CPR0_PLLC_ENG_ENABLE 0x40000000
978 #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
979 #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
980 #define CPR0_PLLC_SRC_MASK 0x20000000
981 #define CPR0_PLLC_SRC_PLLOUTA 0x00000000
982 #define CPR0_PLLC_SRC_PLLOUTB 0x20000000
983 #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
984 #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
985 #define CPR0_PLLC_SEL_MASK 0x07000000
986 #define CPR0_PLLC_SEL_PLLOUT 0x00000000
987 #define CPR0_PLLC_SEL_CPU 0x01000000
988 #define CPR0_PLLC_SEL_EBC 0x05000000
989 #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
990 #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
991 #define CPR0_PLLC_TUNE_MASK 0x000003FF
992 #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
993 #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
995 #define CPR0_PLLD 0x60
996 #define CPR0_PLLD_FBDV_MASK 0x1F000000
997 #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
998 #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
999 #define CPR0_PLLD_FWDVA_MASK 0x000F0000
1000 #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
1001 #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
1002 #define CPR0_PLLD_FWDVB_MASK 0x00000700
1003 #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
1004 #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
1005 #define CPR0_PLLD_LFBDV_MASK 0x0000003F
1006 #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1007 #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1009 #define CPR0_PRIMAD 0x80
1010 #define CPR0_PRIMAD_PRADV0_MASK 0x07000000
1011 #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1012 #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1014 #define CPR0_PRIMBD 0xA0
1015 #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
1016 #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
1017 #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
1019 #define CPR0_OPBD 0xC0
1020 #define CPR0_OPBD_OPBDV0_MASK 0x03000000
1021 #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1022 #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1024 #define CPR0_PERD 0xE0
1025 #if !defined(CONFIG_440EPX)
1026 #define CPR0_PERD_PERDV0_MASK 0x03000000
1027 #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1028 #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1031 #define CPR0_MALD 0x100
1032 #define CPR0_MALD_MALDV0_MASK 0x03000000
1033 #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1034 #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
1036 #define CPR0_ICFG 0x140
1037 #define CPR0_ICFG_RLI_MASK 0x80000000
1038 #define CPR0_ICFG_RLI_RESETCPR 0x00000000
1039 #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
1040 #define CPR0_ICFG_ICS_MASK 0x00000007
1041 #define CPR0_ICFG_ICS_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
1042 #define CPR0_ICFG_ICS_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
1044 /************************/
1046 /************************/
1047 #define IIC0_MMIO_BASE 0xA0000400
1048 #define IIC1_MMIO_BASE 0xA0000500
1050 #endif /* CONFIG_440SP */
1052 /*-----------------------------------------------------------------------------
1054 +----------------------------------------------------------------------------*/
1055 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1056 #define DMA_DCR_BASE 0x200
1058 #define DMA_DCR_BASE 0x100
1060 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
1061 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
1062 #define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */
1063 #define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */
1064 #define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */
1065 #define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */
1066 #define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */
1067 #define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */
1068 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
1069 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
1070 #define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */
1071 #define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */
1072 #define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */
1073 #define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */
1074 #define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */
1075 #define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */
1076 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
1077 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
1078 #define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */
1079 #define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */
1080 #define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */
1081 #define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */
1082 #define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */
1083 #define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */
1084 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */
1085 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */
1086 #define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */
1087 #define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */
1088 #define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */
1089 #define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */
1090 #define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */
1091 #define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */
1092 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
1093 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
1094 #define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */
1095 #define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */
1097 /*-----------------------------------------------------------------------------
1098 | Memory Access Layer
1099 +----------------------------------------------------------------------------*/
1100 #define MAL_DCR_BASE 0x180
1101 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
1102 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
1103 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
1104 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
1105 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
1106 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
1107 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
1108 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
1109 #define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */
1110 #define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */
1111 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
1112 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
1113 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
1114 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
1115 #define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */
1116 #define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */
1117 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
1118 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
1119 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
1120 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */
1121 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
1122 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
1123 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
1124 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
1125 #if defined(CONFIG_440GX) || \
1126 defined(CONFIG_460EX) || defined(CONFIG_460GT)
1127 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
1128 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
1129 #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */
1130 #define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */
1131 #define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */
1132 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
1133 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
1134 #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
1135 #define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
1136 #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
1137 #endif /* CONFIG_440GX */
1140 /*---------------------------------------------------------------------------+
1141 | Universal interrupt controller 0 interrupts (UIC0)
1142 +---------------------------------------------------------------------------*/
1143 #if defined(CONFIG_440SP)
1144 #define UIC_U0 0x80000000 /* UART 0 */
1145 #define UIC_U1 0x40000000 /* UART 1 */
1146 #define UIC_IIC0 0x20000000 /* IIC */
1147 #define UIC_IIC1 0x10000000 /* IIC */
1148 #define UIC_PIM 0x08000000 /* PCI0 inbound message */
1149 #define UIC_PCRW 0x04000000 /* PCI0 command write register */
1150 #define UIC_PPM 0x02000000 /* PCI0 power management */
1151 #define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
1152 #define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
1153 #define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
1154 #define UIC_P1CRW 0x00200000 /* PCI1 command write register */
1155 #define UIC_P1PM 0x00100000 /* PCI1 power management */
1156 #define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
1157 #define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
1158 #define UIC_P2IM 0x00020000 /* PCI2 inbound message */
1159 #define UIC_P2CRW 0x00010000 /* PCI2 command register write */
1160 #define UIC_P2PM 0x00008000 /* PCI2 power management */
1161 #define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
1162 #define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
1163 #define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
1164 #define UIC_D0CSF 0x00000800 /* DMA0 command status */
1165 #define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
1166 #define UIC_D1CSF 0x00000200 /* DMA1 command status */
1167 #define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
1168 #define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
1169 #define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
1170 #define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
1171 #define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
1172 #define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
1173 #define UIC_GPTCT 0x00000004 /* GPT count timer */
1174 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1175 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1176 #elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
1177 #define UIC_U0 0x80000000 /* UART 0 */
1178 #define UIC_U1 0x40000000 /* UART 1 */
1179 #define UIC_IIC0 0x20000000 /* IIC */
1180 #define UIC_IIC1 0x10000000 /* IIC */
1181 #define UIC_PIM 0x08000000 /* PCI inbound message */
1182 #define UIC_PCRW 0x04000000 /* PCI command register write */
1183 #define UIC_PPM 0x02000000 /* PCI power management */
1184 #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
1185 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
1186 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
1187 #define UIC_MTE 0x00200000 /* MAL TXEOB */
1188 #define UIC_MRE 0x00100000 /* MAL RXEOB */
1189 #define UIC_D0 0x00080000 /* DMA channel 0 */
1190 #define UIC_D1 0x00040000 /* DMA channel 1 */
1191 #define UIC_D2 0x00020000 /* DMA channel 2 */
1192 #define UIC_D3 0x00010000 /* DMA channel 3 */
1193 #define UIC_RSVD0 0x00008000 /* Reserved */
1194 #define UIC_RSVD1 0x00004000 /* Reserved */
1195 #define UIC_CT0 0x00002000 /* GPT compare timer 0 */
1196 #define UIC_CT1 0x00001000 /* GPT compare timer 1 */
1197 #define UIC_CT2 0x00000800 /* GPT compare timer 2 */
1198 #define UIC_CT3 0x00000400 /* GPT compare timer 3 */
1199 #define UIC_CT4 0x00000200 /* GPT compare timer 4 */
1200 #define UIC_EIR0 0x00000100 /* External interrupt 0 */
1201 #define UIC_EIR1 0x00000080 /* External interrupt 1 */
1202 #define UIC_EIR2 0x00000040 /* External interrupt 2 */
1203 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
1204 #define UIC_EIR4 0x00000010 /* External interrupt 4 */
1205 #define UIC_EIR5 0x00000008 /* External interrupt 5 */
1206 #define UIC_EIR6 0x00000004 /* External interrupt 6 */
1207 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1208 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1210 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1212 #define UIC_U0 0x80000000 /* UART 0 */
1213 #define UIC_U1 0x40000000 /* UART 1 */
1214 #define UIC_IIC0 0x20000000 /* IIC */
1215 #define UIC_KRD 0x10000000 /* Kasumi Ready for data */
1216 #define UIC_KDA 0x08000000 /* Kasumi Data Available */
1217 #define UIC_PCRW 0x04000000 /* PCI command register write */
1218 #define UIC_PPM 0x02000000 /* PCI power management */
1219 #define UIC_IIC1 0x01000000 /* IIC */
1220 #define UIC_SPI 0x00800000 /* SPI */
1221 #define UIC_EPCISER 0x00400000 /* External PCI SERR */
1222 #define UIC_MTE 0x00200000 /* MAL TXEOB */
1223 #define UIC_MRE 0x00100000 /* MAL RXEOB */
1224 #define UIC_D0 0x00080000 /* DMA channel 0 */
1225 #define UIC_D1 0x00040000 /* DMA channel 1 */
1226 #define UIC_D2 0x00020000 /* DMA channel 2 */
1227 #define UIC_D3 0x00010000 /* DMA channel 3 */
1228 #define UIC_UD0 0x00008000 /* UDMA irq 0 */
1229 #define UIC_UD1 0x00004000 /* UDMA irq 1 */
1230 #define UIC_UD2 0x00002000 /* UDMA irq 2 */
1231 #define UIC_UD3 0x00001000 /* UDMA irq 3 */
1232 #define UIC_HSB2D 0x00000800 /* USB2.0 Device */
1233 #define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */
1234 #define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */
1235 #define UIC_EIP94 0x00000100 /* Security EIP94 */
1236 #define UIC_ETH0 0x00000080 /* Emac 0 */
1237 #define UIC_ETH1 0x00000040 /* Emac 1 */
1238 #define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */
1239 #define UIC_EIR4 0x00000010 /* External interrupt 4 */
1240 #define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */
1241 #define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */
1242 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1243 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1245 /* For compatibility with 405 code */
1246 #define UIC_MAL_TXEOB UIC_MTE
1247 #define UIC_MAL_RXEOB UIC_MRE
1249 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1251 #define UIC_RSVD0 0x80000000 /* N/A - unused */
1252 #define UIC_U1 0x40000000 /* UART 1 */
1253 #define UIC_IIC0 0x20000000 /* IIC */
1254 #define UIC_IIC1 0x10000000 /* IIC */
1255 #define UIC_PIM 0x08000000 /* PCI inbound message */
1256 #define UIC_PCRW 0x04000000 /* PCI command register write */
1257 #define UIC_PPM 0x02000000 /* PCI power management */
1258 #define UIC_PCIVPD 0x01000000 /* PCI VPD */
1259 #define UIC_MSI0 0x00800000 /* PCI MSI level 0 */
1260 #define UIC_EIR0 0x00400000 /* External interrupt 0 */
1261 #define UIC_UIC2NC 0x00200000 /* UIC2 non-critical interrupt */
1262 #define UIC_UIC2C 0x00100000 /* UIC2 critical interrupt */
1263 #define UIC_D0 0x00080000 /* DMA channel 0 */
1264 #define UIC_D1 0x00040000 /* DMA channel 1 */
1265 #define UIC_D2 0x00020000 /* DMA channel 2 */
1266 #define UIC_D3 0x00010000 /* DMA channel 3 */
1267 #define UIC_UIC3NC 0x00008000 /* UIC3 non-critical interrupt */
1268 #define UIC_UIC3C 0x00004000 /* UIC3 critical interrupt */
1269 #define UIC_EIR1 0x00002000 /* External interrupt 1 */
1270 #define UIC_TRNGDA 0x00001000 /* TRNG data available */
1271 #define UIC_PKAR1 0x00000800 /* PKA ready (PKA[1]) */
1272 #define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
1273 #define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
1274 #define UIC_I2OID 0x00000100 /* I2O inbound door bell */
1275 #define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
1276 #define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
1277 #define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
1278 #define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
1279 #define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
1280 #define UIC_EIP94 0x00000004 /* Security EIP94 */
1281 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1282 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1284 #elif !defined(CONFIG_440SPE)
1285 #define UIC_U0 0x80000000 /* UART 0 */
1286 #define UIC_U1 0x40000000 /* UART 1 */
1287 #define UIC_IIC0 0x20000000 /* IIC */
1288 #define UIC_IIC1 0x10000000 /* IIC */
1289 #define UIC_PIM 0x08000000 /* PCI inbound message */
1290 #define UIC_PCRW 0x04000000 /* PCI command register write */
1291 #define UIC_PPM 0x02000000 /* PCI power management */
1292 #define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
1293 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
1294 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
1295 #define UIC_MTE 0x00200000 /* MAL TXEOB */
1296 #define UIC_MRE 0x00100000 /* MAL RXEOB */
1297 #define UIC_D0 0x00080000 /* DMA channel 0 */
1298 #define UIC_D1 0x00040000 /* DMA channel 1 */
1299 #define UIC_D2 0x00020000 /* DMA channel 2 */
1300 #define UIC_D3 0x00010000 /* DMA channel 3 */
1301 #define UIC_RSVD0 0x00008000 /* Reserved */
1302 #define UIC_RSVD1 0x00004000 /* Reserved */
1303 #define UIC_CT0 0x00002000 /* GPT compare timer 0 */
1304 #define UIC_CT1 0x00001000 /* GPT compare timer 1 */
1305 #define UIC_CT2 0x00000800 /* GPT compare timer 2 */
1306 #define UIC_CT3 0x00000400 /* GPT compare timer 3 */
1307 #define UIC_CT4 0x00000200 /* GPT compare timer 4 */
1308 #define UIC_EIR0 0x00000100 /* External interrupt 0 */
1309 #define UIC_EIR1 0x00000080 /* External interrupt 1 */
1310 #define UIC_EIR2 0x00000040 /* External interrupt 2 */
1311 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
1312 #define UIC_EIR4 0x00000010 /* External interrupt 4 */
1313 #define UIC_EIR5 0x00000008 /* External interrupt 5 */
1314 #define UIC_EIR6 0x00000004 /* External interrupt 6 */
1315 #define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
1316 #define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
1317 #endif /* CONFIG_440GX */
1319 /* For compatibility with 405 code */
1320 #define UIC_MAL_TXEOB UIC_MTE
1321 #define UIC_MAL_RXEOB UIC_MRE
1323 /*---------------------------------------------------------------------------+
1324 | Universal interrupt controller 1 interrupts (UIC1)
1325 +---------------------------------------------------------------------------*/
1326 #if defined(CONFIG_440SP)
1327 #define UIC_EIR0 0x80000000 /* External interrupt 0 */
1328 #define UIC_MS 0x40000000 /* MAL SERR */
1329 #define UIC_MTDE 0x20000000 /* MAL TXDE */
1330 #define UIC_MRDE 0x10000000 /* MAL RXDE */
1331 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1332 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1333 #define UIC_MTE 0x02000000 /* MAL TXEOB */
1334 #define UIC_MRE 0x01000000 /* MAL RXEOB */
1335 #define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
1336 #define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
1337 #define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
1338 #define UIC_L2C 0x00100000 /* L2 cache */
1339 #define UIC_CT0 0x00080000 /* GPT compare timer 0 */
1340 #define UIC_CT1 0x00040000 /* GPT compare timer 1 */
1341 #define UIC_CT2 0x00020000 /* GPT compare timer 2 */
1342 #define UIC_CT3 0x00010000 /* GPT compare timer 3 */
1343 #define UIC_CT4 0x00008000 /* GPT compare timer 4 */
1344 #define UIC_EIR1 0x00004000 /* External interrupt 1 */
1345 #define UIC_EIR2 0x00002000 /* External interrupt 2 */
1346 #define UIC_EIR3 0x00001000 /* External interrupt 3 */
1347 #define UIC_EIR4 0x00000800 /* External interrupt 4 */
1348 #define UIC_EIR5 0x00000400 /* External interrupt 5 */
1349 #define UIC_DMAE 0x00000200 /* DMA error */
1350 #define UIC_I2OE 0x00000100 /* I2O error */
1351 #define UIC_SRE 0x00000080 /* Serial ROM error */
1352 #define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
1353 #define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
1354 #define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
1355 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1356 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1357 #define UIC_ETH1 0x00000002 /* Reserved */
1358 #define UIC_XOR 0x00000001 /* XOR */
1359 #elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
1360 #define UIC_MS 0x80000000 /* MAL SERR */
1361 #define UIC_MTDE 0x40000000 /* MAL TXDE */
1362 #define UIC_MRDE 0x20000000 /* MAL RXDE */
1363 #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
1364 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1365 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1366 #define UIC_EBMI 0x02000000 /* EBMI interrupt status */
1367 #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
1368 #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
1369 #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
1370 #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
1371 #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
1372 #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
1373 #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
1374 #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
1375 #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
1376 #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
1377 #define UIC_PPMI 0x00004000 /* PPM interrupt status */
1378 #define UIC_EIR7 0x00002000 /* External interrupt 7 */
1379 #define UIC_EIR8 0x00001000 /* External interrupt 8 */
1380 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
1381 #define UIC_EIR10 0x00000400 /* External interrupt 10 */
1382 #define UIC_EIR11 0x00000200 /* External interrupt 11 */
1383 #define UIC_EIR12 0x00000100 /* External interrupt 12 */
1384 #define UIC_SRE 0x00000080 /* Serial ROM error */
1385 #define UIC_RSVD2 0x00000040 /* Reserved */
1386 #define UIC_RSVD3 0x00000020 /* Reserved */
1387 #define UIC_PAE 0x00000010 /* PCI asynchronous error */
1388 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1389 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1390 #define UIC_ETH1 0x00000002 /* Ethernet 1 */
1391 #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
1393 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1395 #define UIC_EIR2 0x80000000 /* External interrupt 2 */
1396 #define UIC_U0 0x40000000 /* UART 0 */
1397 #define UIC_SPI 0x20000000 /* SPI */
1398 #define UIC_TRNGAL 0x10000000 /* TRNG alarm */
1399 #define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
1400 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1401 #define UIC_NDFC 0x02000000 /* NDFC */
1402 #define UIC_EIPPKPSE 0x01000000 /* EIPPKP slave error */
1403 #define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
1404 #define UIC_P0MSI2 0x00400000 /* PCI0 MSI level 2 */
1405 #define UIC_P0MSI3 0x00200000 /* PCI0 MSI level 3 */
1406 #define UIC_L2C 0x00100000 /* L2 cache */
1407 #define UIC_CT0 0x00080000 /* GPT compare timer 0 */
1408 #define UIC_CT1 0x00040000 /* GPT compare timer 1 */
1409 #define UIC_CT2 0x00020000 /* GPT compare timer 2 */
1410 #define UIC_CT3 0x00010000 /* GPT compare timer 3 */
1411 #define UIC_CT4 0x00008000 /* GPT compare timer 4 */
1412 #define UIC_CT5 0x00004000 /* GPT compare timer 5 */
1413 #define UIC_CT6 0x00002000 /* GPT compare timer 6 */
1414 #define UIC_GPTDC 0x00001000 /* GPT decrementer pulse */
1415 #define UIC_EIR3 0x00000800 /* External interrupt 3 */
1416 #define UIC_EIR4 0x00000400 /* External interrupt 4 */
1417 #define UIC_DMAE 0x00000200 /* DMA error */
1418 #define UIC_I2OE 0x00000100 /* I2O error */
1419 #define UIC_SRE 0x00000080 /* Serial ROM error */
1420 #define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
1421 #define UIC_EIR5 0x00000020 /* External interrupt 5 */
1422 #define UIC_EIR6 0x00000010 /* External interrupt 6 */
1423 #define UIC_U2 0x00000008 /* UART 2 */
1424 #define UIC_U3 0x00000004 /* UART 3 */
1425 #define UIC_EIR7 0x00000002 /* External interrupt 7 */
1426 #define UIC_EIR8 0x00000001 /* External interrupt 8 */
1428 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1430 #define UIC_MS 0x80000000 /* MAL SERR */
1431 #define UIC_MTDE 0x40000000 /* MAL TXDE */
1432 #define UIC_MRDE 0x20000000 /* MAL RXDE */
1433 #define UIC_U2 0x10000000 /* UART 2 */
1434 #define UIC_U3 0x08000000 /* UART 3 */
1435 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1436 #define UIC_NDFC 0x02000000 /* NDFC */
1437 #define UIC_KSLE 0x01000000 /* KASUMI slave error */
1438 #define UIC_CT5 0x00800000 /* GPT compare timer 5 */
1439 #define UIC_CT6 0x00400000 /* GPT compare timer 6 */
1440 #define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */
1441 #define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */
1442 #define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */
1443 #define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */
1444 #define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */
1445 #define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */
1446 #define UIC_CT0 0x00008000 /* GPT compare timer 0 */
1447 #define UIC_CT1 0x00004000 /* GPT compare timer 1 */
1448 #define UIC_EIR7 0x00002000 /* External interrupt 7 */
1449 #define UIC_EIR8 0x00001000 /* External interrupt 8 */
1450 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
1451 #define UIC_CT2 0x00000400 /* GPT compare timer 2 */
1452 #define UIC_CT3 0x00000200 /* GPT compare timer 3 */
1453 #define UIC_CT4 0x00000100 /* GPT compare timer 4 */
1454 #define UIC_SRE 0x00000080 /* Serial ROM error */
1455 #define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */
1456 #define UIC_RSVD0 0x00000020 /* Reserved */
1457 #define UIC_EPCIPER 0x00000010 /* External PCI PERR */
1458 #define UIC_EIR0 0x00000008 /* External interrupt 0 */
1459 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1460 #define UIC_EIR1 0x00000002 /* External interrupt 1 */
1461 #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
1463 /* For compatibility with 405 code */
1464 #define UIC_MAL_SERR UIC_MS
1465 #define UIC_MAL_TXDE UIC_MTDE
1466 #define UIC_MAL_RXDE UIC_MRDE
1467 #define UIC_ENET UIC_ETH0
1469 #elif !defined(CONFIG_440SPE)
1470 #define UIC_MS 0x80000000 /* MAL SERR */
1471 #define UIC_MTDE 0x40000000 /* MAL TXDE */
1472 #define UIC_MRDE 0x20000000 /* MAL RXDE */
1473 #define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
1474 #define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
1475 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1476 #define UIC_EBMI 0x02000000 /* EBMI interrupt status */
1477 #define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
1478 #define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
1479 #define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
1480 #define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
1481 #define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
1482 #define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
1483 #define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
1484 #define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
1485 #define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
1486 #define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
1487 #define UIC_PPMI 0x00004000 /* PPM interrupt status */
1488 #define UIC_EIR7 0x00002000 /* External interrupt 7 */
1489 #define UIC_EIR8 0x00001000 /* External interrupt 8 */
1490 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
1491 #define UIC_EIR10 0x00000400 /* External interrupt 10 */
1492 #define UIC_EIR11 0x00000200 /* External interrupt 11 */
1493 #define UIC_EIR12 0x00000100 /* External interrupt 12 */
1494 #define UIC_SRE 0x00000080 /* Serial ROM error */
1495 #define UIC_RSVD2 0x00000040 /* Reserved */
1496 #define UIC_RSVD3 0x00000020 /* Reserved */
1497 #define UIC_PAE 0x00000010 /* PCI asynchronous error */
1498 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1499 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1500 #define UIC_ETH1 0x00000002 /* Ethernet 1 */
1501 #define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
1502 #endif /* CONFIG_440SP */
1504 /* For compatibility with 405 code */
1505 #define UIC_MAL_SERR UIC_MS
1506 #define UIC_MAL_TXDE UIC_MTDE
1507 #define UIC_MAL_RXDE UIC_MRDE
1508 #define UIC_ENET UIC_ETH0
1510 /*---------------------------------------------------------------------------+
1511 | Universal interrupt controller 2 interrupts (UIC2)
1512 +---------------------------------------------------------------------------*/
1513 #if defined(CONFIG_440GX)
1514 #define UIC_ETH2 0x80000000 /* Ethernet 2 */
1515 #define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
1516 #define UIC_ETH3 0x20000000 /* Ethernet 3 */
1517 #define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */
1518 #define UIC_TAH0 0x08000000 /* TAH 0 */
1519 #define UIC_TAH1 0x04000000 /* TAH 1 */
1520 #define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */
1521 #define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */
1522 #define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */
1523 #define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */
1524 #define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */
1525 #define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */
1526 #define UIC_IMUTO 0x00080000 /* IMU timeout */
1527 #define UIC_MSI12 0x00040000 /* PCI MSI level 12 */
1528 #define UIC_MSI13 0x00020000 /* PCI MSI level 13 */
1529 #define UIC_MSI14 0x00010000 /* PCI MSI level 14 */
1530 #define UIC_MSI15 0x00008000 /* PCI MSI level 15 */
1531 #define UIC_EIR13 0x00004000 /* External interrupt 13 */
1532 #define UIC_EIR14 0x00002000 /* External interrupt 14 */
1533 #define UIC_EIR15 0x00001000 /* External interrupt 15 */
1534 #define UIC_EIR16 0x00000800 /* External interrupt 16 */
1535 #define UIC_EIR17 0x00000400 /* External interrupt 17 */
1536 #define UIC_PCIVPD 0x00000200 /* PCI VPD */
1537 #define UIC_L2C 0x00000100 /* L2 Cache */
1538 #define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */
1539 #define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */
1540 #define UIC_RSVD26 0x00000020 /* Reserved */
1541 #define UIC_RSVD27 0x00000010 /* Reserved */
1542 #define UIC_RSVD28 0x00000008 /* Reserved */
1543 #define UIC_RSVD29 0x00000004 /* Reserved */
1544 #define UIC_RSVD30 0x00000002 /* Reserved */
1545 #define UIC_RSVD31 0x00000001 /* Reserved */
1547 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1549 #define UIC_TAH0 0x80000000 /* TAHOE 0 */
1550 #define UIC_TAH1 0x40000000 /* TAHOE 1 */
1551 #define UIC_EIR9 0x20000000 /* External interrupt 9 */
1552 #define UIC_MS 0x10000000 /* MAL SERR */
1553 #define UIC_MTDE 0x08000000 /* MAL TXDE */
1554 #define UIC_MRDE 0x04000000 /* MAL RXDE */
1555 #define UIC_MTE 0x02000000 /* MAL TXEOB */
1556 #define UIC_MRE 0x01000000 /* MAL RXEOB */
1557 #define UIC_MCTX0 0x00800000 /* MAL interrupt coalescence TX0 */
1558 #define UIC_MCTX1 0x00400000 /* MAL interrupt coalescence TX1 */
1559 #define UIC_MCTX2 0x00200000 /* MAL interrupt coalescence TX2 */
1560 #define UIC_MCTX3 0x00100000 /* MAL interrupt coalescence TX3 */
1561 #define UIC_MCTR0 0x00080000 /* MAL interrupt coalescence TR0 */
1562 #define UIC_MCTR1 0x00040000 /* MAL interrupt coalescence TR1 */
1563 #define UIC_MCTR2 0x00020000 /* MAL interrupt coalescence TR2 */
1564 #define UIC_MCTR3 0x00010000 /* MAL interrupt coalescence TR3 */
1565 #define UIC_ETH0 0x00008000 /* Ethernet 0 */
1566 #define UIC_ETH1 0x00004000 /* Ethernet 1 */
1567 #define UIC_ETH2 0x00002000 /* Ethernet 2 */
1568 #define UIC_ETH3 0x00001000 /* Ethernet 3 */
1569 #define UIC_EWU0 0x00000800 /* Ethernet 0 wakeup */
1570 #define UIC_EWU1 0x00000400 /* Ethernet 1 wakeup */
1571 #define UIC_EWU2 0x00000200 /* Ethernet 2 wakeup */
1572 #define UIC_EWU3 0x00000100 /* Ethernet 3 wakeup */
1573 #define UIC_EIR10 0x00000080 /* External interrupt 10 */
1574 #define UIC_EIR11 0x00000040 /* External interrupt 11 */
1575 #define UIC_RSVD2 0x00000020 /* Reserved */
1576 #define UIC_PLB4XAHB 0x00000010 /* PLB4XAHB / AHBARB error */
1577 #define UIC_OTG 0x00000008 /* USB2.0 OTG */
1578 #define UIC_EHCI 0x00000004 /* USB2.0 Host EHCI */
1579 #define UIC_OHCI 0x00000002 /* USB2.0 Host OHCI */
1580 #define UIC_OHCISMI 0x00000001 /* USB2.0 Host OHCI SMI */
1582 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
1584 #define UIC_EIR5 0x80000000 /* External interrupt 5 */
1585 #define UIC_EIR6 0x40000000 /* External interrupt 6 */
1586 #define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */
1587 #define UIC_EIR2 0x10000000 /* External interrupt 2 */
1588 #define UIC_EIR3 0x08000000 /* External interrupt 3 */
1589 #define UIC_DDR2 0x04000000 /* DDR2 sdram */
1590 #define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */
1591 #define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */
1592 #define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */
1593 #define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */
1595 #endif /* CONFIG_440GX */
1597 /*---------------------------------------------------------------------------+
1598 | Universal interrupt controller Base 0 interrupts (UICB0)
1599 +---------------------------------------------------------------------------*/
1600 #if defined(CONFIG_440GX)
1601 #define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
1602 #define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
1603 #define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
1604 #define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */
1605 #define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */
1606 #define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */
1608 #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
1609 UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
1611 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1613 #define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */
1614 #define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */
1615 #define UICB0_UIC2NCI 0x00200000 /* UIC2 Noncritical Interrupt */
1616 #define UICB0_UIC2CI 0x00100000 /* UIC2 Critical Interrupt */
1617 #define UICB0_UIC3NCI 0x00008000 /* UIC3 Noncritical Interrupt */
1618 #define UICB0_UIC3CI 0x00004000 /* UIC3 Critical Interrupt */
1620 #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
1621 UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
1623 #elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
1625 #define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */
1626 #define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */
1627 #define UICB0_UIC2CI 0x00000004 /* UIC2 Critical Interrupt */
1628 #define UICB0_UIC2NCI 0x00000008 /* UIC2 Noncritical Interrupt */
1630 #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
1631 UICB0_UIC1CI | UICB0_UIC2NCI)
1633 #elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
1634 defined(CONFIG_440EP) || defined(CONFIG_440GR)
1636 #define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */
1637 #define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */
1639 #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI)
1641 #endif /* CONFIG_440GX */
1642 /*---------------------------------------------------------------------------+
1643 | Universal interrupt controller interrupts
1644 +---------------------------------------------------------------------------*/
1645 #if defined(CONFIG_440SPE)
1646 /*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */
1647 /*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */
1648 #define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */
1649 #define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */
1650 #define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */
1651 #define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */
1652 #define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */
1653 #define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */
1655 #define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
1656 UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
1657 /*---------------------------------------------------------------------------+
1658 | Universal interrupt controller 0 interrupts (UIC0)
1659 +---------------------------------------------------------------------------*/
1660 #define UIC_U0 0x80000000 /* UART 0 */
1661 #define UIC_U1 0x40000000 /* UART 1 */
1662 #define UIC_IIC0 0x20000000 /* IIC */
1663 #define UIC_IIC1 0x10000000 /* IIC */
1664 #define UIC_PIM 0x08000000 /* PCI inbound message */
1665 #define UIC_PCRW 0x04000000 /* PCI command register write */
1666 #define UIC_PPM 0x02000000 /* PCI power management */
1667 #define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */
1668 #define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */
1669 #define UIC_EIR15 0x00400000 /* External intp 15 */
1670 #define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */
1671 #define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */
1672 #define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */
1673 #define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */
1674 #define UIC_EIR14 0x00002000 /* External interrupt 14 */
1675 #define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */
1676 #define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */
1677 #define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
1678 #define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
1679 #define UIC_I2OID 0x00000100 /* I2O inbound door bell */
1680 #define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
1681 #define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
1682 #define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
1683 #define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
1684 #define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
1685 #define UIC_CPTCNT 0x00000004 /* GPT Count Timer */
1686 /*---------------------------------------------------------------------------+
1687 | Universal interrupt controller 1 interrupts (UIC1)
1688 +---------------------------------------------------------------------------*/
1689 #define UIC_EIR13 0x80000000 /* externei intp 13 */
1690 #define UIC_MS 0x40000000 /* MAL SERR */
1691 #define UIC_MTDE 0x20000000 /* MAL TXDE */
1692 #define UIC_MRDE 0x10000000 /* MAL RXDE */
1693 #define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
1694 #define UIC_EBCO 0x04000000 /* EBCO interrupt status */
1695 #define UIC_MTE 0x02000000 /* MAL TXEOB */
1696 #define UIC_MRE 0x01000000 /* MAL RXEOB */
1697 #define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
1698 #define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
1699 #define UIC_MSI3 0x00200000 /* PCI MSI level 3 */
1700 #define UIC_L2C 0x00100000 /* L2 cache */
1701 #define UIC_CT0 0x00080000 /* GPT compare timer 0 */
1702 #define UIC_CT1 0x00040000 /* GPT compare timer 1 */
1703 #define UIC_CT2 0x00020000 /* GPT compare timer 2 */
1704 #define UIC_CT3 0x00010000 /* GPT compare timer 3 */
1705 #define UIC_CT4 0x00008000 /* GPT compare timer 4 */
1706 #define UIC_EIR12 0x00004000 /* External interrupt 12 */
1707 #define UIC_EIR11 0x00002000 /* External interrupt 11 */
1708 #define UIC_EIR10 0x00001000 /* External interrupt 10 */
1709 #define UIC_EIR9 0x00000800 /* External interrupt 9 */
1710 #define UIC_EIR8 0x00000400 /* External interrupt 8 */
1711 #define UIC_DMAE 0x00000200 /* dma error */
1712 #define UIC_I2OE 0x00000100 /* i2o error */
1713 #define UIC_SRE 0x00000080 /* Serial ROM error */
1714 #define UIC_PCIXAE 0x00000040 /* Pcix0 async error */
1715 #define UIC_EIR7 0x00000020 /* External interrupt 7 */
1716 #define UIC_EIR6 0x00000010 /* External interrupt 6 */
1717 #define UIC_ETH0 0x00000008 /* Ethernet 0 */
1718 #define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
1719 #define UIC_ETH1 0x00000002 /* reserved */
1720 #define UIC_XOR 0x00000001 /* xor */
1722 /*---------------------------------------------------------------------------+
1723 | Universal interrupt controller 2 interrupts (UIC2)
1724 +---------------------------------------------------------------------------*/
1725 #define UIC_PEOAL 0x80000000 /* PE0 AL */
1726 #define UIC_PEOVA 0x40000000 /* PE0 VPD access */
1727 #define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */
1728 #define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */
1729 #define UIC_PE0TCR 0x08000000 /* PE0 TCR */
1730 #define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */
1731 #define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */
1732 #define UIC_PE1AL 0x00800000 /* PE1 AL */
1733 #define UIC_PE1VA 0x00400000 /* PE1 VPD access */
1734 #define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */
1735 #define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */
1736 #define UIC_PE1TCR 0x00080000 /* PE1 TCR */
1737 #define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */
1738 #define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */
1739 #define UIC_PE2AL 0x00008000 /* PE2 AL */
1740 #define UIC_PE2VA 0x00004000 /* PE2 VPD access */
1741 #define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */
1742 #define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */
1743 #define UIC_PE2TCR 0x00000800 /* PE2 TCR */
1744 #define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */
1745 #define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */
1746 #define UIC_EIR5 0x00000080 /* External interrupt 5 */
1747 #define UIC_EIR4 0x00000040 /* External interrupt 4 */
1748 #define UIC_EIR3 0x00000020 /* External interrupt 3 */
1749 #define UIC_EIR2 0x00000010 /* External interrupt 2 */
1750 #define UIC_EIR1 0x00000008 /* External interrupt 1 */
1751 #define UIC_EIR0 0x00000004 /* External interrupt 0 */
1752 #endif /* CONFIG_440SPE */
1754 /*-----------------------------------------------------------------------------+
1755 | External Bus Controller Bit Settings
1756 +-----------------------------------------------------------------------------*/
1757 #define EBC_CFGADDR_MASK 0x0000003F
1759 #define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&0xFFF00000)<<0)
1760 #define EBC_BXCR_BS_MASK 0x000E0000
1761 #define EBC_BXCR_BS_1MB 0x00000000
1762 #define EBC_BXCR_BS_2MB 0x00020000
1763 #define EBC_BXCR_BS_4MB 0x00040000
1764 #define EBC_BXCR_BS_8MB 0x00060000
1765 #define EBC_BXCR_BS_16MB 0x00080000
1766 #define EBC_BXCR_BS_32MB 0x000A0000
1767 #define EBC_BXCR_BS_64MB 0x000C0000
1768 #define EBC_BXCR_BS_128MB 0x000E0000
1769 #define EBC_BXCR_BU_MASK 0x00018000
1770 #define EBC_BXCR_BU_R 0x00008000
1771 #define EBC_BXCR_BU_W 0x00010000
1772 #define EBC_BXCR_BU_RW 0x00018000
1773 #define EBC_BXCR_BW_MASK 0x00006000
1774 #define EBC_BXCR_BW_8BIT 0x00000000
1775 #define EBC_BXCR_BW_16BIT 0x00002000
1776 #define EBC_BXCR_BW_32BIT 0x00006000
1777 #define EBC_BXAP_BME_ENABLED 0x80000000
1778 #define EBC_BXAP_BME_DISABLED 0x00000000
1779 #define EBC_BXAP_TWT_ENCODE(n) ((((unsigned long)(n))&0xFF)<<23)
1780 #define EBC_BXAP_BCE_DISABLE 0x00000000
1781 #define EBC_BXAP_BCE_ENABLE 0x00400000
1782 #define EBC_BXAP_BCT_MASK 0x00300000
1783 #define EBC_BXAP_BCT_2TRANS 0x00000000
1784 #define EBC_BXAP_BCT_4TRANS 0x00100000
1785 #define EBC_BXAP_BCT_8TRANS 0x00200000
1786 #define EBC_BXAP_BCT_16TRANS 0x00300000
1787 #define EBC_BXAP_CSN_ENCODE(n) ((((unsigned long)(n))&0x3)<<18)
1788 #define EBC_BXAP_OEN_ENCODE(n) ((((unsigned long)(n))&0x3)<<16)
1789 #define EBC_BXAP_WBN_ENCODE(n) ((((unsigned long)(n))&0x3)<<14)
1790 #define EBC_BXAP_WBF_ENCODE(n) ((((unsigned long)(n))&0x3)<<12)
1791 #define EBC_BXAP_TH_ENCODE(n) ((((unsigned long)(n))&0x7)<<9)
1792 #define EBC_BXAP_RE_ENABLED 0x00000100
1793 #define EBC_BXAP_RE_DISABLED 0x00000000
1794 #define EBC_BXAP_SOR_DELAYED 0x00000000
1795 #define EBC_BXAP_SOR_NONDELAYED 0x00000080
1796 #define EBC_BXAP_BEM_WRITEONLY 0x00000000
1797 #define EBC_BXAP_BEM_RW 0x00000040
1798 #define EBC_BXAP_PEN_DISABLED 0x00000000
1800 #define EBC_CFG_LE_MASK 0x80000000
1801 #define EBC_CFG_LE_UNLOCK 0x00000000
1802 #define EBC_CFG_LE_LOCK 0x80000000
1803 #define EBC_CFG_PTD_MASK 0x40000000
1804 #define EBC_CFG_PTD_ENABLE 0x00000000
1805 #define EBC_CFG_PTD_DISABLE 0x40000000
1806 #define EBC_CFG_RTC_MASK 0x38000000
1807 #define EBC_CFG_RTC_16PERCLK 0x00000000
1808 #define EBC_CFG_RTC_32PERCLK 0x08000000
1809 #define EBC_CFG_RTC_64PERCLK 0x10000000
1810 #define EBC_CFG_RTC_128PERCLK 0x18000000
1811 #define EBC_CFG_RTC_256PERCLK 0x20000000
1812 #define EBC_CFG_RTC_512PERCLK 0x28000000
1813 #define EBC_CFG_RTC_1024PERCLK 0x30000000
1814 #define EBC_CFG_RTC_2048PERCLK 0x38000000
1815 #define EBC_CFG_ATC_MASK 0x04000000
1816 #define EBC_CFG_ATC_HI 0x00000000
1817 #define EBC_CFG_ATC_PREVIOUS 0x04000000
1818 #define EBC_CFG_DTC_MASK 0x02000000
1819 #define EBC_CFG_DTC_HI 0x00000000
1820 #define EBC_CFG_DTC_PREVIOUS 0x02000000
1821 #define EBC_CFG_CTC_MASK 0x01000000
1822 #define EBC_CFG_CTC_HI 0x00000000
1823 #define EBC_CFG_CTC_PREVIOUS 0x01000000
1824 #define EBC_CFG_OEO_MASK 0x00800000
1825 #define EBC_CFG_OEO_HI 0x00000000
1826 #define EBC_CFG_OEO_PREVIOUS 0x00800000
1827 #define EBC_CFG_EMC_MASK 0x00400000
1828 #define EBC_CFG_EMC_NONDEFAULT 0x00000000
1829 #define EBC_CFG_EMC_DEFAULT 0x00400000
1830 #define EBC_CFG_PME_MASK 0x00200000
1831 #define EBC_CFG_PME_DISABLE 0x00000000
1832 #define EBC_CFG_PME_ENABLE 0x00200000
1833 #define EBC_CFG_PMT_MASK 0x001F0000
1834 #define EBC_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
1835 #define EBC_CFG_PR_MASK 0x0000C000
1836 #define EBC_CFG_PR_16 0x00000000
1837 #define EBC_CFG_PR_32 0x00004000
1838 #define EBC_CFG_PR_64 0x00008000
1839 #define EBC_CFG_PR_128 0x0000C000
1841 /*-----------------------------------------------------------------------------+
1843 +-----------------------------------------------------------------------------*/
1844 #if defined(CONFIG_440SP)
1845 #define SDR0_SRST 0x0200
1847 #define SDR0_DDR0 0x00E1
1848 #define SDR0_DDR0_DPLLRST 0x80000000
1849 #define SDR0_DDR0_DDRM_MASK 0x60000000
1850 #define SDR0_DDR0_DDRM_DDR1 0x20000000
1851 #define SDR0_DDR0_DDRM_DDR2 0x40000000
1852 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
1853 #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
1854 #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
1855 #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
1858 #if defined(CONFIG_440SPE)
1859 #define SDR0_CP440 0x0180
1860 #define SDR0_CP440_ERPN_MASK 0x30000000
1861 #define SDR0_CP440_ERPN_MASK_HI 0x3000
1862 #define SDR0_CP440_ERPN_MASK_LO 0x0000
1863 #define SDR0_CP440_ERPN_EBC 0x10000000
1864 #define SDR0_CP440_ERPN_EBC_HI 0x1000
1865 #define SDR0_CP440_ERPN_EBC_LO 0x0000
1866 #define SDR0_CP440_ERPN_PCI 0x20000000
1867 #define SDR0_CP440_ERPN_PCI_HI 0x2000
1868 #define SDR0_CP440_ERPN_PCI_LO 0x0000
1869 #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
1870 #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
1871 #define SDR0_CP440_NTO1_MASK 0x00000002
1872 #define SDR0_CP440_NTO1_NTOP 0x00000000
1873 #define SDR0_CP440_NTO1_NTO1 0x00000002
1874 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
1875 #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
1877 #define SDR0_SDSTP0 0x0020
1878 #define SDR0_SDSTP0_ENG_MASK 0x80000000
1879 #define SDR0_SDSTP0_ENG_PLLDIS 0x00000000
1880 #define SDR0_SDSTP0_ENG_PLLENAB 0x80000000
1881 #define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1882 #define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1883 #define SDR0_SDSTP0_SRC_MASK 0x40000000
1884 #define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000
1885 #define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000
1886 #define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1887 #define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1888 #define SDR0_SDSTP0_SEL_MASK 0x38000000
1889 #define SDR0_SDSTP0_SEL_PLLOUT 0x00000000
1890 #define SDR0_SDSTP0_SEL_CPU 0x08000000
1891 #define SDR0_SDSTP0_SEL_EBC 0x28000000
1892 #define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27)
1893 #define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07)
1894 #define SDR0_SDSTP0_TUNE_MASK 0x07FE0000
1895 #define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17)
1896 #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF)
1897 #define SDR0_SDSTP0_FBDV_MASK 0x0001F000
1898 #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
1899 #define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1)
1900 #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00
1901 #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8)
1902 #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1)
1903 #define SDR0_SDSTP0_FWDVB_MASK 0x000000E0
1904 #define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5)
1905 #define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1)
1906 #define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C
1907 #define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2)
1908 #define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1)
1909 #define SDR0_SDSTP0_OPBDV0_MASK 0x00000003
1910 #define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0)
1911 #define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1)
1914 #define SDR0_SDSTP1 0x0021
1915 #define SDR0_SDSTP1_LFBDV_MASK 0xFC000000
1916 #define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26)
1917 #define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F)
1918 #define SDR0_SDSTP1_PERDV0_MASK 0x03000000
1919 #define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
1920 #define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03)
1921 #define SDR0_SDSTP1_MALDV0_MASK 0x00C00000
1922 #define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22)
1923 #define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
1924 #define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000
1925 #define SDR0_SDSTP1_DDR1_MODE 0x00100000
1926 #define SDR0_SDSTP1_DDR2_MODE 0x00200000
1927 #define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20)
1928 #define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03)
1929 #define SDR0_SDSTP1_ERPN_MASK 0x00080000
1930 #define SDR0_SDSTP1_ERPN_EBC 0x00000000
1931 #define SDR0_SDSTP1_ERPN_PCI 0x00080000
1932 #define SDR0_SDSTP1_PAE_MASK 0x00040000
1933 #define SDR0_SDSTP1_PAE_DISABLE 0x00000000
1934 #define SDR0_SDSTP1_PAE_ENABLE 0x00040000
1935 #define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
1936 #define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
1937 #define SDR0_SDSTP1_PHCE_MASK 0x00020000
1938 #define SDR0_SDSTP1_PHCE_DISABLE 0x00000000
1939 #define SDR0_SDSTP1_PHCE_ENABLE 0x00020000
1940 #define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
1941 #define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
1942 #define SDR0_SDSTP1_PISE_MASK 0x00010000
1943 #define SDR0_SDSTP1_PISE_DISABLE 0x00000000
1944 #define SDR0_SDSTP1_PISE_ENABLE 0x00001000
1945 #define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
1946 #define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
1947 #define SDR0_SDSTP1_PCWE_MASK 0x00008000
1948 #define SDR0_SDSTP1_PCWE_DISABLE 0x00000000
1949 #define SDR0_SDSTP1_PCWE_ENABLE 0x00008000
1950 #define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
1951 #define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
1952 #define SDR0_SDSTP1_PPIM_MASK 0x00007800
1953 #define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
1954 #define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
1955 #define SDR0_SDSTP1_PR64E_MASK 0x00000400
1956 #define SDR0_SDSTP1_PR64E_DISABLE 0x00000000
1957 #define SDR0_SDSTP1_PR64E_ENABLE 0x00000400
1958 #define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10)
1959 #define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01)
1960 #define SDR0_SDSTP1_PXFS_MASK 0x00000300
1961 #define SDR0_SDSTP1_PXFS_100_133 0x00000000
1962 #define SDR0_SDSTP1_PXFS_66_100 0x00000100
1963 #define SDR0_SDSTP1_PXFS_50_66 0x00000200
1964 #define SDR0_SDSTP1_PXFS_0_50 0x00000300
1965 #define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
1966 #define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
1967 #define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */
1968 #define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */
1969 #define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */
1970 #define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */
1971 #define SDR0_SDSTP1_DBGEN_FUNC 0x00000000
1972 #define SDR0_SDSTP1_DBGEN_TRACE 0x00000010
1973 #define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */
1974 #define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */
1975 #define SDR0_SDSTP1_ETH_MASK 0x00000004
1976 #define SDR0_SDSTP1_ETH_10_100 0x00000000
1977 #define SDR0_SDSTP1_ETH_GIGA 0x00000004
1978 #define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2)
1979 #define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01)
1980 #define SDR0_SDSTP1_NTO1_MASK 0x00000001
1981 #define SDR0_SDSTP1_NTO1_DISABLE 0x00000000
1982 #define SDR0_SDSTP1_NTO1_ENABLE 0x00000001
1983 #define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0)
1984 #define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01)
1986 #define SDR0_SDSTP2 0x0022
1987 #define SDR0_SDSTP2_P1AE_MASK 0x80000000
1988 #define SDR0_SDSTP2_P1AE_DISABLE 0x00000000
1989 #define SDR0_SDSTP2_P1AE_ENABLE 0x80000000
1990 #define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
1991 #define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
1992 #define SDR0_SDSTP2_P1HCE_MASK 0x40000000
1993 #define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000
1994 #define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000
1995 #define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
1996 #define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
1997 #define SDR0_SDSTP2_P1ISE_MASK 0x20000000
1998 #define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000
1999 #define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000
2000 #define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2001 #define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2002 #define SDR0_SDSTP2_P1CWE_MASK 0x10000000
2003 #define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000
2004 #define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000
2005 #define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2006 #define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2007 #define SDR0_SDSTP2_P1PIM_MASK 0x0F000000
2008 #define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2009 #define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2010 #define SDR0_SDSTP2_P1R64E_MASK 0x00800000
2011 #define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000
2012 #define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000
2013 #define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2014 #define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2015 #define SDR0_SDSTP2_P1XFS_MASK 0x00600000
2016 #define SDR0_SDSTP2_P1XFS_100_133 0x00000000
2017 #define SDR0_SDSTP2_P1XFS_66_100 0x00200000
2018 #define SDR0_SDSTP2_P1XFS_50_66 0x00400000
2019 #define SDR0_SDSTP2_P1XFS_0_50 0x00600000
2020 #define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2021 #define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2022 #define SDR0_SDSTP2_P2AE_MASK 0x00040000
2023 #define SDR0_SDSTP2_P2AE_DISABLE 0x00000000
2024 #define SDR0_SDSTP2_P2AE_ENABLE 0x00040000
2025 #define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18)
2026 #define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01)
2027 #define SDR0_SDSTP2_P2HCE_MASK 0x00020000
2028 #define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000
2029 #define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000
2030 #define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17)
2031 #define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01)
2032 #define SDR0_SDSTP2_P2ISE_MASK 0x00010000
2033 #define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000
2034 #define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000
2035 #define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16)
2036 #define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01)
2037 #define SDR0_SDSTP2_P2CWE_MASK 0x00008000
2038 #define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000
2039 #define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000
2040 #define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15)
2041 #define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01)
2042 #define SDR0_SDSTP2_P2PIM_MASK 0x00007800
2043 #define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11)
2044 #define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F)
2045 #define SDR0_SDSTP2_P2XFS_MASK 0x00000300
2046 #define SDR0_SDSTP2_P2XFS_100_133 0x00000000
2047 #define SDR0_SDSTP2_P2XFS_66_100 0x00000100
2048 #define SDR0_SDSTP2_P2XFS_50_66 0x00000200
2049 #define SDR0_SDSTP2_P2XFS_0_50 0x00000100
2050 #define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
2051 #define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
2053 #define SDR0_SDSTP3 0x0023
2055 #define SDR0_PINSTP 0x0040
2056 #define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */
2057 #define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */
2058 #define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */
2059 #define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */
2060 #define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */
2061 #define SDR0_SDCS 0x0060
2062 #define SDR0_ECID0 0x0080
2063 #define SDR0_ECID1 0x0081
2064 #define SDR0_ECID2 0x0082
2065 #define SDR0_JTAG 0x00C0
2067 #define SDR0_DDR0 0x00E1
2068 #define SDR0_DDR0_DPLLRST 0x80000000
2069 #define SDR0_DDR0_DDRM_MASK 0x60000000
2070 #define SDR0_DDR0_DDRM_DDR1 0x20000000
2071 #define SDR0_DDR0_DDRM_DDR2 0x40000000
2072 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
2073 #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
2074 #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
2075 #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
2077 #define SDR0_UART0 0x0120
2078 #define SDR0_UART1 0x0121
2079 #define SDR0_UART2 0x0122
2080 #define SDR0_UARTX_UXICS_MASK 0xF0000000
2081 #define SDR0_UARTX_UXICS_PLB 0x20000000
2082 #define SDR0_UARTX_UXEC_MASK 0x00800000
2083 #define SDR0_UARTX_UXEC_INT 0x00000000
2084 #define SDR0_UARTX_UXEC_EXT 0x00800000
2085 #define SDR0_UARTX_UXDIV_MASK 0x000000FF
2086 #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
2087 #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
2089 #define SDR0_CP440 0x0180
2090 #define SDR0_CP440_ERPN_MASK 0x30000000
2091 #define SDR0_CP440_ERPN_MASK_HI 0x3000
2092 #define SDR0_CP440_ERPN_MASK_LO 0x0000
2093 #define SDR0_CP440_ERPN_EBC 0x10000000
2094 #define SDR0_CP440_ERPN_EBC_HI 0x1000
2095 #define SDR0_CP440_ERPN_EBC_LO 0x0000
2096 #define SDR0_CP440_ERPN_PCI 0x20000000
2097 #define SDR0_CP440_ERPN_PCI_HI 0x2000
2098 #define SDR0_CP440_ERPN_PCI_LO 0x0000
2099 #define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
2100 #define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
2101 #define SDR0_CP440_NTO1_MASK 0x00000002
2102 #define SDR0_CP440_NTO1_NTOP 0x00000000
2103 #define SDR0_CP440_NTO1_NTO1 0x00000002
2104 #define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
2105 #define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
2107 #define SDR0_XCR0 0x01C0
2108 #define SDR0_XCR1 0x01C3
2109 #define SDR0_XCR2 0x01C6
2110 #define SDR0_XCRn_PAE_MASK 0x80000000
2111 #define SDR0_XCRn_PAE_DISABLE 0x00000000
2112 #define SDR0_XCRn_PAE_ENABLE 0x80000000
2113 #define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2114 #define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2115 #define SDR0_XCRn_PHCE_MASK 0x40000000
2116 #define SDR0_XCRn_PHCE_DISABLE 0x00000000
2117 #define SDR0_XCRn_PHCE_ENABLE 0x40000000
2118 #define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2119 #define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2120 #define SDR0_XCRn_PISE_MASK 0x20000000
2121 #define SDR0_XCRn_PISE_DISABLE 0x00000000
2122 #define SDR0_XCRn_PISE_ENABLE 0x20000000
2123 #define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2124 #define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2125 #define SDR0_XCRn_PCWE_MASK 0x10000000
2126 #define SDR0_XCRn_PCWE_DISABLE 0x00000000
2127 #define SDR0_XCRn_PCWE_ENABLE 0x10000000
2128 #define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2129 #define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2130 #define SDR0_XCRn_PPIM_MASK 0x0F000000
2131 #define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2132 #define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2133 #define SDR0_XCRn_PR64E_MASK 0x00800000
2134 #define SDR0_XCRn_PR64E_DISABLE 0x00000000
2135 #define SDR0_XCRn_PR64E_ENABLE 0x00800000
2136 #define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2137 #define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2138 #define SDR0_XCRn_PXFS_MASK 0x00600000
2139 #define SDR0_XCRn_PXFS_100_133 0x00000000
2140 #define SDR0_XCRn_PXFS_66_100 0x00200000
2141 #define SDR0_XCRn_PXFS_50_66 0x00400000
2142 #define SDR0_XCRn_PXFS_0_33 0x00600000
2143 #define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2144 #define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2146 #define SDR0_XPLLC0 0x01C1
2147 #define SDR0_XPLLD0 0x01C2
2148 #define SDR0_XPLLC1 0x01C4
2149 #define SDR0_XPLLD1 0x01C5
2150 #define SDR0_XPLLC2 0x01C7
2151 #define SDR0_XPLLD2 0x01C8
2152 #define SDR0_SRST 0x0200
2153 #define SDR0_SLPIPE 0x0220
2155 #define SDR0_AMP0 0x0240
2156 #define SDR0_AMP0_PRIORITY 0xFFFF0000
2157 #define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00
2158 #define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF
2160 #define SDR0_AMP1 0x0241
2161 #define SDR0_AMP1_PRIORITY 0xFC000000
2162 #define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000
2163 #define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF
2165 #define SDR0_MIRQ0 0x0260
2166 #define SDR0_MIRQ1 0x0261
2167 #define SDR0_MALTBL 0x0280
2168 #define SDR0_MALRBL 0x02A0
2169 #define SDR0_MALTBS 0x02C0
2170 #define SDR0_MALRBS 0x02E0
2172 /* Reserved for Customer Use */
2173 #define SDR0_CUST0 0x4000
2174 #define SDR0_CUST0_AUTONEG_MASK 0x8000000
2175 #define SDR0_CUST0_NO_AUTONEG 0x0000000
2176 #define SDR0_CUST0_AUTONEG 0x8000000
2177 #define SDR0_CUST0_ETH_FORCE_MASK 0x6000000
2178 #define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000
2179 #define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000
2180 #define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000
2181 #define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000
2182 #define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000
2183 #define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000
2185 #define SDR0_SDSTP4 0x4001
2186 #define SDR0_CUST1 0x4002
2187 #define SDR0_SDSTP5 0x4003
2188 #define SDR0_CUST2 0x4004
2189 #define SDR0_SDSTP6 0x4005
2190 #define SDR0_CUST3 0x4006
2191 #define SDR0_SDSTP7 0x4007
2193 #define SDR0_PFC0 0x4100
2194 #define SDR0_PFC0_GPIO_0 0x80000000
2195 #define SDR0_PFC0_PCIX0REQ2_N 0x00000000
2196 #define SDR0_PFC0_GPIO_1 0x40000000
2197 #define SDR0_PFC0_PCIX0REQ3_N 0x00000000
2198 #define SDR0_PFC0_GPIO_2 0x20000000
2199 #define SDR0_PFC0_PCIX0GNT2_N 0x00000000
2200 #define SDR0_PFC0_GPIO_3 0x10000000
2201 #define SDR0_PFC0_PCIX0GNT3_N 0x00000000
2202 #define SDR0_PFC0_GPIO_4 0x08000000
2203 #define SDR0_PFC0_PCIX1REQ2_N 0x00000000
2204 #define SDR0_PFC0_GPIO_5 0x04000000
2205 #define SDR0_PFC0_PCIX1REQ3_N 0x00000000
2206 #define SDR0_PFC0_GPIO_6 0x02000000
2207 #define SDR0_PFC0_PCIX1GNT2_N 0x00000000
2208 #define SDR0_PFC0_GPIO_7 0x01000000
2209 #define SDR0_PFC0_PCIX1GNT3_N 0x00000000
2210 #define SDR0_PFC0_GPIO_8 0x00800000
2211 #define SDR0_PFC0_PERREADY 0x00000000
2212 #define SDR0_PFC0_GPIO_9 0x00400000
2213 #define SDR0_PFC0_PERCS1_N 0x00000000
2214 #define SDR0_PFC0_GPIO_10 0x00200000
2215 #define SDR0_PFC0_PERCS2_N 0x00000000
2216 #define SDR0_PFC0_GPIO_11 0x00100000
2217 #define SDR0_PFC0_IRQ0 0x00000000
2218 #define SDR0_PFC0_GPIO_12 0x00080000
2219 #define SDR0_PFC0_IRQ1 0x00000000
2220 #define SDR0_PFC0_GPIO_13 0x00040000
2221 #define SDR0_PFC0_IRQ2 0x00000000
2222 #define SDR0_PFC0_GPIO_14 0x00020000
2223 #define SDR0_PFC0_IRQ3 0x00000000
2224 #define SDR0_PFC0_GPIO_15 0x00010000
2225 #define SDR0_PFC0_IRQ4 0x00000000
2226 #define SDR0_PFC0_GPIO_16 0x00008000
2227 #define SDR0_PFC0_IRQ5 0x00000000
2228 #define SDR0_PFC0_GPIO_17 0x00004000
2229 #define SDR0_PFC0_PERBE0_N 0x00000000
2230 #define SDR0_PFC0_GPIO_18 0x00002000
2231 #define SDR0_PFC0_PCI0GNT0_N 0x00000000
2232 #define SDR0_PFC0_GPIO_19 0x00001000
2233 #define SDR0_PFC0_PCI0GNT1_N 0x00000000
2234 #define SDR0_PFC0_GPIO_20 0x00000800
2235 #define SDR0_PFC0_PCI0REQ0_N 0x00000000
2236 #define SDR0_PFC0_GPIO_21 0x00000400
2237 #define SDR0_PFC0_PCI0REQ1_N 0x00000000
2238 #define SDR0_PFC0_GPIO_22 0x00000200
2239 #define SDR0_PFC0_PCI1GNT0_N 0x00000000
2240 #define SDR0_PFC0_GPIO_23 0x00000100
2241 #define SDR0_PFC0_PCI1GNT1_N 0x00000000
2242 #define SDR0_PFC0_GPIO_24 0x00000080
2243 #define SDR0_PFC0_PCI1REQ0_N 0x00000000
2244 #define SDR0_PFC0_GPIO_25 0x00000040
2245 #define SDR0_PFC0_PCI1REQ1_N 0x00000000
2246 #define SDR0_PFC0_GPIO_26 0x00000020
2247 #define SDR0_PFC0_PCI2GNT0_N 0x00000000
2248 #define SDR0_PFC0_GPIO_27 0x00000010
2249 #define SDR0_PFC0_PCI2GNT1_N 0x00000000
2250 #define SDR0_PFC0_GPIO_28 0x00000008
2251 #define SDR0_PFC0_PCI2REQ0_N 0x00000000
2252 #define SDR0_PFC0_GPIO_29 0x00000004
2253 #define SDR0_PFC0_PCI2REQ1_N 0x00000000
2254 #define SDR0_PFC0_GPIO_30 0x00000002
2255 #define SDR0_PFC0_UART1RX 0x00000000
2256 #define SDR0_PFC0_GPIO_31 0x00000001
2257 #define SDR0_PFC0_UART1TX 0x00000000
2259 #define SDR0_PFC1 0x4101
2260 #define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000
2261 #define SDR0_PFC1_UART1_DSR_DTR 0x00000000
2262 #define SDR0_PFC1_UART1_CTS_RTS 0x02000000
2263 #define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000
2264 #define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000
2265 #define SDR0_PFC1_UART2_IN_SERVICE 0x01000000
2266 #define SDR0_PFC1_ETH_GIGA_MASK 0x00200000
2267 #define SDR0_PFC1_ETH_10_100 0x00000000
2268 #define SDR0_PFC1_ETH_GIGA 0x00200000
2269 #define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21)
2270 #define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
2271 #define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */
2272 #define SDR0_PFC1_CPU_NO_TRACE 0x00000000
2273 #define SDR0_PFC1_CPU_TRACE 0x00080000
2274 #define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */
2275 #define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */
2277 #define SDR0_MFR 0x4300
2278 #endif /* CONFIG_440SPE */
2280 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
2281 /* Pin Function Control Register 0 (SDR0_PFC0) */
2282 #define SDR0_PFC0 0x4100
2283 #define SDR0_PFC0_DBG 0x00008000 /* debug enable */
2284 #define SDR0_PFC0_G49E 0x00004000 /* GPIO 49 enable */
2285 #define SDR0_PFC0_G50E 0x00002000 /* GPIO 50 enable */
2286 #define SDR0_PFC0_G51E 0x00001000 /* GPIO 51 enable */
2287 #define SDR0_PFC0_G52E 0x00000800 /* GPIO 52 enable */
2288 #define SDR0_PFC0_G53E 0x00000400 /* GPIO 53 enable */
2289 #define SDR0_PFC0_G54E 0x00000200 /* GPIO 54 enable */
2290 #define SDR0_PFC0_G55E 0x00000100 /* GPIO 55 enable */
2291 #define SDR0_PFC0_G56E 0x00000080 /* GPIO 56 enable */
2292 #define SDR0_PFC0_G57E 0x00000040 /* GPIO 57 enable */
2293 #define SDR0_PFC0_G58E 0x00000020 /* GPIO 58 enable */
2294 #define SDR0_PFC0_G59E 0x00000010 /* GPIO 59 enable */
2295 #define SDR0_PFC0_G60E 0x00000008 /* GPIO 60 enable */
2296 #define SDR0_PFC0_G61E 0x00000004 /* GPIO 61 enable */
2297 #define SDR0_PFC0_G62E 0x00000002 /* GPIO 62 enable */
2298 #define SDR0_PFC0_G63E 0x00000001 /* GPIO 63 enable */
2300 /* Pin Function Control Register 1 (SDR0_PFC1) */
2301 #define SDR0_PFC1 0x4101
2302 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */
2303 #define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */
2304 #define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */
2305 #define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */
2306 #define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */
2307 #define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */
2308 #define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */
2309 #define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins*/
2310 #define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins*/
2311 #define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */
2312 #define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */
2313 #define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */
2315 /* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */
2316 #define SDR0_ETH_PLL 0x4102
2317 #define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/
2318 #define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000 /* Ethernet reference clock */
2319 #define SDR0_ETH_PLL_BYPASS 0x08000000 /* bypass mode enable */
2320 #define SDR0_ETH_PLL_STOPCLK 0x04000000 /* output clock disable */
2321 #define SDR0_ETH_PLL_TUNE_MASK 0x03FF0000 /* loop stability tuning bits */
2322 #define SDR0_ETH_PLL_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3ff)<<16)
2323 #define SDR0_ETH_PLL_MULTI_MASK 0x0000FF00 /* frequency multiplication */
2324 #define SDR0_ETH_PLL_MULTI_ENCODE(n) ((((unsigned long)(n))&0xff)<<8)
2325 #define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0 /* PLLOUTB/C frequency */
2326 #define SDR0_ETH_PLL_RANGEB_ENCODE(n) ((((unsigned long)(n))&0x0f)<<4)
2327 #define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F /* PLLOUTA frequency */
2328 #define SDR0_ETH_PLL_RANGEA_ENCODE(n) (((unsigned long)(n))&0x0f)
2330 /* Ethernet Configuration Register (SDR0_ETH_CFG) */
2331 #define SDR0_ETH_CFG 0x4103
2332 #define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */
2333 #define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */
2334 #define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */
2335 #define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */
2336 #define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */
2337 #define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */
2338 #define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */
2339 #define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */
2340 #define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */
2341 #define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */
2342 #define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */
2343 #define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */
2344 #define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */
2345 #define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */
2346 #define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */
2347 #define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */
2348 #define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */
2349 #define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */
2350 #define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */
2351 #define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */
2352 #define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */
2353 #define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */
2354 #define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */
2355 #define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */
2356 #define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */
2357 #define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */
2358 #define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */
2359 #define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */
2361 #define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4
2362 #define SDR0_ETH_CFG_ZMII_MII_MODE 0x00
2363 #define SDR0_ETH_CFG_ZMII_SMII_MODE 0x01
2364 #define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10
2365 #define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11
2367 /* Miscealleneaous Function Reg. (SDR0_MFR) */
2368 #define SDR0_MFR 0x4300
2369 #define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */
2370 #define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */
2371 #define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */
2372 #define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */
2373 #define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */
2374 #define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */
2375 #define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */
2376 #define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */
2377 #define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */
2378 #define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */
2379 #define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */
2380 #define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */
2381 #define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */
2382 #define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */
2383 #define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */
2384 #define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */
2385 #define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */
2386 #define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */
2387 #define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */
2388 #define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */
2390 /* EMACx TX Status Register (SDR0_EMACxTXST)*/
2391 #define SDR0_EMAC0TXST 0x4400
2392 #define SDR0_EMAC1TXST 0x4401
2393 #define SDR0_EMAC2TXST 0x4402
2394 #define SDR0_EMAC3TXST 0x4403
2396 #define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */
2397 #define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */
2398 #define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */
2399 #define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */
2400 #define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */
2401 #define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */
2402 #define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */
2403 #define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */
2404 #define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */
2405 #define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */
2406 #define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */
2407 #define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */
2408 #define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */
2409 #define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */
2410 #define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */
2411 #define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */
2412 #define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */
2413 #define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */
2414 #define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */
2415 #define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */
2416 #define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */
2417 #define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */
2418 #define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */
2419 #define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */
2421 /* EMACx RX Status Register (SDR0_EMACxRXST)*/
2422 #define SDR0_EMAC0RXST 0x4404
2423 #define SDR0_EMAC1RXST 0x4405
2424 #define SDR0_EMAC2RXST 0x4406
2425 #define SDR0_EMAC3RXST 0x4407
2427 #define SDR0_EMACxRXST_FOR 0x20000000 /* RX FIFO overrun */
2428 #define SDR0_EMACxRXST_BC 0x10000000 /* broadcast address */
2429 #define SDR0_EMACxRXST_MC 0x08000000 /* multicast address */
2430 #define SDR0_EMACxRXST_UC 0x04000000 /* unicast address */
2431 #define SDR0_EMACxRXST_UPR_MASK 0x03800000 /* user priority field */
2432 #define SDR0_EMACxRXST_UPR_ENCODE(n) ((((unsigned long)(n))&0x07)<<23)
2433 #define SDR0_EMACxRXST_VLAN 0x00400000 /* RX VLAN tagged frame */
2434 #define SDR0_EMACxRXST_LOOP 0x00200000 /* received in loop-back mode */
2435 #define SDR0_EMACxRXST_UOP 0x00100000 /* RX unsupported opcode */
2436 #define SDR0_EMACxRXST_CPF 0x00080000 /* RX control pause frame */
2437 #define SDR0_EMACxRXST_CF 0x00040000 /* RX control frame*/
2438 #define SDR0_EMACxRXST_MSIZ 0x00020000 /* 1024-MaxSize bytes recieved*/
2439 #define SDR0_EMACxRXST_1023 0x00010000 /* 512-1023 bytes received */
2440 #define SDR0_EMACxRXST_511 0x00008000 /* 128-511 bytes received */
2441 #define SDR0_EMACxRXST_255 0x00004000 /* 128-255 bytes received */
2442 #define SDR0_EMACxRXST_127 0x00002000 /* 65-127 bytes received */
2443 #define SDR0_EMACxRXST_64 0x00001000 /* 64 bytes received */
2444 #define SDR0_EMACxRXST_RUNT 0x00000800 /* runt frame */
2445 #define SDR0_EMACxRXST_SEVT 0x00000400 /* short event */
2446 #define SDR0_EMACxRXST_AERR 0x00000200 /* alignment error */
2447 #define SDR0_EMACxRXST_SERR 0x00000100 /* received with symbol error */
2448 #define SDR0_EMACxRXST_BURST 0x00000040 /* received burst */
2449 #define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */
2450 #define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */
2451 #define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */
2452 #define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */
2453 #define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */
2454 #define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */
2456 /* EMACx TX Status Register (SDR0_EMACxREJCNT)*/
2457 #define SDR0_EMAC0REJCNT 0x4408
2458 #define SDR0_EMAC1REJCNT 0x4409
2459 #define SDR0_EMAC2REJCNT 0x440A
2460 #define SDR0_EMAC3REJCNT 0x440B
2462 #define SDR0_DDR0 0x00E1
2463 #define SDR0_DDR0_DPLLRST 0x80000000
2464 #define SDR0_DDR0_DDRM_MASK 0x60000000
2465 #define SDR0_DDR0_DDRM_DDR1 0x20000000
2466 #define SDR0_DDR0_DDRM_DDR2 0x40000000
2467 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29)
2468 #define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03)
2469 #define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0)
2470 #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF)
2472 #define AHB_TOP 0xA4
2473 #define AHB_BOT 0xA5
2474 #define SDR0_AHB_CFG 0x370
2475 #define SDR0_USB2HOST_CFG 0x371
2476 #endif /* CONFIG_460EX || CONFIG_460GT */
2478 #define SDR0_SDCS_SDD (0x80000000 >> 31)
2480 #if defined(CONFIG_440GP)
2481 #define CPC0_STRP1_PAE_MASK (0x80000000 >> 11)
2482 #define CPC0_STRP1_PISE_MASK (0x80000000 >> 13)
2483 #endif /* defined(CONFIG_440GP) */
2484 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
2485 #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13)
2486 #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15)
2487 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
2488 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
2489 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2490 #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21)
2491 #define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27)
2492 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
2494 #define SDR0_UARTX_UXICS_MASK 0xF0000000
2495 #define SDR0_UARTX_UXICS_PLB 0x20000000
2496 #define SDR0_UARTX_UXEC_MASK 0x00800000
2497 #define SDR0_UARTX_UXEC_INT 0x00000000
2498 #define SDR0_UARTX_UXEC_EXT 0x00800000
2499 #define SDR0_UARTX_UXDTE_MASK 0x00400000
2500 #define SDR0_UARTX_UXDTE_DISABLE 0x00000000
2501 #define SDR0_UARTX_UXDTE_ENABLE 0x00400000
2502 #define SDR0_UARTX_UXDRE_MASK 0x00200000
2503 #define SDR0_UARTX_UXDRE_DISABLE 0x00000000
2504 #define SDR0_UARTX_UXDRE_ENABLE 0x00200000
2505 #define SDR0_UARTX_UXDC_MASK 0x00100000
2506 #define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000
2507 #define SDR0_UARTX_UXDC_CLEARED 0x00100000
2508 #define SDR0_UARTX_UXDIV_MASK 0x000000FF
2509 #define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0)
2510 #define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1)
2512 #define SDR0_CPU440_EARV_MASK 0x30000000
2513 #define SDR0_CPU440_EARV_EBC 0x10000000
2514 #define SDR0_CPU440_EARV_PCI 0x20000000
2515 #define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28)
2516 #define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03)
2517 #define SDR0_CPU440_NTO1_MASK 0x00000002
2518 #define SDR0_CPU440_NTO1_NTOP 0x00000000
2519 #define SDR0_CPU440_NTO1_NTO1 0x00000002
2520 #define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1)
2521 #define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01)
2523 #define SDR0_XCR_PAE_MASK 0x80000000
2524 #define SDR0_XCR_PAE_DISABLE 0x00000000
2525 #define SDR0_XCR_PAE_ENABLE 0x80000000
2526 #define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31)
2527 #define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01)
2528 #define SDR0_XCR_PHCE_MASK 0x40000000
2529 #define SDR0_XCR_PHCE_DISABLE 0x00000000
2530 #define SDR0_XCR_PHCE_ENABLE 0x40000000
2531 #define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2532 #define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2533 #define SDR0_XCR_PISE_MASK 0x20000000
2534 #define SDR0_XCR_PISE_DISABLE 0x00000000
2535 #define SDR0_XCR_PISE_ENABLE 0x20000000
2536 #define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2537 #define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2538 #define SDR0_XCR_PCWE_MASK 0x10000000
2539 #define SDR0_XCR_PCWE_DISABLE 0x00000000
2540 #define SDR0_XCR_PCWE_ENABLE 0x10000000
2541 #define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28)
2542 #define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01)
2543 #define SDR0_XCR_PPIM_MASK 0x0F000000
2544 #define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24)
2545 #define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
2546 #define SDR0_XCR_PR64E_MASK 0x00800000
2547 #define SDR0_XCR_PR64E_DISABLE 0x00000000
2548 #define SDR0_XCR_PR64E_ENABLE 0x00800000
2549 #define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23)
2550 #define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01)
2551 #define SDR0_XCR_PXFS_MASK 0x00600000
2552 #define SDR0_XCR_PXFS_HIGH 0x00000000
2553 #define SDR0_XCR_PXFS_MED 0x00200000
2554 #define SDR0_XCR_PXFS_LOW 0x00400000
2555 #define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21)
2556 #define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03)
2557 #define SDR0_XCR_PDM_MASK 0x00000040
2558 #define SDR0_XCR_PDM_MULTIPOINT 0x00000000
2559 #define SDR0_XCR_PDM_P2P 0x00000040
2560 #define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19)
2561 #define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01)
2563 #define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000
2564 #define SDR0_PFC0_GEIE_MASK 0x00003E00
2565 #define SDR0_PFC0_GEIE_TRE 0x00003E00
2566 #define SDR0_PFC0_GEIE_NOTRE 0x00000000
2567 #define SDR0_PFC0_TRE_MASK 0x00000100
2568 #define SDR0_PFC0_TRE_DISABLE 0x00000000
2569 #define SDR0_PFC0_TRE_ENABLE 0x00000100
2570 #define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8)
2571 #define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01)
2573 #define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000
2574 #define SDR0_PFC1_EPS_MASK 0x01C00000
2575 #define SDR0_PFC1_EPS_GROUP0 0x00000000
2576 #define SDR0_PFC1_EPS_GROUP1 0x00400000
2577 #define SDR0_PFC1_EPS_GROUP2 0x00800000
2578 #define SDR0_PFC1_EPS_GROUP3 0x00C00000
2579 #define SDR0_PFC1_EPS_GROUP4 0x01000000
2580 #define SDR0_PFC1_EPS_GROUP5 0x01400000
2581 #define SDR0_PFC1_EPS_GROUP6 0x01800000
2582 #define SDR0_PFC1_EPS_GROUP7 0x01C00000
2583 #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
2584 #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
2585 #define SDR0_PFC1_RMII_MASK 0x00200000
2586 #define SDR0_PFC1_RMII_100MBIT 0x00000000
2587 #define SDR0_PFC1_RMII_10MBIT 0x00200000
2588 #define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21)
2589 #define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01)
2590 #define SDR0_PFC1_CTEMS_MASK 0x00100000
2591 #define SDR0_PFC1_CTEMS_EMS 0x00000000
2592 #define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000
2594 #define SDR0_MFR_TAH0_MASK 0x80000000
2595 #define SDR0_MFR_TAH0_ENABLE 0x00000000
2596 #define SDR0_MFR_TAH0_DISABLE 0x80000000
2597 #define SDR0_MFR_TAH1_MASK 0x40000000
2598 #define SDR0_MFR_TAH1_ENABLE 0x00000000
2599 #define SDR0_MFR_TAH1_DISABLE 0x40000000
2600 #define SDR0_MFR_PCM_MASK 0x20000000
2601 #define SDR0_MFR_PCM_PPC440GX 0x00000000
2602 #define SDR0_MFR_PCM_PPC440GP 0x20000000
2603 #define SDR0_MFR_ECS_MASK 0x10000000
2604 #define SDR0_MFR_ECS_INTERNAL 0x10000000
2606 #define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */
2607 #define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */
2608 #define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */
2609 #define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */
2610 #define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */
2611 #define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */
2612 #define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */
2613 #define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */
2614 #define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */
2615 #define SDR0_MFR_ERRATA3_EN0 0x00800000
2616 #define SDR0_MFR_ERRATA3_EN1 0x00400000
2617 #if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */
2618 #define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */
2619 #define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */
2620 #define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */
2621 #define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */
2622 #define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */
2625 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2626 #define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22)
2627 #define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07)
2628 #define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29)
2629 #define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07)
2632 #define SDR0_MFR_ECS_MASK 0x10000000
2633 #define SDR0_MFR_ECS_INTERNAL 0x10000000
2635 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
2636 #define SDR0_SRST0 0x200
2637 #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
2638 #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
2639 #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
2640 #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
2641 #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
2642 #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
2643 #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
2644 #define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */
2645 #define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */
2646 #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
2647 #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
2648 #define SDR0_SRST0_PCI 0x00100000 /* PCI */
2649 #define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */
2650 #define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */
2651 #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
2652 #define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */
2653 #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */
2654 #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */
2655 #define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */
2656 #define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */
2657 #define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */
2658 #define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */
2659 #define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */
2660 #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
2661 #define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */
2662 #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
2663 #define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */
2664 #define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */
2665 #define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */
2666 #define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */
2667 #define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */
2669 #define SDR0_SRST1 0x201
2670 #define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */
2671 #define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */
2672 #define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */
2673 #define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0
2674 #define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */
2675 #define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */
2676 #define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */
2677 #define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */
2678 #define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */
2679 #define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */
2680 #define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */
2681 #define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */
2682 #define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */
2683 #define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */
2684 #define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */
2685 #define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */
2686 #define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */
2687 #define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */
2688 #define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */
2689 #define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */
2691 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
2693 #define SDR0_SRST0 0x0200
2694 #define SDR0_SRST SDR0_SRST0 /* for compatability reasons */
2695 #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */
2696 #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */
2697 #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */
2698 #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */
2699 #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */
2700 #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */
2701 #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */
2702 #define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */
2703 #define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */
2704 #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */
2705 #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */
2706 #define SDR0_SRST0_PCI 0x00100000 /* PCI */
2707 #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */
2708 #define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */
2709 #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/
2710 #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/
2711 #define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/
2712 #define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/
2713 #define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/
2714 #define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/
2715 #define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */
2716 #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */
2717 #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */
2718 #define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */
2719 #define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */
2720 #define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */
2722 #define SDR0_SRST1 0x201
2723 #define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */
2724 #define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */
2725 #define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */
2726 #define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */
2727 #define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */
2728 #define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */
2729 #define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */
2730 #define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */
2731 #define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */
2732 #define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */
2733 #define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */
2734 #define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */
2735 #define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */
2736 #define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */
2737 #define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */
2738 #define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */
2739 #define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */
2740 #define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */
2741 #define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */
2742 #define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */
2743 #define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */
2744 #define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */
2745 #define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */
2746 #define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */
2747 #define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */
2748 #define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
2749 #define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */
2750 #define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */
2751 #define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */
2752 #define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */
2753 #define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */
2754 #define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */
2756 #define SDR0_PCI0 0x1c0 /* PCI Configuration Register */
2760 #define SDR0_SRST_BGO 0x80000000
2761 #define SDR0_SRST_PLB 0x40000000
2762 #define SDR0_SRST_EBC 0x20000000
2763 #define SDR0_SRST_OPB 0x10000000
2764 #define SDR0_SRST_UART0 0x08000000
2765 #define SDR0_SRST_UART1 0x04000000
2766 #define SDR0_SRST_IIC0 0x02000000
2767 #define SDR0_SRST_IIC1 0x01000000
2768 #define SDR0_SRST_GPIO 0x00800000
2769 #define SDR0_SRST_GPT 0x00400000
2770 #define SDR0_SRST_DMC 0x00200000
2771 #define SDR0_SRST_PCI 0x00100000
2772 #define SDR0_SRST_EMAC0 0x00080000
2773 #define SDR0_SRST_EMAC1 0x00040000
2774 #define SDR0_SRST_CPM 0x00020000
2775 #define SDR0_SRST_IMU 0x00010000
2776 #define SDR0_SRST_UIC01 0x00008000
2777 #define SDR0_SRST_UICB2 0x00004000
2778 #define SDR0_SRST_SRAM 0x00002000
2779 #define SDR0_SRST_EBM 0x00001000
2780 #define SDR0_SRST_BGI 0x00000800
2781 #define SDR0_SRST_DMA 0x00000400
2782 #define SDR0_SRST_DMAC 0x00000200
2783 #define SDR0_SRST_MAL 0x00000100
2784 #define SDR0_SRST_ZMII 0x00000080
2785 #define SDR0_SRST_GPTR 0x00000040
2786 #define SDR0_SRST_PPM 0x00000020
2787 #define SDR0_SRST_EMAC2 0x00000010
2788 #define SDR0_SRST_EMAC3 0x00000008
2789 #define SDR0_SRST_RGMII 0x00000001
2793 /*-----------------------------------------------------------------------------+
2795 +-----------------------------------------------------------------------------*/
2796 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
2797 #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
2798 #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
2799 #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
2800 #define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
2801 #define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */
2802 #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
2803 #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
2804 #elif !defined (CONFIG_440GX) && \
2805 !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
2806 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
2807 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
2808 #define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */
2809 #define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */
2810 #define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */
2811 #define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */
2812 #define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */
2813 #define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
2814 #define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
2815 #define PLLSYS0_RW_MASK 0x00000060 /* ROM width */
2816 #define PLLSYS0_RL_MASK 0x00000010 /* ROM location */
2817 #define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */
2818 #define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */
2819 #define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
2821 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
2822 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
2823 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
2824 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
2825 #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */
2826 #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */
2827 #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */
2828 #define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */
2829 #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */
2830 #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */
2831 #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */
2832 #define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */
2833 #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */
2834 #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */
2836 #define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */
2837 #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
2838 #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */
2839 #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */
2840 #define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */
2841 #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
2843 #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
2844 #define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
2845 #define PRADV_MASK 0x07000000 /* Primary Divisor A */
2846 #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
2847 #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
2849 #define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */
2850 #define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */
2851 #define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */
2852 #define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */
2854 /* Strap 1 Register */
2855 #define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */
2856 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
2857 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
2858 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
2859 #define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
2860 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
2861 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
2862 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
2863 #define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */
2864 #define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */
2865 #define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */
2866 #define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */
2867 #define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */
2868 #define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */
2869 #define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */
2870 #define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */
2871 #define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */
2872 #define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */
2873 #endif /* CONFIG_440GX */
2875 #if defined (CONFIG_440EPX) || defined (CONFIG_440GRX)
2876 /*--------------------------------------*/
2877 #define CPR0_PLLC 0x40
2878 #define CPR0_PLLC_RST_MASK 0x80000000
2879 #define CPR0_PLLC_RST_PLLLOCKED 0x00000000
2880 #define CPR0_PLLC_RST_PLLRESET 0x80000000
2881 #define CPR0_PLLC_ENG_MASK 0x40000000
2882 #define CPR0_PLLC_ENG_DISABLE 0x00000000
2883 #define CPR0_PLLC_ENG_ENABLE 0x40000000
2884 #define CPR0_PLLC_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<30)
2885 #define CPR0_PLLC_ENG_DECODE(n) ((((unsigned long)(n))>>30)&0x01)
2886 #define CPR0_PLLC_SRC_MASK 0x20000000
2887 #define CPR0_PLLC_SRC_PLLOUTA 0x00000000
2888 #define CPR0_PLLC_SRC_PLLOUTB 0x20000000
2889 #define CPR0_PLLC_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<29)
2890 #define CPR0_PLLC_SRC_DECODE(n) ((((unsigned long)(n))>>29)&0x01)
2891 #define CPR0_PLLC_SEL_MASK 0x07000000
2892 #define CPR0_PLLC_SEL_PLL 0x00000000
2893 #define CPR0_PLLC_SEL_CPU 0x01000000
2894 #define CPR0_PLLC_SEL_PER 0x05000000
2895 #define CPR0_PLLC_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2896 #define CPR0_PLLC_SEL_DECODE(n) ((((unsigned long)(n))>>24)&0x07)
2897 #define CPR0_PLLC_TUNE_MASK 0x000003FF
2898 #define CPR0_PLLC_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0)
2899 #define CPR0_PLLC_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF)
2900 /*--------------------------------------*/
2901 #define CPR0_PLLD 0x60
2902 #define CPR0_PLLD_FBDV_MASK 0x1F000000
2903 #define CPR0_PLLD_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24)
2904 #define CPR0_PLLD_FBDV_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x1F)+1)
2905 #define CPR0_PLLD_FWDVA_MASK 0x000F0000
2906 #define CPR0_PLLD_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<16)
2907 #define CPR0_PLLD_FWDVA_DECODE(n) ((((((unsigned long)(n))>>16)-1)&0x0F)+1)
2908 #define CPR0_PLLD_FWDVB_MASK 0x00000700
2909 #define CPR0_PLLD_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<8)
2910 #define CPR0_PLLD_FWDVB_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x07)+1)
2911 #define CPR0_PLLD_LFBDV_MASK 0x0000003F
2912 #define CPR0_PLLD_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<0)
2913 #define CPR0_PLLD_LFBDV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x3F)+1)
2914 /*--------------------------------------*/
2915 #define CPR0_PRIMAD 0x80
2916 #define CPR0_PRIMAD_PRADV0_MASK 0x07000000
2917 #define CPR0_PRIMAD_PRADV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2918 #define CPR0_PRIMAD_PRADV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
2919 /*--------------------------------------*/
2920 #define CPR0_PRIMBD 0xA0
2921 #define CPR0_PRIMBD_PRBDV0_MASK 0x07000000
2922 #define CPR0_PRIMBD_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2923 #define CPR0_PRIMBD_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
2924 /*--------------------------------------*/
2926 #define CPR0_CPM0_ER 0xB0 /* CPM Enable Register */
2927 #define CPR0_CPM0_FR 0xB1 /* CPM Force Register */
2928 #define CPR0_CPM0_SR 0xB2 /* CPM Status Register */
2929 #define CPR0_CPM0_IIC0 0x80000000 /* Inter-Intergrated Circuit0 */
2930 #define CPR0_CPM0_IIC1 0x40000000 /* Inter-Intergrated Circuit1 */
2931 #define CPR0_CPM0_PCI 0x20000000 /* Peripheral Component Interconnect */
2932 #define CPR0_CPM0_USB1H 0x08000000 /* USB1.1 Host */
2933 #define CPR0_CPM0_FPU 0x04000000 /* PPC440 FPU */
2934 #define CPR0_CPM0_CPU 0x02000000 /* PPC440x5 Processor Core */
2935 #define CPR0_CPM0_DMA 0x01000000 /* Direct Memory Access Controller */
2936 #define CPR0_CPM0_BGO 0x00800000 /* PLB to OPB Bridge */
2937 #define CPR0_CPM0_BGI 0x00400000 /* OPB to PLB Bridge */
2938 #define CPR0_CPM0_EBC 0x00200000 /* External Bus Controller */
2939 #define CPR0_CPM0_NDFC 0x00100000 /* Nand Flash Controller */
2940 #define CPR0_CPM0_MADMAL 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
2941 #define CPR0_CPM0_DMC 0x00080000 /* DDR SDRAM Controller or MADMAL ??? */
2942 #define CPR0_CPM0_PLB4 0x00040000 /* PLB4 Arbiter */
2943 #define CPR0_CPM0_PLB4x3x 0x00020000 /* PLB4 to PLB3 */
2944 #define CPR0_CPM0_PLB3x4x 0x00010000 /* PLB3 to PLB4 */
2945 #define CPR0_CPM0_PLB3 0x00008000 /* PLB3 Arbiter */
2946 #define CPR0_CPM0_PPM 0x00002000 /* PLB Performance Monitor */
2947 #define CPR0_CPM0_UIC1 0x00001000 /* Universal Interrupt Controller 1 */
2948 #define CPR0_CPM0_GPIO 0x00000800 /* General Purpose IO */
2949 #define CPR0_CPM0_GPT 0x00000400 /* General Purpose Timer */
2950 #define CPR0_CPM0_UART0 0x00000200 /* Universal Asynchronous Rcver/Xmitter 0 */
2951 #define CPR0_CPM0_UART1 0x00000100 /* Universal Asynchronous Rcver/Xmitter 1 */
2952 #define CPR0_CPM0_UIC0 0x00000080 /* Universal Interrupt Controller 0 */
2953 #define CPR0_CPM0_TMRCLK 0x00000040 /* CPU Timer */
2954 #define CPR0_CPM0_EMC0 0x00000020 /* Ethernet 0 */
2955 #define CPR0_CPM0_EMC1 0x00000010 /* Ethernet 1 */
2956 #define CPR0_CPM0_UART2 0x00000008 /* Universal Asynchronous Rcver/Xmitter 2 */
2957 #define CPR0_CPM0_UART3 0x00000004 /* Universal Asynchronous Rcver/Xmitter 3 */
2958 #define CPR0_CPM0_USB2D 0x00000002 /* USB2.0 Device */
2959 #define CPR0_CPM0_USB2H 0x00000001 /* USB2.0 Host */
2961 /*--------------------------------------*/
2962 #define CPR0_OPBD 0xC0
2963 #define CPR0_OPBD_OPBDV0_MASK 0x03000000
2964 #define CPR0_OPBD_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
2965 #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
2966 /*--------------------------------------*/
2967 #define CPR0_PERD 0xE0
2968 #define CPR0_PERD_PERDV0_MASK 0x07000000
2969 #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<24)
2970 #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x07)+1)
2971 /*--------------------------------------*/
2972 #define CPR0_MALD 0x100
2973 #define CPR0_MALD_MALDV0_MASK 0x03000000
2974 #define CPR0_MALD_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
2975 #define CPR0_MALD_MALDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
2976 /*--------------------------------------*/
2977 #define CPR0_SPCID 0x120
2978 #define CPR0_SPCID_SPCIDV0_MASK 0x03000000
2979 #define CPR0_SPCID_SPCIDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24)
2980 #define CPR0_SPCID_SPCIDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1)
2981 /*--------------------------------------*/
2982 #define CPR0_ICFG 0x140
2983 #define CPR0_ICFG_RLI_MASK 0x80000000
2984 #define CPR0_ICFG_RLI_RESETCPR 0x00000000
2985 #define CPR0_ICFG_RLI_PRESERVECPR 0x80000000
2986 #define CPR0_ICFG_ICS_MASK 0x00000007
2987 #endif /* defined (CONFIG_440EPX) || defined (CONFIG_440GRX) */
2989 /*-----------------------------------------------------------------------------
2990 | IIC Register Offsets
2991 '----------------------------------------------------------------------------*/
2992 #define IICMDBUF 0x00
2993 #define IICSDBUF 0x02
2994 #define IICLMADR 0x04
2995 #define IICHMADR 0x05
2996 #define IICCNTL 0x06
2997 #define IICMDCNTL 0x07
2999 #define IICEXTSTS 0x09
3000 #define IICLSADR 0x0A
3001 #define IICHSADR 0x0B
3002 #define IICCLKDIV 0x0C
3003 #define IICINTRMSK 0x0D
3004 #define IICXFRCNT 0x0E
3005 #define IICXTCNTLSS 0x0F
3006 #define IICDIRECTCNTL 0x10
3008 /*-----------------------------------------------------------------------------
3009 | UART Register Offsets
3010 '----------------------------------------------------------------------------*/
3011 #define DATA_REG 0x00
3014 #define INT_ENABLE 0x01
3015 #define FIFO_CONTROL 0x02
3016 #define LINE_CONTROL 0x03
3017 #define MODEM_CONTROL 0x04
3018 #define LINE_STATUS 0x05
3019 #define MODEM_STATUS 0x06
3020 #define SCRATCH 0x07
3022 /*-----------------------------------------------------------------------------
3023 | PCI Internal Registers et. al. (accessed via plb)
3024 +----------------------------------------------------------------------------*/
3025 #define PCIX0_CFGADR (CFG_PCI_BASE + 0x0ec00000)
3026 #define PCIX0_CFGDATA (CFG_PCI_BASE + 0x0ec00004)
3027 #define PCIX0_CFGBASE (CFG_PCI_BASE + 0x0ec80000)
3028 #define PCIX0_IOBASE (CFG_PCI_BASE + 0x08000000)
3030 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
3031 defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3033 /* PCI Local Configuration Registers
3034 --------------------------------- */
3035 #define PCI_MMIO_LCR_BASE (CFG_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */
3037 /* PCI Master Local Configuration Registers */
3038 #define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */
3039 #define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */
3040 #define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */
3041 #define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */
3042 #define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */
3043 #define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */
3044 #define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */
3045 #define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */
3046 #define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */
3047 #define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */
3048 #define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */
3049 #define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */
3051 /* PCI Target Local Configuration Registers */
3052 #define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */
3053 #define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */
3054 #define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */
3055 #define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */
3059 #define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID )
3060 #define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID )
3061 #define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND )
3062 #define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS )
3063 #define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID )
3064 #define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE)
3065 #define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE )
3066 #define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER )
3067 #define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE )
3068 #define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST )
3069 #define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 )
3070 #define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 )
3071 #define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 )
3072 #define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 )
3073 #define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 )
3074 #define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 )
3075 #define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS )
3076 #define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
3077 #define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID )
3078 #define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS )
3079 #define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST )
3080 #define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 )
3081 #define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 )
3082 #define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 )
3083 #define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE )
3084 #define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN )
3085 #define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT )
3086 #define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT )
3088 #define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040)
3089 #define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044)
3091 #define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068)
3092 #define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c)
3093 #define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070)
3094 #define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074)
3095 #define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078)
3096 #define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c)
3097 #define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080)
3098 #define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084)
3099 #define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088)
3100 #define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c)
3101 #define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090)
3103 #define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098)
3104 #define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c)
3105 #define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0)
3106 #define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4)
3107 #define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8)
3108 #define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac)
3109 #define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0)
3110 #define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4)
3111 #define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8)
3113 #define PCIX0_STS (PCIX0_CFGBASE + 0x00e0)
3115 #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */
3117 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
3120 #define USB2D0_BASE CFG_USB2D0_BASE
3122 #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000)
3124 #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */
3125 #define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */
3126 #define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */
3127 #define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */
3128 #define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */
3129 #define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */
3130 #define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */
3131 #define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */
3132 #define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */
3133 #define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */
3134 #define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */
3135 #define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */
3136 #define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */
3137 #define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */
3138 #define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */
3139 #define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */
3140 #define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */
3141 #define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */
3144 /******************************************************************************
3145 * GPIO macro register defines
3146 ******************************************************************************/
3147 #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \
3148 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
3149 #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700)
3151 #define GPIO0_OR (GPIO0_BASE+0x0)
3152 #define GPIO0_TCR (GPIO0_BASE+0x4)
3153 #define GPIO0_ODR (GPIO0_BASE+0x18)
3154 #define GPIO0_IR (GPIO0_BASE+0x1C)
3155 #endif /* CONFIG_440GP */
3157 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
3158 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
3159 defined(CONFIG_460EX) || defined(CONFIG_460GT)
3160 #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000B00)
3161 #define GPIO1_BASE (CFG_PERIPHERAL_BASE+0x00000C00)
3163 #define GPIO0_OR (GPIO0_BASE+0x0)
3164 #define GPIO0_TCR (GPIO0_BASE+0x4)
3165 #define GPIO0_OSRL (GPIO0_BASE+0x8)
3166 #define GPIO0_OSRH (GPIO0_BASE+0xC)
3167 #define GPIO0_TSRL (GPIO0_BASE+0x10)
3168 #define GPIO0_TSRH (GPIO0_BASE+0x14)
3169 #define GPIO0_ODR (GPIO0_BASE+0x18)
3170 #define GPIO0_IR (GPIO0_BASE+0x1C)
3171 #define GPIO0_RR1 (GPIO0_BASE+0x20)
3172 #define GPIO0_RR2 (GPIO0_BASE+0x24)
3173 #define GPIO0_RR3 (GPIO0_BASE+0x28)
3174 #define GPIO0_ISR1L (GPIO0_BASE+0x30)
3175 #define GPIO0_ISR1H (GPIO0_BASE+0x34)
3176 #define GPIO0_ISR2L (GPIO0_BASE+0x38)
3177 #define GPIO0_ISR2H (GPIO0_BASE+0x3C)
3178 #define GPIO0_ISR3L (GPIO0_BASE+0x40)
3179 #define GPIO0_ISR3H (GPIO0_BASE+0x44)
3181 #define GPIO1_OR (GPIO1_BASE+0x0)
3182 #define GPIO1_TCR (GPIO1_BASE+0x4)
3183 #define GPIO1_OSRL (GPIO1_BASE+0x8)
3184 #define GPIO1_OSRH (GPIO1_BASE+0xC)
3185 #define GPIO1_TSRL (GPIO1_BASE+0x10)
3186 #define GPIO1_TSRH (GPIO1_BASE+0x14)
3187 #define GPIO1_ODR (GPIO1_BASE+0x18)
3188 #define GPIO1_IR (GPIO1_BASE+0x1C)
3189 #define GPIO1_RR1 (GPIO1_BASE+0x20)
3190 #define GPIO1_RR2 (GPIO1_BASE+0x24)
3191 #define GPIO1_RR3 (GPIO1_BASE+0x28)
3192 #define GPIO1_ISR1L (GPIO1_BASE+0x30)
3193 #define GPIO1_ISR1H (GPIO1_BASE+0x34)
3194 #define GPIO1_ISR2L (GPIO1_BASE+0x38)
3195 #define GPIO1_ISR2H (GPIO1_BASE+0x3C)
3196 #define GPIO1_ISR3L (GPIO1_BASE+0x40)
3197 #define GPIO1_ISR3H (GPIO1_BASE+0x44)
3200 #ifndef __ASSEMBLY__
3202 static inline u32 get_mcsr(void)
3206 asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
3210 static inline void set_mcsr(u32 val)
3212 asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
3215 #endif /* _ASMLANGUAGE */
3217 #endif /* __PPC440_H__ */
projects / platform / kernel / u-boot.git / blob