1 /*----------------------------------------------------------------------------+
2 | This source code is dual-licensed. You may use it under the terms of the
3 | GNU General Public License version 2, or under the license below.
5 | This source code has been made available to you by IBM on an AS-IS
6 | basis. Anyone receiving this source is licensed under IBM
7 | copyrights to use it in any way he or she deems fit, including
8 | copying it, modifying it, compiling it, and redistributing it either
9 | with or without modifications. No license under IBM patents or
10 | patent applications is to be implied by the copyright license.
12 | Any user of this software should understand that IBM cannot provide
13 | technical support for this software and will not be responsible for
14 | any consequences resulting from the use of this software.
16 | Any person who transfers this source code or any derivative work
17 | must include the IBM copyright notice, this paragraph, and the
18 | preceding two paragraphs in the transferred software.
20 | COPYRIGHT I B M CORPORATION 1999
21 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22 +----------------------------------------------------------------------------*/
27 /* Define bits and masks for real-mode storage attribute control registers */
28 #define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
29 #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
32 #define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
34 #define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */
37 /******************************************************************************
38 * Special for PPC405GP
39 ******************************************************************************/
41 /******************************************************************************
43 ******************************************************************************/
44 #define DMA_DCR_BASE 0x100
45 #define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */
46 #define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */
47 #define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */
48 #define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */
49 #define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */
50 #define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */
51 #define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */
52 #define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */
53 #define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */
54 #define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */
55 #define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */
56 #define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */
57 #define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */
58 #define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */
59 #define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */
60 #define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */
61 #define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */
62 #define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */
63 #define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */
64 #define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */
65 #define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */
66 #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
67 #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
70 /******************************************************************************
71 * Decompression Controller
72 ******************************************************************************/
73 #define DECOMP_DCR_BASE 0x14
74 #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */
75 #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */
76 /* values for kiar register - indirect addressing of these regs */
77 #define kitor0 0x00 /* index table origin register 0 */
78 #define kitor1 0x01 /* index table origin register 1 */
79 #define kitor2 0x02 /* index table origin register 2 */
80 #define kitor3 0x03 /* index table origin register 3 */
81 #define kaddr0 0x04 /* address decode definition regsiter 0 */
82 #define kaddr1 0x05 /* address decode definition regsiter 1 */
83 #define kconf 0x40 /* decompression core config register */
84 #define kid 0x41 /* decompression core ID register */
85 #define kver 0x42 /* decompression core version # reg */
86 #define kpear 0x50 /* bus error addr reg (PLB addr) */
87 #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/
88 #define kesr0 0x52 /* bus error status reg 0 (R/clear) */
89 #define kesr0s 0x53 /* bus error status reg 0 (set) */
90 /* There are 0x400 of the following registers, from krom0 to krom3ff*/
91 /* Only the first one is given here. */
92 #define krom0 0x400 /* SRAM/ROM read/write */
95 /******************************************************************************
97 ******************************************************************************/
99 #define POWERMAN_DCR_BASE 0xb0
101 #define POWERMAN_DCR_BASE 0xb8
103 #define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */
104 #define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */
105 #define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */
107 /******************************************************************************
108 * Extrnal Bus Controller
109 ******************************************************************************/
110 /* values for ebccfga register - indirect addressing of these regs */
111 #define pb0cr 0x00 /* periph bank 0 config reg */
112 #define pb1cr 0x01 /* periph bank 1 config reg */
113 #define pb2cr 0x02 /* periph bank 2 config reg */
114 #define pb3cr 0x03 /* periph bank 3 config reg */
115 #define pb4cr 0x04 /* periph bank 4 config reg */
117 #define pb5cr 0x05 /* periph bank 5 config reg */
118 #define pb6cr 0x06 /* periph bank 6 config reg */
119 #define pb7cr 0x07 /* periph bank 7 config reg */
121 #define pb0ap 0x10 /* periph bank 0 access parameters */
122 #define pb1ap 0x11 /* periph bank 1 access parameters */
123 #define pb2ap 0x12 /* periph bank 2 access parameters */
124 #define pb3ap 0x13 /* periph bank 3 access parameters */
125 #define pb4ap 0x14 /* periph bank 4 access parameters */
127 #define pb5ap 0x15 /* periph bank 5 access parameters */
128 #define pb6ap 0x16 /* periph bank 6 access parameters */
129 #define pb7ap 0x17 /* periph bank 7 access parameters */
131 #define pbear 0x20 /* periph bus error addr reg */
132 #define pbesr0 0x21 /* periph bus error status reg 0 */
133 #define pbesr1 0x22 /* periph bus error status reg 1 */
134 #define epcr 0x23 /* external periph control reg */
135 #define EBC0_CFG 0x23 /* external bus configuration reg */
138 /******************************************************************************
140 ******************************************************************************/
141 #define CNTRL_DCR_BASE 0x0f0
142 #define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */
143 #define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */
144 #define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */
145 #define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */
146 #define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */
147 #define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */
149 #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
150 #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
151 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
152 #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/
153 #define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
154 #define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
155 #define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
156 #define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
157 #define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
158 #define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
160 /* Bit definitions */
161 #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */
162 #define PLLMR0_CPU_DIV_BYPASS 0x00000000
163 #define PLLMR0_CPU_DIV_2 0x00100000
164 #define PLLMR0_CPU_DIV_3 0x00200000
165 #define PLLMR0_CPU_DIV_4 0x00300000
167 #define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */
168 #define PLLMR0_CPU_PLB_DIV_1 0x00000000
169 #define PLLMR0_CPU_PLB_DIV_2 0x00010000
170 #define PLLMR0_CPU_PLB_DIV_3 0x00020000
171 #define PLLMR0_CPU_PLB_DIV_4 0x00030000
173 #define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */
174 #define PLLMR0_OPB_PLB_DIV_1 0x00000000
175 #define PLLMR0_OPB_PLB_DIV_2 0x00001000
176 #define PLLMR0_OPB_PLB_DIV_3 0x00002000
177 #define PLLMR0_OPB_PLB_DIV_4 0x00003000
179 #define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */
180 #define PLLMR0_EXB_PLB_DIV_2 0x00000000
181 #define PLLMR0_EXB_PLB_DIV_3 0x00000100
182 #define PLLMR0_EXB_PLB_DIV_4 0x00000200
183 #define PLLMR0_EXB_PLB_DIV_5 0x00000300
185 #define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */
186 #define PLLMR0_MAL_PLB_DIV_1 0x00000000
187 #define PLLMR0_MAL_PLB_DIV_2 0x00000010
188 #define PLLMR0_MAL_PLB_DIV_3 0x00000020
189 #define PLLMR0_MAL_PLB_DIV_4 0x00000030
191 #define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */
192 #define PLLMR0_PCI_PLB_DIV_1 0x00000000
193 #define PLLMR0_PCI_PLB_DIV_2 0x00000001
194 #define PLLMR0_PCI_PLB_DIV_3 0x00000002
195 #define PLLMR0_PCI_PLB_DIV_4 0x00000003
197 #define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */
198 #define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */
199 #define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */
200 #define PLLMR1_FBMUL_DIV_16 0x00000000
201 #define PLLMR1_FBMUL_DIV_1 0x00100000
202 #define PLLMR1_FBMUL_DIV_2 0x00200000
203 #define PLLMR1_FBMUL_DIV_3 0x00300000
204 #define PLLMR1_FBMUL_DIV_4 0x00400000
205 #define PLLMR1_FBMUL_DIV_5 0x00500000
206 #define PLLMR1_FBMUL_DIV_6 0x00600000
207 #define PLLMR1_FBMUL_DIV_7 0x00700000
208 #define PLLMR1_FBMUL_DIV_8 0x00800000
209 #define PLLMR1_FBMUL_DIV_9 0x00900000
210 #define PLLMR1_FBMUL_DIV_10 0x00A00000
211 #define PLLMR1_FBMUL_DIV_11 0x00B00000
212 #define PLLMR1_FBMUL_DIV_12 0x00C00000
213 #define PLLMR1_FBMUL_DIV_13 0x00D00000
214 #define PLLMR1_FBMUL_DIV_14 0x00E00000
215 #define PLLMR1_FBMUL_DIV_15 0x00F00000
217 #define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */
218 #define PLLMR1_FWDVA_DIV_8 0x00000000
219 #define PLLMR1_FWDVA_DIV_7 0x00010000
220 #define PLLMR1_FWDVA_DIV_6 0x00020000
221 #define PLLMR1_FWDVA_DIV_5 0x00030000
222 #define PLLMR1_FWDVA_DIV_4 0x00040000
223 #define PLLMR1_FWDVA_DIV_3 0x00050000
224 #define PLLMR1_FWDVA_DIV_2 0x00060000
225 #define PLLMR1_FWDVA_DIV_1 0x00070000
226 #define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */
227 #define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */
229 /* Defines for CPC0_EPRCSR register */
230 #define CPC0_EPRCSR_E0NFE 0x80000000
231 #define CPC0_EPRCSR_E1NFE 0x40000000
232 #define CPC0_EPRCSR_E1RPP 0x00000080
233 #define CPC0_EPRCSR_E0RPP 0x00000040
234 #define CPC0_EPRCSR_E1ERP 0x00000020
235 #define CPC0_EPRCSR_E0ERP 0x00000010
236 #define CPC0_EPRCSR_E1PCI 0x00000002
237 #define CPC0_EPRCSR_E0PCI 0x00000001
239 /* Defines for CPC0_PCI Register */
240 #define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */
241 #define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */
242 #define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/
244 /* Defines for CPC0_BOOR Register */
245 #define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */
247 /* Defines for CPC0_PLLMR1 Register fields */
248 #define PLL_ACTIVE 0x80000000
249 #define CPC0_PLLMR1_SSCS 0x80000000
250 #define PLL_RESET 0x40000000
251 #define CPC0_PLLMR1_PLLR 0x40000000
252 /* Feedback multiplier */
253 #define PLL_FBKDIV 0x00F00000
254 #define CPC0_PLLMR1_FBDV 0x00F00000
255 #define PLL_FBKDIV_16 0x00000000
256 #define PLL_FBKDIV_1 0x00100000
257 #define PLL_FBKDIV_2 0x00200000
258 #define PLL_FBKDIV_3 0x00300000
259 #define PLL_FBKDIV_4 0x00400000
260 #define PLL_FBKDIV_5 0x00500000
261 #define PLL_FBKDIV_6 0x00600000
262 #define PLL_FBKDIV_7 0x00700000
263 #define PLL_FBKDIV_8 0x00800000
264 #define PLL_FBKDIV_9 0x00900000
265 #define PLL_FBKDIV_10 0x00A00000
266 #define PLL_FBKDIV_11 0x00B00000
267 #define PLL_FBKDIV_12 0x00C00000
268 #define PLL_FBKDIV_13 0x00D00000
269 #define PLL_FBKDIV_14 0x00E00000
270 #define PLL_FBKDIV_15 0x00F00000
271 /* Forward A divisor */
272 #define PLL_FWDDIVA 0x00070000
273 #define CPC0_PLLMR1_FWDVA 0x00070000
274 #define PLL_FWDDIVA_8 0x00000000
275 #define PLL_FWDDIVA_7 0x00010000
276 #define PLL_FWDDIVA_6 0x00020000
277 #define PLL_FWDDIVA_5 0x00030000
278 #define PLL_FWDDIVA_4 0x00040000
279 #define PLL_FWDDIVA_3 0x00050000
280 #define PLL_FWDDIVA_2 0x00060000
281 #define PLL_FWDDIVA_1 0x00070000
282 /* Forward B divisor */
283 #define PLL_FWDDIVB 0x00007000
284 #define CPC0_PLLMR1_FWDVB 0x00007000
285 #define PLL_FWDDIVB_8 0x00000000
286 #define PLL_FWDDIVB_7 0x00001000
287 #define PLL_FWDDIVB_6 0x00002000
288 #define PLL_FWDDIVB_5 0x00003000
289 #define PLL_FWDDIVB_4 0x00004000
290 #define PLL_FWDDIVB_3 0x00005000
291 #define PLL_FWDDIVB_2 0x00006000
292 #define PLL_FWDDIVB_1 0x00007000
294 #define PLL_TUNE_MASK 0x000003FF
295 #define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
296 #define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
297 #define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
298 #define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
299 #define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
300 #define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
301 #define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
303 /* Defines for CPC0_PLLMR0 Register fields */
305 #define PLL_CPUDIV 0x00300000
306 #define CPC0_PLLMR0_CCDV 0x00300000
307 #define PLL_CPUDIV_1 0x00000000
308 #define PLL_CPUDIV_2 0x00100000
309 #define PLL_CPUDIV_3 0x00200000
310 #define PLL_CPUDIV_4 0x00300000
312 #define PLL_PLBDIV 0x00030000
313 #define CPC0_PLLMR0_CBDV 0x00030000
314 #define PLL_PLBDIV_1 0x00000000
315 #define PLL_PLBDIV_2 0x00010000
316 #define PLL_PLBDIV_3 0x00020000
317 #define PLL_PLBDIV_4 0x00030000
319 #define PLL_OPBDIV 0x00003000
320 #define CPC0_PLLMR0_OPDV 0x00003000
321 #define PLL_OPBDIV_1 0x00000000
322 #define PLL_OPBDIV_2 0x00001000
323 #define PLL_OPBDIV_3 0x00002000
324 #define PLL_OPBDIV_4 0x00003000
326 #define PLL_EXTBUSDIV 0x00000300
327 #define CPC0_PLLMR0_EPDV 0x00000300
328 #define PLL_EXTBUSDIV_2 0x00000000
329 #define PLL_EXTBUSDIV_3 0x00000100
330 #define PLL_EXTBUSDIV_4 0x00000200
331 #define PLL_EXTBUSDIV_5 0x00000300
333 #define PLL_MALDIV 0x00000030
334 #define CPC0_PLLMR0_MPDV 0x00000030
335 #define PLL_MALDIV_1 0x00000000
336 #define PLL_MALDIV_2 0x00000010
337 #define PLL_MALDIV_3 0x00000020
338 #define PLL_MALDIV_4 0x00000030
340 #define PLL_PCIDIV 0x00000003
341 #define CPC0_PLLMR0_PPFD 0x00000003
342 #define PLL_PCIDIV_1 0x00000000
343 #define PLL_PCIDIV_2 0x00000001
344 #define PLL_PCIDIV_3 0x00000002
345 #define PLL_PCIDIV_4 0x00000003
348 *-------------------------------------------------------------------------------
349 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
350 * assuming a 33.3MHz input clock to the 405EP.
351 *-------------------------------------------------------------------------------
353 #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
354 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
355 PLL_MALDIV_1 | PLL_PCIDIV_4)
356 #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \
357 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
358 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
360 #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
361 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
362 PLL_MALDIV_1 | PLL_PCIDIV_4)
363 #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \
364 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
365 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
366 #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
367 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
368 PLL_MALDIV_1 | PLL_PCIDIV_4)
369 #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
370 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
371 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
372 #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
373 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
374 PLL_MALDIV_1 | PLL_PCIDIV_4)
375 #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \
376 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
377 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
378 #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \
379 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
380 PLL_MALDIV_1 | PLL_PCIDIV_2)
381 #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \
382 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
383 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
384 #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
385 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
386 PLL_MALDIV_1 | PLL_PCIDIV_3)
387 #define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \
388 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
389 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
390 #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
391 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
392 PLL_MALDIV_1 | PLL_PCIDIV_1)
393 #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \
394 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
395 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
398 * PLL Voltage Controlled Oscillator (VCO) definitions
399 * Maximum and minimum values (in MHz) for correct PLL operation.
403 #elif defined(CONFIG_405EZ)
404 #define sdrnand0 0x4000
405 #define sdrultra0 0x4040
406 #define sdrultra1 0x4050
407 #define sdricintstat 0x4510
409 #define SDR_NAND0_NDEN 0x80000000
410 #define SDR_NAND0_NDBTEN 0x40000000
411 #define SDR_NAND0_NDBADR_MASK 0x30000000
412 #define SDR_NAND0_NDBPG_MASK 0x0f000000
413 #define SDR_NAND0_NDAREN 0x00800000
414 #define SDR_NAND0_NDRBEN 0x00400000
416 #define SDR_ULTRA0_NDGPIOBP 0x80000000
417 #define SDR_ULTRA0_CSN_MASK 0x78000000
418 #define SDR_ULTRA0_CSNSEL0 0x40000000
419 #define SDR_ULTRA0_CSNSEL1 0x20000000
420 #define SDR_ULTRA0_CSNSEL2 0x10000000
421 #define SDR_ULTRA0_CSNSEL3 0x08000000
422 #define SDR_ULTRA0_EBCRDYEN 0x04000000
423 #define SDR_ULTRA0_SPISSINEN 0x02000000
424 #define SDR_ULTRA0_NFSRSTEN 0x01000000
426 #define SDR_ULTRA1_LEDNENABLE 0x40000000
428 #define SDR_ICRX_STAT 0x80000000
429 #define SDR_ICTX0_STAT 0x40000000
430 #define SDR_ICTX1_STAT 0x20000000
432 #define SDR_PINSTP 0x40
434 /******************************************************************************
436 ******************************************************************************/
438 #define cprclkupd 0x020 /* CPR_CLKUPD */
439 #define cprpllc 0x040 /* CPR_PLLC */
440 #define cprplld 0x060 /* CPR_PLLD */
441 #define cprprimad 0x080 /* CPR_PRIMAD */
442 #define cprperd0 0x0e0 /* CPR_PERD0 */
443 #define cprperd1 0x0e1 /* CPR_PERD1 */
444 #define cprperc0 0x180 /* CPR_PERC0 */
445 #define cprmisc0 0x181 /* CPR_MISC0 */
446 #define cprmisc1 0x182 /* CPR_MISC1 */
448 #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */
449 #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */
450 #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */
452 #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */
454 #define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */
455 #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */
456 #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */
458 #define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */
459 #define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */
460 #define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */
461 #define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */
463 #define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */
464 #define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */
465 #define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */
466 #define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */
468 #else /* #ifdef CONFIG_405EP */
469 /******************************************************************************
471 ******************************************************************************/
472 #define CNTRL_DCR_BASE 0x0b0
473 #define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */
474 #define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */
475 #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */
476 #define reset (CNTRL_DCR_BASE+0x3) /* reset register */
477 #define strap (CNTRL_DCR_BASE+0x4) /* strap register */
479 #define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */
480 #define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */
481 #define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */
483 /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */
484 #define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */
485 #define CPC0_ECR (0xaa) /* edge conditioner register */
487 #define ecr (0xaa) /* edge conditioner register (405gpr) */
489 /* Bit definitions */
490 #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */
491 #define PLLMR_FWD_DIV_BYPASS 0xE0000000
492 #define PLLMR_FWD_DIV_3 0xA0000000
493 #define PLLMR_FWD_DIV_4 0x80000000
494 #define PLLMR_FWD_DIV_6 0x40000000
496 #define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */
497 #define PLLMR_FB_DIV_1 0x02000000
498 #define PLLMR_FB_DIV_2 0x04000000
499 #define PLLMR_FB_DIV_3 0x06000000
500 #define PLLMR_FB_DIV_4 0x08000000
502 #define PLLMR_TUNING_MASK 0x01F80000
504 #define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */
505 #define PLLMR_CPU_PLB_DIV_1 0x00000000
506 #define PLLMR_CPU_PLB_DIV_2 0x00020000
507 #define PLLMR_CPU_PLB_DIV_3 0x00040000
508 #define PLLMR_CPU_PLB_DIV_4 0x00060000
510 #define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */
511 #define PLLMR_OPB_PLB_DIV_1 0x00000000
512 #define PLLMR_OPB_PLB_DIV_2 0x00008000
513 #define PLLMR_OPB_PLB_DIV_3 0x00010000
514 #define PLLMR_OPB_PLB_DIV_4 0x00018000
516 #define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */
517 #define PLLMR_PCI_PLB_DIV_1 0x00000000
518 #define PLLMR_PCI_PLB_DIV_2 0x00002000
519 #define PLLMR_PCI_PLB_DIV_3 0x00004000
520 #define PLLMR_PCI_PLB_DIV_4 0x00006000
522 #define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */
523 #define PLLMR_EXB_PLB_DIV_2 0x00000000
524 #define PLLMR_EXB_PLB_DIV_3 0x00000800
525 #define PLLMR_EXB_PLB_DIV_4 0x00001000
526 #define PLLMR_EXB_PLB_DIV_5 0x00001800
528 /* definitions for PPC405GPr (new mode strapping) */
529 #define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */
531 #define PSR_PLL_FWD_MASK 0xC0000000
532 #define PSR_PLL_FDBACK_MASK 0x30000000
533 #define PSR_PLL_TUNING_MASK 0x0E000000
534 #define PSR_PLB_CPU_MASK 0x01800000
535 #define PSR_OPB_PLB_MASK 0x00600000
536 #define PSR_PCI_PLB_MASK 0x00180000
537 #define PSR_EB_PLB_MASK 0x00060000
538 #define PSR_ROM_WIDTH_MASK 0x00018000
539 #define PSR_ROM_LOC 0x00004000
540 #define PSR_PCI_ASYNC_EN 0x00001000
541 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */
542 #define PSR_PCI_ARBIT_EN 0x00000400
543 #define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */
545 #ifndef CONFIG_IOP480
547 * PLL Voltage Controlled Oscillator (VCO) definitions
548 * Maximum and minimum values (in MHz) for correct PLL operation.
552 #endif /* #ifndef CONFIG_IOP480 */
553 #endif /* #ifdef CONFIG_405EP */
555 /******************************************************************************
556 * Memory Access Layer
557 ******************************************************************************/
558 #if defined(CONFIG_405EZ)
559 #define MAL_DCR_BASE 0x380
560 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
561 #define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/
562 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
563 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
564 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/
565 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
566 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
567 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
568 /* 0x08-0x0F Reserved */
569 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/
570 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
571 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
572 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
573 /* 0x14-0x1F Reserved */
574 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */
575 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */
576 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */
577 #define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */
578 #define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */
579 #define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */
580 #define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */
581 #define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */
582 #define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */
583 #define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */
584 #define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */
585 #define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */
586 #define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */
587 #define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */
588 #define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */
589 #define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */
590 #define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */
591 #define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */
592 #define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */
593 #define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */
594 #define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */
595 #define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */
596 #define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */
597 #define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */
598 #define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */
599 #define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */
600 #define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */
601 #define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */
602 #define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */
603 #define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */
604 #define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */
605 #define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */
606 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */
607 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */
608 #define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */
609 #define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */
610 #define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */
611 #define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */
612 #define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */
613 #define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */
614 #define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */
615 #define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */
616 #define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */
617 #define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */
618 #define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */
619 #define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */
620 #define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */
621 #define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */
622 #define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */
623 #define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */
624 #define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */
625 #define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */
626 #define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */
627 #define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */
628 #define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */
629 #define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */
630 #define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */
631 #define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */
632 #define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */
633 #define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */
634 #define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */
635 #define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */
636 #define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */
637 #define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */
638 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
639 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
640 #define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */
641 #define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */
642 #define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */
643 #define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */
644 #define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */
645 #define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */
646 #define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */
647 #define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */
648 #define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */
649 #define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */
650 #define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */
651 #define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */
652 #define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */
653 #define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */
654 #define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */
655 #define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */
656 #define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */
657 #define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */
658 #define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */
659 #define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */
660 #define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */
661 #define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */
662 #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
663 #define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */
664 #define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */
665 #define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */
666 #define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */
667 #define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */
668 #define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */
669 #define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */
671 #else /* !defined(CONFIG_405EZ) */
673 #define MAL_DCR_BASE 0x180
674 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */
675 #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */
676 #define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */
677 #define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */
678 #define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */
679 #define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */
680 #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */
681 #define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */
682 #define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */
683 #define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */
684 #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */
685 #define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */
686 #define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */
687 #define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */
688 #define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */
689 #define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
690 #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
691 #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
692 #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */
693 #endif /* defined(CONFIG_405EZ) */
695 /*-----------------------------------------------------------------------------
696 | IIC Register Offsets
697 '----------------------------------------------------------------------------*/
698 #define IICMDBUF 0x00
699 #define IICSDBUF 0x02
700 #define IICLMADR 0x04
701 #define IICHMADR 0x05
703 #define IICMDCNTL 0x07
705 #define IICEXTSTS 0x09
706 #define IICLSADR 0x0A
707 #define IICHSADR 0x0B
708 #define IICCLKDIV 0x0C
709 #define IICINTRMSK 0x0D
710 #define IICXFRCNT 0x0E
711 #define IICXTCNTLSS 0x0F
712 #define IICDIRECTCNTL 0x10
714 /*-----------------------------------------------------------------------------
715 | UART Register Offsets
716 '----------------------------------------------------------------------------*/
717 #define DATA_REG 0x00
720 #define INT_ENABLE 0x01
721 #define FIFO_CONTROL 0x02
722 #define LINE_CONTROL 0x03
723 #define MODEM_CONTROL 0x04
724 #define LINE_STATUS 0x05
725 #define MODEM_STATUS 0x06
728 /******************************************************************************
730 ******************************************************************************/
731 #if defined(CONFIG_405EZ)
732 #define OCM_DCR_BASE 0x020
733 #define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */
734 #define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */
735 #define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */
736 #define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */
737 #define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */
738 #define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */
739 #define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */
740 #define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */
741 #define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */
742 #define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */
743 #define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */
744 #define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */
745 #define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/
746 #define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/
747 #define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/
749 #define OCM_DCR_BASE 0x018
750 #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */
751 #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */
752 #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */
753 #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */
754 #endif /* CONFIG_405EZ */
756 /******************************************************************************
757 * GPIO macro register defines
758 ******************************************************************************/
759 #if defined(CONFIG_405EZ)
760 /* Only the 405EZ has 2 GPIOs */
761 #define GPIO_BASE 0xEF600700
762 #define GPIO0_OR (GPIO_BASE+0x0)
763 #define GPIO0_TCR (GPIO_BASE+0x4)
764 #define GPIO0_OSRL (GPIO_BASE+0x8)
765 #define GPIO0_OSRH (GPIO_BASE+0xC)
766 #define GPIO0_TSRL (GPIO_BASE+0x10)
767 #define GPIO0_TSRH (GPIO_BASE+0x14)
768 #define GPIO0_ODR (GPIO_BASE+0x18)
769 #define GPIO0_IR (GPIO_BASE+0x1C)
770 #define GPIO0_RR1 (GPIO_BASE+0x20)
771 #define GPIO0_RR2 (GPIO_BASE+0x24)
772 #define GPIO0_RR3 (GPIO_BASE+0x28)
773 #define GPIO0_ISR1L (GPIO_BASE+0x30)
774 #define GPIO0_ISR1H (GPIO_BASE+0x34)
775 #define GPIO0_ISR2L (GPIO_BASE+0x38)
776 #define GPIO0_ISR2H (GPIO_BASE+0x3C)
777 #define GPIO0_ISR3L (GPIO_BASE+0x40)
778 #define GPIO0_ISR3H (GPIO_BASE+0x44)
780 #define GPIO1_BASE 0xEF600800
781 #define GPIO1_OR (GPIO1_BASE+0x0)
782 #define GPIO1_TCR (GPIO1_BASE+0x4)
783 #define GPIO1_OSRL (GPIO1_BASE+0x8)
784 #define GPIO1_OSRH (GPIO1_BASE+0xC)
785 #define GPIO1_TSRL (GPIO1_BASE+0x10)
786 #define GPIO1_TSRH (GPIO1_BASE+0x14)
787 #define GPIO1_ODR (GPIO1_BASE+0x18)
788 #define GPIO1_IR (GPIO1_BASE+0x1C)
789 #define GPIO1_RR1 (GPIO1_BASE+0x20)
790 #define GPIO1_RR2 (GPIO1_BASE+0x24)
791 #define GPIO1_RR3 (GPIO1_BASE+0x28)
792 #define GPIO1_ISR1L (GPIO1_BASE+0x30)
793 #define GPIO1_ISR1H (GPIO1_BASE+0x34)
794 #define GPIO1_ISR2L (GPIO1_BASE+0x38)
795 #define GPIO1_ISR2H (GPIO1_BASE+0x3C)
796 #define GPIO1_ISR3L (GPIO1_BASE+0x40)
797 #define GPIO1_ISR3H (GPIO1_BASE+0x44)
799 #elif defined(CONFIG_405EX)
800 #define GPIO_BASE 0xEF600800
801 #define GPIO0_OR (GPIO_BASE+0x0)
802 #define GPIO0_TCR (GPIO_BASE+0x4)
803 #define GPIO0_OSRL (GPIO_BASE+0x8)
804 #define GPIO0_OSRH (GPIO_BASE+0xC)
805 #define GPIO0_TSRL (GPIO_BASE+0x10)
806 #define GPIO0_TSRH (GPIO_BASE+0x14)
807 #define GPIO0_ODR (GPIO_BASE+0x18)
808 #define GPIO0_IR (GPIO_BASE+0x1C)
809 #define GPIO0_RR1 (GPIO_BASE+0x20)
810 #define GPIO0_RR2 (GPIO_BASE+0x24)
811 #define GPIO0_ISR1L (GPIO_BASE+0x30)
812 #define GPIO0_ISR1H (GPIO_BASE+0x34)
813 #define GPIO0_ISR2L (GPIO_BASE+0x38)
814 #define GPIO0_ISR2H (GPIO_BASE+0x3C)
815 #define GPIO0_ISR3L (GPIO_BASE+0x40)
816 #define GPIO0_ISR3H (GPIO_BASE+0x44)
820 #define GPIO_BASE 0xEF600700
821 #define GPIO0_OR (GPIO_BASE+0x0)
822 #define GPIO0_TCR (GPIO_BASE+0x4)
823 #define GPIO0_OSRH (GPIO_BASE+0x8)
824 #define GPIO0_OSRL (GPIO_BASE+0xC)
825 #define GPIO0_TSRH (GPIO_BASE+0x10)
826 #define GPIO0_TSRL (GPIO_BASE+0x14)
827 #define GPIO0_ODR (GPIO_BASE+0x18)
828 #define GPIO0_IR (GPIO_BASE+0x1C)
829 #define GPIO0_RR1 (GPIO_BASE+0x20)
830 #define GPIO0_RR2 (GPIO_BASE+0x24)
831 #define GPIO0_ISR1H (GPIO_BASE+0x30)
832 #define GPIO0_ISR1L (GPIO_BASE+0x34)
833 #define GPIO0_ISR2H (GPIO_BASE+0x38)
834 #define GPIO0_ISR2L (GPIO_BASE+0x3C)
836 #endif /* CONFIG_405EZ */
838 #define GPIO0_BASE GPIO_BASE
840 #if defined(CONFIG_405EX)
841 #define SDR0_SRST 0x0200
844 * Software Reset Register
846 #define SDR0_SRST_BGO PPC_REG_VAL(0, 1)
847 #define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1)
848 #define SDR0_SRST_EBC PPC_REG_VAL(2, 1)
849 #define SDR0_SRST_OPB PPC_REG_VAL(3, 1)
850 #define SDR0_SRST_UART0 PPC_REG_VAL(4, 1)
851 #define SDR0_SRST_UART1 PPC_REG_VAL(5, 1)
852 #define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1)
853 #define SDR0_SRST_BGI PPC_REG_VAL(7, 1)
854 #define SDR0_SRST_GPIO PPC_REG_VAL(8, 1)
855 #define SDR0_SRST_GPT PPC_REG_VAL(9, 1)
856 #define SDR0_SRST_DMC PPC_REG_VAL(10, 1)
857 #define SDR0_SRST_RGMII PPC_REG_VAL(11, 1)
858 #define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1)
859 #define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1)
860 #define SDR0_SRST_CPM PPC_REG_VAL(14, 1)
861 #define SDR0_SRST_EPLL PPC_REG_VAL(15, 1)
862 #define SDR0_SRST_UIC PPC_REG_VAL(16, 1)
863 #define SDR0_SRST_UPRST PPC_REG_VAL(17, 1)
864 #define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1)
865 #define SDR0_SRST_SCP PPC_REG_VAL(19, 1)
866 #define SDR0_SRST_UHRST PPC_REG_VAL(20, 1)
867 #define SDR0_SRST_DMA PPC_REG_VAL(21, 1)
868 #define SDR0_SRST_DMAC PPC_REG_VAL(22, 1)
869 #define SDR0_SRST_MAL PPC_REG_VAL(23, 1)
870 #define SDR0_SRST_EBM PPC_REG_VAL(24, 1)
871 #define SDR0_SRST_GPTR PPC_REG_VAL(25, 1)
872 #define SDR0_SRST_PE0 PPC_REG_VAL(26, 1)
873 #define SDR0_SRST_PE1 PPC_REG_VAL(27, 1)
874 #define SDR0_SRST_CRYP PPC_REG_VAL(28, 1)
875 #define SDR0_SRST_PKP PPC_REG_VAL(29, 1)
876 #define SDR0_SRST_AHB PPC_REG_VAL(30, 1)
877 #define SDR0_SRST_NDFC PPC_REG_VAL(31, 1)
879 #define sdr_uart0 0x0120 /* UART0 Config */
880 #define sdr_uart1 0x0121 /* UART1 Config */
881 #define sdr_mfr 0x4300 /* SDR0_MFR reg */
883 /* Defines for CPC0_EPRCSR register */
884 #define CPC0_EPRCSR_E0NFE 0x80000000
885 #define CPC0_EPRCSR_E1NFE 0x40000000
886 #define CPC0_EPRCSR_E1RPP 0x00000080
887 #define CPC0_EPRCSR_E0RPP 0x00000040
888 #define CPC0_EPRCSR_E1ERP 0x00000020
889 #define CPC0_EPRCSR_E0ERP 0x00000010
890 #define CPC0_EPRCSR_E1PCI 0x00000002
891 #define CPC0_EPRCSR_E0PCI 0x00000001
893 #define cpr0_clkupd 0x020
894 #define cpr0_pllc 0x040
895 #define cpr0_plld 0x060
896 #define cpr0_cpud 0x080
897 #define cpr0_plbd 0x0a0
898 #define cpr0_opbd 0x0c0
899 #define cpr0_perd 0x0e0
900 #define cpr0_ahbd 0x100
901 #define cpr0_icfg 0x140
903 #define SDR_PINSTP 0x0040
904 #define sdr_sdcs 0x0060
906 #define SDR0_SDCS_SDD (0x80000000 >> 31)
908 /* CUST0 Customer Configuration Register0 */
909 #define SDR0_CUST0 0x4000
910 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */
911 #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */
912 #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */
913 #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */
915 #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */
916 #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */
917 #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */
919 #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */
920 #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */
921 #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */
923 #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */
924 #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24)
925 #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F)
927 #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */
928 #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22)
929 #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03)
931 #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */
932 #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */
933 #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */
935 #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */
936 #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */
937 #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */
939 #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */
940 #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4)
941 #define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF)
943 #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */
944 #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */
945 #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */
946 #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */
947 #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */
948 #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */
949 #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */
951 #define SDR0_PFC0 0x4100
952 #define SDR0_PFC1 0x4101
953 #define SDR0_PFC1_U1ME 0x02000000
954 #define SDR0_PFC1_U0ME 0x00080000
955 #define SDR0_PFC1_U0IM 0x00040000
956 #define SDR0_PFC1_SIS 0x00020000
957 #define SDR0_PFC1_DMAAEN 0x00010000
958 #define SDR0_PFC1_DMADEN 0x00008000
959 #define SDR0_PFC1_USBEN 0x00004000
960 #define SDR0_PFC1_AHBSWAP 0x00000020
961 #define SDR0_PFC1_USBBIGEN 0x00000010
962 #define SDR0_PFC1_GPT_FREQ 0x0000000f
965 /* General Purpose Timer (GPT) Register Offsets */
966 #define GPT0_TBC 0x00000000
967 #define GPT0_IM 0x00000018
968 #define GPT0_ISS 0x0000001C
969 #define GPT0_ISC 0x00000020
970 #define GPT0_IE 0x00000024
971 #define GPT0_COMP0 0x00000080
972 #define GPT0_COMP1 0x00000084
973 #define GPT0_COMP2 0x00000088
974 #define GPT0_COMP3 0x0000008C
975 #define GPT0_COMP4 0x00000090
976 #define GPT0_COMP5 0x00000094
977 #define GPT0_COMP6 0x00000098
978 #define GPT0_MASK0 0x000000C0
979 #define GPT0_MASK1 0x000000C4
980 #define GPT0_MASK2 0x000000C8
981 #define GPT0_MASK3 0x000000CC
982 #define GPT0_MASK4 0x000000D0
983 #define GPT0_MASK5 0x000000D4
984 #define GPT0_MASK6 0x000000D8
985 #define GPT0_DCT0 0x00000110
986 #define GPT0_DCIS 0x0000011C
988 #endif /* __PPC405_H__ */
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