include/power/stpmic1.h

   1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #ifndef __PMIC_STPMIC1_H_
   7 #define __PMIC_STPMIC1_H_
   8
   9 #include <linux/bitops.h>
  10 #define STPMIC1_MAIN_CR                 0x10
  11 #define STPMIC1_BUCKS_MRST_CR           0x18
  12 #define STPMIC1_LDOS_MRST_CR            0x1a
  13 #define STPMIC1_BUCKX_MAIN_CR(buck)     (0x20 + (buck))
  14 #define STPMIC1_REFDDR_MAIN_CR          0x24
  15 #define STPMIC1_LDOX_MAIN_CR(ldo)       (0x25 + (ldo))
  16 #define STPMIC1_BST_SW_CR               0x40
  17 #define STPMIC1_NVM_SR                  0xb8
  18 #define STPMIC1_NVM_CR                  0xb9
  19
  20 /* Main PMIC Control Register (MAIN_CR) */
  21 #define STPMIC1_SWOFF                   BIT(0)
  22 #define STPMIC1_RREQ_EN                 BIT(1)
  23
  24 /* BUCKS_MRST_CR */
  25 #define STPMIC1_MRST_BUCK(buck)         BIT(buck)
  26 #define STPMIC1_MRST_BUCK_DEBUG         (STPMIC1_MRST_BUCK(STPMIC1_BUCK1) | \
  27                                          STPMIC1_MRST_BUCK(STPMIC1_BUCK3))
  28
  29 /* LDOS_MRST_CR */
  30 #define STPMIC1_MRST_LDO(ldo)           BIT(ldo)
  31 #define STPMIC1_MRST_LDO_DEBUG          0
  32
  33 /* BUCKx_MAIN_CR (x=1...4) */
  34 #define STPMIC1_BUCK_ENA                BIT(0)
  35 #define STPMIC1_BUCK_PREG_MODE          BIT(1)
  36 #define STPMIC1_BUCK_VOUT_MASK          GENMASK(7, 2)
  37 #define STPMIC1_BUCK_VOUT_SHIFT         2
  38 #define STPMIC1_BUCK_VOUT(sel)          (sel << STPMIC1_BUCK_VOUT_SHIFT)
  39
  40 #define STPMIC1_BUCK2_1200000V          STPMIC1_BUCK_VOUT(24)
  41 #define STPMIC1_BUCK2_1250000V          STPMIC1_BUCK_VOUT(26)
  42 #define STPMIC1_BUCK2_1350000V          STPMIC1_BUCK_VOUT(30)
  43
  44 #define STPMIC1_BUCK3_1800000V          STPMIC1_BUCK_VOUT(39)
  45
  46 /* REFDDR_MAIN_CR */
  47 #define STPMIC1_VREF_ENA                BIT(0)
  48
  49 /* LDOX_MAIN_CR */
  50 #define STPMIC1_LDO_ENA                 BIT(0)
  51 #define STPMIC1_LDO12356_VOUT_MASK      GENMASK(6, 2)
  52 #define STPMIC1_LDO12356_VOUT_SHIFT     2
  53 #define STPMIC1_LDO_VOUT(sel)           (sel << STPMIC1_LDO12356_VOUT_SHIFT)
  54
  55 #define STPMIC1_LDO3_MODE               BIT(7)
  56 #define STPMIC1_LDO3_DDR_SEL            31
  57 #define STPMIC1_LDO3_1800000            STPMIC1_LDO_VOUT(9)
  58
  59 #define STPMIC1_LDO4_UV                 3300000
  60
  61 /* BST_SW_CR */
  62 #define STPMIC1_BST_ON                  BIT(0)
  63 #define STPMIC1_VBUSOTG_ON              BIT(1)
  64 #define STPMIC1_SWOUT_ON                BIT(2)
  65 #define STPMIC1_PWR_SW_ON               (STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
  66
  67 /* NVM_SR */
  68 #define STPMIC1_NVM_BUSY                BIT(0)
  69
  70 /* NVM_CR */
  71 #define STPMIC1_NVM_CMD_PROGRAM         1
  72 #define STPMIC1_NVM_CMD_READ            2
  73
  74 /* Timeout */
  75 #define STPMIC1_DEFAULT_START_UP_DELAY_MS       1
  76 #define STPMIC1_DEFAULT_STOP_DELAY_MS           5
  77 #define STPMIC1_USB_BOOST_START_UP_DELAY_MS     10
  78
  79 enum {
  80         STPMIC1_BUCK1,
  81         STPMIC1_BUCK2,
  82         STPMIC1_BUCK3,
  83         STPMIC1_BUCK4,
  84         STPMIC1_MAX_BUCK,
  85 };
  86
  87 enum {
  88         STPMIC1_PREG_MODE_HP,
  89         STPMIC1_PREG_MODE_LP,
  90 };
  91
  92 enum {
  93         STPMIC1_LDO1,
  94         STPMIC1_LDO2,
  95         STPMIC1_LDO3,
  96         STPMIC1_LDO4,
  97         STPMIC1_LDO5,
  98         STPMIC1_LDO6,
  99         STPMIC1_MAX_LDO,
 100 };
 101
 102 enum {
 103         STPMIC1_LDO_MODE_NORMAL,
 104         STPMIC1_LDO_MODE_BYPASS,
 105         STPMIC1_LDO_MODE_SINK_SOURCE,
 106 };
 107
 108 enum {
 109         STPMIC1_PWR_SW1,
 110         STPMIC1_PWR_SW2,
 111         STPMIC1_MAX_PWR_SW,
 112 };
 113 #endif