include/power/rk8xx_pmic.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2015 Google, Inc
   4  * Written by Simon Glass <sjg@chromium.org>
   5  */
   6
   7 #ifndef _PMIC_RK8XX_H_
   8 #define _PMIC_RK8XX_H_
   9
  10 enum {
  11         REG_SECONDS                     = 0x00,
  12         REG_MINUTES,
  13         REG_HOURS,
  14         REG_DAYS,
  15         REG_MONTHS,
  16         REG_YEARS,
  17         REG_WEEKS,
  18         REG_ALARM_SECONDS,
  19         REG_ALARM_MINUTES,
  20         REG_ALARM_HOURS,
  21         REG_ALARM_DAYS,
  22         REG_ALARM_MONTHS,
  23         REG_ALARM_YEARS,
  24
  25         REG_RTC_CTRL                    = 0x10,
  26         REG_RTC_STATUS,
  27         REG_RTC_INT,
  28         REG_RTC_COMP_LSB,
  29         REG_RTC_COMP_MSB,
  30
  31         ID_MSB                          = 0x17,
  32         ID_LSB,
  33
  34         REG_CLK32OUT                    = 0x20,
  35         REG_VB_MON,
  36         REG_THERMAL,
  37         REG_DCDC_EN,
  38         REG_LDO_EN,
  39         REG_SLEEP_SET_OFF1,
  40         REG_SLEEP_SET_OFF2,
  41         REG_DCDC_UV_STS,
  42         REG_DCDC_UV_ACT,
  43         REG_LDO_UV_STS,
  44         REG_LDO_UV_ACT,
  45         REG_DCDC_PG,
  46         REG_LDO_PG,
  47         REG_VOUT_MON_TDB,
  48         REG_BUCK1_CONFIG,
  49         REG_BUCK1_ON_VSEL,
  50         REG_BUCK1_SLP_VSEL,
  51         REG_BUCK1_DVS_VSEL,
  52         REG_BUCK2_CONFIG,
  53         REG_BUCK2_ON_VSEL,
  54         REG_BUCK2_SLP_VSEL,
  55         REG_BUCK2_DVS_VSEL,
  56         REG_BUCK3_CONFIG,
  57         REG_BUCK4_CONFIG,
  58         REG_BUCK4_ON_VSEL,
  59         REG_BUCK4_SLP_VSEL,
  60         REG_BOOST_CONFIG_REG,
  61         REG_LDO1_ON_VSEL,
  62         REG_LDO1_SLP_VSEL,
  63         REG_LDO2_ON_VSEL,
  64         REG_LDO2_SLP_VSEL,
  65         REG_LDO3_ON_VSEL,
  66         REG_LDO3_SLP_VSEL,
  67         REG_LDO4_ON_VSEL,
  68         REG_LDO4_SLP_VSEL,
  69         REG_LDO5_ON_VSEL,
  70         REG_LDO5_SLP_VSEL,
  71         REG_LDO6_ON_VSEL,
  72         REG_LDO6_SLP_VSEL,
  73         REG_LDO7_ON_VSEL,
  74         REG_LDO7_SLP_VSEL,
  75         REG_LDO8_ON_VSEL,
  76         REG_LDO8_SLP_VSEL,
  77         REG_DEVCTRL,
  78         REG_INT_STS1,
  79         REG_INT_STS_MSK1,
  80         REG_INT_STS2,
  81         REG_INT_STS_MSK2,
  82         REG_IO_POL,
  83         REG_OTP_VDD_EN,
  84         REG_H5V_EN,
  85         REG_SLEEP_SET_OFF,
  86         REG_BOOST_LDO9_ON_VSEL,
  87         REG_BOOST_LDO9_SLP_VSEL,
  88         REG_BOOST_CTRL,
  89
  90         /* Not sure what this does */
  91         REG_DCDC_ILMAX                  = 0x90,
  92         REG_CHRG_COMP                   = 0x9a,
  93         REG_SUP_STS                     = 0xa0,
  94         REG_USB_CTRL,
  95         REG1_CHRG_CTRL,
  96         REG2_CHRG_CTRL,
  97         REG3_CHRG_CTRL,
  98         REG_BAT_CTRL,
  99         REG_BAT_HTS_TS1,
 100         REG_BAT_LTS_TS1,
 101         REG_BAT_HTS_TS2,
 102         REG_BAT_LTS_TS2,
 103         REG_TS_CTRL,
 104         REG_ADC_CTRL,
 105         REG_ON_SOURCE,
 106         REG_OFF_SOURCE,
 107         REG_GGCON,
 108         REG_GGSTS,
 109         REG_FRAME_SMP_INTERV,
 110         REG_AUTO_SLP_CUR_THR,
 111         REG3_GASCNT_CAL,
 112         REG2_GASCNT_CAL,
 113         REG1_GASCNT_CAL,
 114         REG0_GASCNT_CAL,
 115         REG3_GASCNT,
 116         REG2_GASCNT,
 117         REG1_GASCNT,
 118         REG0_GASCNT,
 119         REGH_BAT_CUR_AVG,
 120         REGL_BAT_CUR_AVG,
 121         REGH_TS1_ADC,
 122         REGL_TS1_ADC,
 123         REGH_TS2_ADC,
 124         REGL_TS2_ADC,
 125         REGH_BAT_OCV,
 126         REGL_BAT_OCV,
 127         REGH_BAT_VOL,
 128         REGL_BAT_VOL,
 129         REGH_RELAX_ENTRY_THRES,
 130         REGL_RELAX_ENTRY_THRES,
 131         REGH_RELAX_EXIT_THRES,
 132         REGL_RELAX_EXIT_THRES,
 133         REGH_RELAX_VOL1,
 134         REGL_RELAX_VOL1,
 135         REGH_RELAX_VOL2,
 136         REGL_RELAX_VOL2,
 137         REGH_BAT_CUR_R_CALC,
 138         REGL_BAT_CUR_R_CALC,
 139         REGH_BAT_VOL_R_CALC,
 140         REGL_BAT_VOL_R_CALC,
 141         REGH_CAL_OFFSET,
 142         REGL_CAL_OFFSET,
 143         REG_NON_ACT_TIMER_CNT,
 144         REGH_VCALIB0,
 145         REGL_VCALIB0,
 146         REGH_VCALIB1,
 147         REGL_VCALIB1,
 148         REGH_IOFFSET,
 149         REGL_IOFFSET,
 150         REG_SOC,
 151         REG3_REMAIN_CAP,
 152         REG2_REMAIN_CAP,
 153         REG1_REMAIN_CAP,
 154         REG0_REMAIN_CAP,
 155         REG_UPDAT_LEVE,
 156         REG3_NEW_FCC,
 157         REG2_NEW_FCC,
 158         REG1_NEW_FCC,
 159         REG0_NEW_FCC,
 160         REG_NON_ACT_TIMER_CNT_SAVE,
 161         REG_OCV_VOL_VALID,
 162         REG_REBOOT_CNT,
 163         REG_POFFSET,
 164         REG_MISC_MARK,
 165         REG_HALT_CNT,
 166         REGH_CALC_REST,
 167         REGL_CALC_REST,
 168         SAVE_DATA19,
 169         RK808_NUM_OF_REGS,
 170 };
 171
 172 enum {
 173         RK817_REG_SYS_CFG3 = 0xf4,
 174 };
 175
 176 enum {
 177         RK816_REG_DCDC_EN1 = 0x23,
 178         RK816_REG_DCDC_EN2,
 179         RK816_REG_DCDC_SLP_EN,
 180         RK816_REG_LDO_SLP_EN,
 181         RK816_REG_LDO_EN1 = 0x27,
 182         RK816_REG_LDO_EN2,
 183 };
 184
 185 enum {
 186         RK805_ID = 0x8050,
 187         RK808_ID = 0x0000,
 188         RK809_ID = 0x8090,
 189         RK816_ID = 0x8160,
 190         RK817_ID = 0x8170,
 191         RK818_ID = 0x8180,
 192 };
 193
 194 enum {
 195         RK817_POWER_EN0 = 0xb1,
 196         RK817_POWER_EN1,
 197         RK817_POWER_EN2,
 198         RK817_POWER_EN3,
 199 };
 200
 201 #define RK817_POWER_EN_SAVE0    0x99
 202 #define RK817_POWER_EN_SAVE1    0xa4
 203
 204 #define RK817_ID_MSB    0xed
 205 #define RK817_ID_LSB    0xee
 206 #define RK8XX_ID_MSK    0xfff0
 207
 208 #define RK817_PMIC_SYS_CFG3     0xf4
 209 #define RK817_GPIO_INT_CFG      0xfe
 210
 211 #define RK8XX_ON_SOURCE         0xae
 212 #define RK8XX_OFF_SOURCE        0xaf
 213 #define RK817_BUCK4_CMIN        0xc6
 214 #define RK817_ON_SOURCE         0xf5
 215 #define RK817_OFF_SOURCE        0xf6
 216
 217 struct reg_data {
 218         u8 reg;
 219         u8 val;
 220         u8 mask;
 221 };
 222 struct rk8xx_reg_table {
 223         char *name;
 224         u8 reg_ctl;
 225         u8 reg_vol;
 226 };
 227
 228 struct rk8xx_priv {
 229         int variant;
 230 };
 231
 232 int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
 233 int rk818_spl_configure_usb_input_current(struct udevice *pmic, int current_ma);
 234 int rk818_spl_configure_usb_chrg_shutdown(struct udevice *pmic, int uvolt);
 235
 236 #endif