include/pmic_s5m8767.h

   1 #ifndef __PMIC_S5M8767_H__
   2 #define __PMIC_S5M8767_H__
   3
   4 /* S5M8767 PMIC Registers. */
   5 enum s5m8767_reg {
   6
   7         S5M8767_REG_ID,
   8         S5M8767_REG_INT1,
   9         S5M8767_REG_INT2,
  10         S5M8767_REG_INT3,
  11         S5M8767_REG_INT1M,
  12         S5M8767_REG_INT2M,
  13         S5M8767_REG_INT3M,
  14         S5M8767_REG_STATUS1,
  15         S5M8767_REG_STATUS2,
  16         S5M8767_REG_STATUS3,
  17         S5M8767_REG_CTRL1,
  18         S5M8767_REG_CTRL2,
  19         S5M8767_REG_LOWBAT1,
  20         S5M8767_REG_LOWBAT2,
  21         S5M8767_REG_BUCHG,
  22         S5M8767_REG_DVSRAMP,
  23         S5M8767_REG_DVSTIMER2 = 0x10,
  24         S5M8767_REG_DVSTIMER3,
  25         S5M8767_REG_DVSTIMER4,
  26         S5M8767_REG_LDO1,
  27         S5M8767_REG_LDO2,
  28         S5M8767_REG_LDO3,
  29         S5M8767_REG_LDO4,
  30         S5M8767_REG_LDO5,
  31         S5M8767_REG_LDO6,
  32         S5M8767_REG_LDO7,
  33         S5M8767_REG_LDO8,
  34         S5M8767_REG_LDO9,
  35         S5M8767_REG_LDO10,
  36         S5M8767_REG_LDO11,
  37         S5M8767_REG_LDO12,
  38         S5M8767_REG_LDO13,
  39         S5M8767_REG_LDO14 = 0x20,
  40         S5M8767_REG_LDO15,
  41         S5M8767_REG_LDO16,
  42         S5M8767_REG_LDO17,
  43         S5M8767_REG_LDO18,
  44         S5M8767_REG_LDO19,
  45         S5M8767_REG_LDO20,
  46         S5M8767_REG_LDO21,
  47         S5M8767_REG_LDO22,
  48         S5M8767_REG_LDO23,
  49         S5M8767_REG_LDO24,
  50         S5M8767_REG_LDO25,
  51         S5M8767_REG_LDO26,
  52         S5M8767_REG_LDO27,
  53         S5M8767_REG_LDO28,
  54         S5M8767_REG_UVLO = 0x31,
  55         S5M8767_REG_BUCK1CTRL1,
  56         S5M8767_REG_BUCK1CTRL2,
  57         S5M8767_REG_BUCK2CTRL,
  58         S5M8767_REG_BUCK2DVS1,
  59         S5M8767_REG_BUCK2DVS2,
  60         S5M8767_REG_BUCK2DVS3,
  61         S5M8767_REG_BUCK2DVS4,
  62         S5M8767_REG_BUCK2DVS5,
  63         S5M8767_REG_BUCK2DVS6,
  64         S5M8767_REG_BUCK2DVS7,
  65         S5M8767_REG_BUCK2DVS8,
  66         S5M8767_REG_BUCK3CTRL,
  67         S5M8767_REG_BUCK3DVS1,
  68         S5M8767_REG_BUCK3DVS2,
  69         S5M8767_REG_BUCK3DVS3,
  70         S5M8767_REG_BUCK3DVS4,
  71         S5M8767_REG_BUCK3DVS5,
  72         S5M8767_REG_BUCK3DVS6,
  73         S5M8767_REG_BUCK3DVS7,
  74         S5M8767_REG_BUCK3DVS8,
  75         S5M8767_REG_BUCK4CTRL,
  76         S5M8767_REG_BUCK4DVS1,
  77         S5M8767_REG_BUCK4DVS2,
  78         S5M8767_REG_BUCK4DVS3,
  79         S5M8767_REG_BUCK4DVS4,
  80         S5M8767_REG_BUCK4DVS5,
  81         S5M8767_REG_BUCK4DVS6,
  82         S5M8767_REG_BUCK4DVS7,
  83         S5M8767_REG_BUCK4DVS8,
  84         S5M8767_REG_BUCK5CTRL1,
  85         S5M8767_REG_BUCK5CTRL2,
  86         S5M8767_REG_BUCK5CTRL3,
  87         S5M8767_REG_BUCK5CTRL4,
  88         S5M8767_REG_BUCK5CTRL5,
  89         S5M8767_REG_BUCK6CTRL1,
  90         S5M8767_REG_BUCK6CTRL2,
  91         S5M8767_REG_BUCK7CTRL1,
  92         S5M8767_REG_BUCK7CTRL2,
  93         S5M8767_REG_BUCK8CTRL1,
  94         S5M8767_REG_BUCK8CTRL2,
  95         S5M8767_REG_BUCK9CTRL1,
  96         S5M8767_REG_BUCK9CTRL2,
  97         S5M8767_REG_LDO1CTRL,
  98         S5M8767_REG_LDO2_1CTRL,
  99         S5M8767_REG_LDO2_2CTRL,
 100         S5M8767_REG_LDO2_3CTRL,
 101         S5M8767_REG_LDO2_4CTRL,
 102         S5M8767_REG_LDO3CTRL,
 103         S5M8767_REG_LDO4CTRL,
 104         S5M8767_REG_LDO5CTRL,
 105         S5M8767_REG_LDO6CTRL,
 106         S5M8767_REG_LDO7CTRL,
 107         S5M8767_REG_LDO8CTRL,
 108         S5M8767_REG_LDO9CTRL,
 109         S5M8767_REG_LDO10CTRL,
 110         S5M8767_REG_LDO11CTRL,
 111         S5M8767_REG_LDO12CTRL,
 112         S5M8767_REG_LDO13CTRL,
 113         S5M8767_REG_LDO14CTRL,
 114         S5M8767_REG_LDO15CTRL,
 115         S5M8767_REG_LDO16CTRL,
 116         S5M8767_REG_LDO17CTRL,
 117         S5M8767_REG_LDO18CTRL,
 118         S5M8767_REG_LDO19CTRL,
 119         S5M8767_REG_LDO20CTRL,
 120         S5M8767_REG_LDO21CTRL,
 121         S5M8767_REG_LDO22CTRL,
 122         S5M8767_REG_LDO23CTRL,
 123         S5M8767_REG_LDO24CTRL,
 124         S5M8767_REG_LDO25CTRL,
 125         S5M8767_REG_LDO26CTRL,
 126         S5M8767_REG_LDO27CTRL,
 127         S5M8767_REG_LDO28CTRL,
 128         S5M8767_INTSRC = 0xE0,
 129 };
 130
 131 #define S5M8767_32KHZ                   S5M8767_REG_CTRL1
 132
 133 /* PMIC_RTC registers . */
 134 #define PMIC_RTC_TIME_ADDR      0x0
 135 #define PMIC_RTC_ALARM0_ADDR    0x8
 136 #define PMIC_RTC_ALARM1_ADDR    0x10
 137 #define PMIC_RTC_ALRM0CONF_REG  0x18
 138 #define PMIC_RTC_ALRM1CONF_REG  0x19
 139 #define PMIC_RTC_WTSR_SMPL_REG  0x1B
 140
 141 /* PMIC_RTC register time sets . */
 142 #define PMIC_REG_SECOND     0
 143 #define PMIC_REG_MIN        1
 144 #define PMIC_REG_HOUR       2
 145 #define PMIC_REG_WEEKDAY    3
 146 #define PMIC_REG_DATE       4
 147 #define PMIC_REG_MONTH      5
 148 #define PMIC_REG_YEAR0      6
 149 #define PMIC_REG_YEAR1      7
 150
 151 #define PMIC_RTC_LEN        8
 152
 153 /* i2c slave address. */
 154 #define S5M8767_I2C_ADDRESS   (0xCC)
 155 #define S5M8767_RTC_I2C_ADDRESS  (0x0C)
 156
 157 enum PMIC_LDO {
 158         PMIC_LDO1 = 0,
 159         PMIC_LDO2,
 160         PMIC_LDO3,
 161         PMIC_LDO4,
 162         PMIC_LDO5,
 163         PMIC_LDO6,
 164         PMIC_LDO7,
 165         PMIC_LDO8,
 166         PMIC_LDO9,
 167         PMIC_LDO10,
 168         PMIC_LDO11,
 169         PMIC_LDO12,
 170         PMIC_LDO13,
 171         PMIC_LDO14,
 172         PMIC_LDO15,
 173         PMIC_LDO16,
 174         PMIC_LDO17,
 175         PMIC_LDO18,
 176         PMIC_LDO19,
 177         PMIC_LDO20,
 178         PMIC_LDO21,
 179         PMIC_LDO22,
 180         PMIC_LDO23,
 181         PMIC_LDO24,
 182         PMIC_LDO25,
 183         PMIC_LDO26,
 184         PMIC_LDO27,
 185         PMIC_LDO28,
 186 };
 187
 188 typedef enum PMIC_BUCK {
 189         PMIC_BUCK1 = 0,
 190         PMIC_BUCK2,
 191         PMIC_BUCK3,
 192         PMIC_BUCK4
 193 } PMIC_RegNum;
 194
 195 #endif /* __PMIC_S5M8767_H__ */
 196
 197 static void PMIC_WRITE(char address, char data);
 198 static void pmic_reg_update(u8 addr, u8 data, u8 mask);
 199 u8 pmic_check_ldo_type(u8 ldo);
 200 void I2C_S5M8767_VolSetting(PMIC_RegNum eRegNum, u8 ucVolLevel, u8 ucEnable);
 201 static int S5M8767_probe(void);
 202 void pmic_init();
 203 void pmic_onoff(char *name, int onoff);
 204 static int pmic_detbat();
 205 void pmic_get_status(void);
 206 void pmic_lowpower();
 207 void pmic_highpower();
 208 int pmic_read(unsigned char reg, unsigned char *pch);
 209 int pmic_write(unsigned char reg, unsigned char pch);
 210 int pmic_ldo_enable(u8 ldo);
 211 int pmic_ldo_disable(u8 ldo);
 212 void battery_pole_disconnect_check(void);
 213 int pmic_7sec_reset();
 214 int pmic_check_rtc_alarm(void);
 215 int pmic_check_powerkey_irq(void);
 216 int pmic_check_longkey_reset(void);
 217 int pmic_check_jig_on(void);
 218 int pmic_check_dcinok(void);
 219 int pmic_set_mrstb(int en, int timeout);
 220 int pmic_check_charger_intr(void);
 221 int pmic_check_wtsr_intr(void);
 222 int pmic_check_smpl_intr(void);