2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
15 * Allow configuration to select PCMCIA slot,
16 * or try to generate a useful default
18 #if defined(CONFIG_CMD_PCMCIA) || \
19 (defined(CONFIG_CMD_IDE) && \
20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
24 #if defined(CONFIG_TQM8xxL)
25 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
26 #elif defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) /* The IVM* use SLOT_A */
27 # define CONFIG_PCMCIA_SLOT_A
28 #elif defined(CONFIG_LWMON) /* The LWMON use SLOT_B */
29 # define CONFIG_PCMCIA_SLOT_B
30 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
31 # define CONFIG_PCMCIA_SLOT_A
33 # error "PCMCIA Slot not configured"
36 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
38 /* Make sure exactly one slot is defined - we support only one for now */
39 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
40 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
42 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
43 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
46 #ifndef PCMCIA_SOCKETS_NO
47 #define PCMCIA_SOCKETS_NO 1
49 #ifndef PCMCIA_MEM_WIN_NO
50 #define PCMCIA_MEM_WIN_NO 4
52 #define PCMCIA_IO_WIN_NO 2
54 /* define _slot_ to be able to optimize macros */
55 #ifdef CONFIG_PCMCIA_SLOT_A
57 # define PCMCIA_SLOT_MSG "slot A"
58 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A
61 # define PCMCIA_SLOT_MSG "slot B"
62 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B
66 * The TQM850L hardware has two pins swapped! Grrrrgh!
69 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
70 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
72 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
73 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
77 * This structure is used to address each window in the PCMCIA controller.
79 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
80 * after pcmcia_win_t[n]...
89 * Definitions for PCMCIA control registers to operate in IDE mode
91 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
92 * to be done later (depending on CPU clock)
96 * Base: 0xFE100000 CS1
102 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
103 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
111 * Base: 0xFE100080 CS1
114 * Common Memory Space
117 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
118 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
126 * Base: 0xFE100100 CS2
129 * Common Memory Space
132 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
133 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
143 #define CONFIG_SYS_PCMCIA_PBR3 0
144 #define CONFIG_SYS_PCMCIA_POR3 0
147 * Base: 0xFE100C00 CS1
150 * Common Memory Space
153 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
154 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
162 * Base: 0xFE100C80 CS1
165 * Common Memory Space
168 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
169 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
177 * Base: 0xFE100D00 CS2
180 * Common Memory Space
183 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
184 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
194 #define CONFIG_SYS_PCMCIA_PBR7 0
195 #define CONFIG_SYS_PCMCIA_POR7 0
197 /**********************************************************************/
202 #define CISTPL_NULL 0x00
203 #define CISTPL_DEVICE 0x01
204 #define CISTPL_LONGLINK_CB 0x02
205 #define CISTPL_INDIRECT 0x03
206 #define CISTPL_CONFIG_CB 0x04
207 #define CISTPL_CFTABLE_ENTRY_CB 0x05
208 #define CISTPL_LONGLINK_MFC 0x06
209 #define CISTPL_BAR 0x07
210 #define CISTPL_PWR_MGMNT 0x08
211 #define CISTPL_EXTDEVICE 0x09
212 #define CISTPL_CHECKSUM 0x10
213 #define CISTPL_LONGLINK_A 0x11
214 #define CISTPL_LONGLINK_C 0x12
215 #define CISTPL_LINKTARGET 0x13
216 #define CISTPL_NO_LINK 0x14
217 #define CISTPL_VERS_1 0x15
218 #define CISTPL_ALTSTR 0x16
219 #define CISTPL_DEVICE_A 0x17
220 #define CISTPL_JEDEC_C 0x18
221 #define CISTPL_JEDEC_A 0x19
222 #define CISTPL_CONFIG 0x1a
223 #define CISTPL_CFTABLE_ENTRY 0x1b
224 #define CISTPL_DEVICE_OC 0x1c
225 #define CISTPL_DEVICE_OA 0x1d
226 #define CISTPL_DEVICE_GEO 0x1e
227 #define CISTPL_DEVICE_GEO_A 0x1f
228 #define CISTPL_MANFID 0x20
229 #define CISTPL_FUNCID 0x21
230 #define CISTPL_FUNCE 0x22
231 #define CISTPL_SWIL 0x23
232 #define CISTPL_END 0xff
235 * CIS Function ID codes
237 #define CISTPL_FUNCID_MULTI 0x00
238 #define CISTPL_FUNCID_MEMORY 0x01
239 #define CISTPL_FUNCID_SERIAL 0x02
240 #define CISTPL_FUNCID_PARALLEL 0x03
241 #define CISTPL_FUNCID_FIXED 0x04
242 #define CISTPL_FUNCID_VIDEO 0x05
243 #define CISTPL_FUNCID_NETWORK 0x06
244 #define CISTPL_FUNCID_AIMS 0x07
245 #define CISTPL_FUNCID_SCSI 0x08
248 * Fixed Disk FUNCE codes
250 #define CISTPL_IDE_INTERFACE 0x01
252 #define CISTPL_FUNCE_IDE_IFACE 0x01
253 #define CISTPL_FUNCE_IDE_MASTER 0x02
254 #define CISTPL_FUNCE_IDE_SLAVE 0x03
256 /* First feature byte */
257 #define CISTPL_IDE_SILICON 0x04
258 #define CISTPL_IDE_UNIQUE 0x08
259 #define CISTPL_IDE_DUAL 0x10
261 /* Second feature byte */
262 #define CISTPL_IDE_HAS_SLEEP 0x01
263 #define CISTPL_IDE_HAS_STANDBY 0x02
264 #define CISTPL_IDE_HAS_IDLE 0x04
265 #define CISTPL_IDE_LOW_POWER 0x08
266 #define CISTPL_IDE_REG_INHIBIT 0x10
267 #define CISTPL_IDE_HAS_INDEX 0x20
268 #define CISTPL_IDE_IOIS16 0x40
273 extern u_int *pcmcia_pgcrx[];
274 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
277 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
278 extern int check_ide_device(int slot);
281 #endif /* _PCMCIA_H */