2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
15 * Allow configuration to select PCMCIA slot,
16 * or try to generate a useful default
18 #if defined(CONFIG_CMD_PCMCIA) || \
19 (defined(CONFIG_CMD_IDE) && \
20 (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) )
22 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
24 #if defined(CONFIG_TQM8xxL)
25 # define CONFIG_PCMCIA_SLOT_B /* The TQM8xxL use SLOT_B */
26 #elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
27 # define CONFIG_PCMCIA_SLOT_A
29 # error "PCMCIA Slot not configured"
32 #endif /* !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) */
34 /* Make sure exactly one slot is defined - we support only one for now */
35 #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B)
36 #error Neither CONFIG_PCMCIA_SLOT_A nor CONFIG_PCMCIA_SLOT_B configured
38 #if defined(CONFIG_PCMCIA_SLOT_A) && defined(CONFIG_PCMCIA_SLOT_B)
39 #error Both CONFIG_PCMCIA_SLOT_A and CONFIG_PCMCIA_SLOT_B configured
42 #ifndef PCMCIA_SOCKETS_NO
43 #define PCMCIA_SOCKETS_NO 1
45 #ifndef PCMCIA_MEM_WIN_NO
46 #define PCMCIA_MEM_WIN_NO 4
48 #define PCMCIA_IO_WIN_NO 2
50 /* define _slot_ to be able to optimize macros */
51 #ifdef CONFIG_PCMCIA_SLOT_A
53 # define PCMCIA_SLOT_MSG "slot A"
54 # define PCMCIA_SLOT_x PCMCIA_PSLOT_A
57 # define PCMCIA_SLOT_MSG "slot B"
58 # define PCMCIA_SLOT_x PCMCIA_PSLOT_B
62 * The TQM850L hardware has two pins swapped! Grrrrgh!
65 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXOE
66 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXRESET
68 #define __MY_PCMCIA_GCRX_CXRESET PCMCIA_GCRX_CXRESET
69 #define __MY_PCMCIA_GCRX_CXOE PCMCIA_GCRX_CXOE
73 * This structure is used to address each window in the PCMCIA controller.
75 * Keep in mind that we assume that pcmcia_win_t[n+1] is mapped directly
76 * after pcmcia_win_t[n]...
85 * Definitions for PCMCIA control registers to operate in IDE mode
87 * All timing related setup (PCMCIA_SHT, PCMCIA_SST, PCMCIA_SL)
88 * to be done later (depending on CPU clock)
92 * Base: 0xFE100000 CS1
98 #define CONFIG_SYS_PCMCIA_PBR0 0xFE100000
99 #define CONFIG_SYS_PCMCIA_POR0 ( PCMCIA_BSIZE_2 \
107 * Base: 0xFE100080 CS1
110 * Common Memory Space
113 #define CONFIG_SYS_PCMCIA_PBR1 0xFE100080
114 #define CONFIG_SYS_PCMCIA_POR1 ( PCMCIA_BSIZE_8 \
122 * Base: 0xFE100100 CS2
125 * Common Memory Space
128 #define CONFIG_SYS_PCMCIA_PBR2 0xFE100100
129 #define CONFIG_SYS_PCMCIA_POR2 ( PCMCIA_BSIZE_8 \
139 #define CONFIG_SYS_PCMCIA_PBR3 0
140 #define CONFIG_SYS_PCMCIA_POR3 0
143 * Base: 0xFE100C00 CS1
146 * Common Memory Space
149 #define CONFIG_SYS_PCMCIA_PBR4 0xFE100C00
150 #define CONFIG_SYS_PCMCIA_POR4 ( PCMCIA_BSIZE_2 \
158 * Base: 0xFE100C80 CS1
161 * Common Memory Space
164 #define CONFIG_SYS_PCMCIA_PBR5 0xFE100C80
165 #define CONFIG_SYS_PCMCIA_POR5 ( PCMCIA_BSIZE_8 \
173 * Base: 0xFE100D00 CS2
176 * Common Memory Space
179 #define CONFIG_SYS_PCMCIA_PBR6 0xFE100D00
180 #define CONFIG_SYS_PCMCIA_POR6 ( PCMCIA_BSIZE_8 \
190 #define CONFIG_SYS_PCMCIA_PBR7 0
191 #define CONFIG_SYS_PCMCIA_POR7 0
193 /**********************************************************************/
198 #define CISTPL_NULL 0x00
199 #define CISTPL_DEVICE 0x01
200 #define CISTPL_LONGLINK_CB 0x02
201 #define CISTPL_INDIRECT 0x03
202 #define CISTPL_CONFIG_CB 0x04
203 #define CISTPL_CFTABLE_ENTRY_CB 0x05
204 #define CISTPL_LONGLINK_MFC 0x06
205 #define CISTPL_BAR 0x07
206 #define CISTPL_PWR_MGMNT 0x08
207 #define CISTPL_EXTDEVICE 0x09
208 #define CISTPL_CHECKSUM 0x10
209 #define CISTPL_LONGLINK_A 0x11
210 #define CISTPL_LONGLINK_C 0x12
211 #define CISTPL_LINKTARGET 0x13
212 #define CISTPL_NO_LINK 0x14
213 #define CISTPL_VERS_1 0x15
214 #define CISTPL_ALTSTR 0x16
215 #define CISTPL_DEVICE_A 0x17
216 #define CISTPL_JEDEC_C 0x18
217 #define CISTPL_JEDEC_A 0x19
218 #define CISTPL_CONFIG 0x1a
219 #define CISTPL_CFTABLE_ENTRY 0x1b
220 #define CISTPL_DEVICE_OC 0x1c
221 #define CISTPL_DEVICE_OA 0x1d
222 #define CISTPL_DEVICE_GEO 0x1e
223 #define CISTPL_DEVICE_GEO_A 0x1f
224 #define CISTPL_MANFID 0x20
225 #define CISTPL_FUNCID 0x21
226 #define CISTPL_FUNCE 0x22
227 #define CISTPL_SWIL 0x23
228 #define CISTPL_END 0xff
231 * CIS Function ID codes
233 #define CISTPL_FUNCID_MULTI 0x00
234 #define CISTPL_FUNCID_MEMORY 0x01
235 #define CISTPL_FUNCID_SERIAL 0x02
236 #define CISTPL_FUNCID_PARALLEL 0x03
237 #define CISTPL_FUNCID_FIXED 0x04
238 #define CISTPL_FUNCID_VIDEO 0x05
239 #define CISTPL_FUNCID_NETWORK 0x06
240 #define CISTPL_FUNCID_AIMS 0x07
241 #define CISTPL_FUNCID_SCSI 0x08
244 * Fixed Disk FUNCE codes
246 #define CISTPL_IDE_INTERFACE 0x01
248 #define CISTPL_FUNCE_IDE_IFACE 0x01
249 #define CISTPL_FUNCE_IDE_MASTER 0x02
250 #define CISTPL_FUNCE_IDE_SLAVE 0x03
252 /* First feature byte */
253 #define CISTPL_IDE_SILICON 0x04
254 #define CISTPL_IDE_UNIQUE 0x08
255 #define CISTPL_IDE_DUAL 0x10
257 /* Second feature byte */
258 #define CISTPL_IDE_HAS_SLEEP 0x01
259 #define CISTPL_IDE_HAS_STANDBY 0x02
260 #define CISTPL_IDE_HAS_IDLE 0x04
261 #define CISTPL_IDE_LOW_POWER 0x08
262 #define CISTPL_IDE_REG_INHIBIT 0x10
263 #define CISTPL_IDE_HAS_INDEX 0x20
264 #define CISTPL_IDE_IOIS16 0x40
269 extern u_int *pcmcia_pgcrx[];
270 #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
273 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
274 extern int check_ide_device(int slot);
277 #endif /* _PCMCIA_H */