1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
13 #define PCI_CFG_SPACE_SIZE 256
14 #define PCI_CFG_SPACE_EXP_SIZE 4096
17 * Under PCI, each device has 256 bytes of configuration address space,
18 * of which the first 64 bytes are standardized as follows:
20 #define PCI_STD_HEADER_SIZEOF 64
21 #define PCI_VENDOR_ID 0x00 /* 16 bits */
22 #define PCI_DEVICE_ID 0x02 /* 16 bits */
23 #define PCI_COMMAND 0x04 /* 16 bits */
24 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
25 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
26 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
27 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
28 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
29 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
30 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
31 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
32 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
33 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
35 #define PCI_STATUS 0x06 /* 16 bits */
36 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
37 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
38 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
39 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
40 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
41 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
42 #define PCI_STATUS_DEVSEL_FAST 0x000
43 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
44 #define PCI_STATUS_DEVSEL_SLOW 0x400
45 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
46 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
47 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
48 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
49 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
51 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
53 #define PCI_REVISION_ID 0x08 /* Revision ID */
54 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
55 #define PCI_CLASS_DEVICE 0x0a /* Device class */
56 #define PCI_CLASS_CODE 0x0b /* Device class code */
57 #define PCI_CLASS_CODE_TOO_OLD 0x00
58 #define PCI_CLASS_CODE_STORAGE 0x01
59 #define PCI_CLASS_CODE_NETWORK 0x02
60 #define PCI_CLASS_CODE_DISPLAY 0x03
61 #define PCI_CLASS_CODE_MULTIMEDIA 0x04
62 #define PCI_CLASS_CODE_MEMORY 0x05
63 #define PCI_CLASS_CODE_BRIDGE 0x06
64 #define PCI_CLASS_CODE_COMM 0x07
65 #define PCI_CLASS_CODE_PERIPHERAL 0x08
66 #define PCI_CLASS_CODE_INPUT 0x09
67 #define PCI_CLASS_CODE_DOCKING 0x0A
68 #define PCI_CLASS_CODE_PROCESSOR 0x0B
69 #define PCI_CLASS_CODE_SERIAL 0x0C
70 #define PCI_CLASS_CODE_WIRELESS 0x0D
71 #define PCI_CLASS_CODE_I2O 0x0E
72 #define PCI_CLASS_CODE_SATELLITE 0x0F
73 #define PCI_CLASS_CODE_CRYPTO 0x10
74 #define PCI_CLASS_CODE_DATA 0x11
75 /* Base Class 0x12 - 0xFE is reserved */
76 #define PCI_CLASS_CODE_OTHER 0xFF
78 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
79 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
80 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
81 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
82 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
83 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
84 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
85 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
86 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
87 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
88 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
89 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
90 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
91 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
92 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
93 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
94 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
95 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
96 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
97 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
98 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
99 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
100 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
101 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
105 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
106 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
107 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
108 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
109 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
110 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
111 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
112 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
113 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
114 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
115 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
116 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
117 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
118 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
119 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
120 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
121 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
122 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
123 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
124 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
125 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
126 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
127 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
134 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
135 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
136 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
137 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
138 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
139 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
140 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
141 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
142 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
143 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
144 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
145 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
146 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
147 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
148 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
149 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
150 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
151 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
152 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
153 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
154 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
155 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
156 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
157 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
158 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
159 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
160 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
161 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
162 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
163 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
164 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
165 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
166 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
167 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
168 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
169 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
170 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
171 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
172 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
173 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
174 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
175 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
176 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
177 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
178 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
179 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
180 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
182 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
183 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
184 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
185 #define PCI_HEADER_TYPE_NORMAL 0
186 #define PCI_HEADER_TYPE_BRIDGE 1
187 #define PCI_HEADER_TYPE_CARDBUS 2
189 #define PCI_BIST 0x0f /* 8 bits */
190 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
191 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
192 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
195 * Base addresses specify locations in memory or I/O space.
196 * Decoded size can be determined by writing a value of
197 * 0xffffffff to the register, and reading it back. Only
198 * 1 bits are decoded.
200 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
201 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
202 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
203 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
204 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
205 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
206 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
207 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
208 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
209 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
210 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
211 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
212 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
213 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
214 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
215 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
216 /* bit 1 is reserved if address_space = 1 */
218 /* Header type 0 (normal devices) */
219 #define PCI_CARDBUS_CIS 0x28
220 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
221 #define PCI_SUBSYSTEM_ID 0x2e
222 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
223 #define PCI_ROM_ADDRESS_ENABLE 0x01
224 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
226 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
228 /* 0x35-0x3b are reserved */
229 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
230 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
231 #define PCI_MIN_GNT 0x3e /* 8 bits */
232 #define PCI_MAX_LAT 0x3f /* 8 bits */
234 #define PCI_INTERRUPT_LINE_DISABLE 0xff
236 /* Header type 1 (PCI-to-PCI bridges) */
237 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
238 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
239 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
240 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
241 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
242 #define PCI_IO_LIMIT 0x1d
243 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
244 #define PCI_IO_RANGE_TYPE_16 0x00
245 #define PCI_IO_RANGE_TYPE_32 0x01
246 #define PCI_IO_RANGE_MASK ~0x0f
247 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
248 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
249 #define PCI_MEMORY_LIMIT 0x22
250 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
251 #define PCI_MEMORY_RANGE_MASK ~0x0f
252 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
253 #define PCI_PREF_MEMORY_LIMIT 0x26
254 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
255 #define PCI_PREF_RANGE_TYPE_32 0x00
256 #define PCI_PREF_RANGE_TYPE_64 0x01
257 #define PCI_PREF_RANGE_MASK ~0x0f
258 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
259 #define PCI_PREF_LIMIT_UPPER32 0x2c
260 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
261 #define PCI_IO_LIMIT_UPPER16 0x32
262 /* 0x34 same as for htype 0 */
263 /* 0x35-0x3b is reserved */
264 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
265 /* 0x3c-0x3d are same as for htype 0 */
266 #define PCI_BRIDGE_CONTROL 0x3e
267 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
268 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
269 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
270 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
271 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
272 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
273 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
275 /* Header type 2 (CardBus bridges) */
276 #define PCI_CB_CAPABILITY_LIST 0x14
278 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
279 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
280 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
281 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
282 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
283 #define PCI_CB_MEMORY_BASE_0 0x1c
284 #define PCI_CB_MEMORY_LIMIT_0 0x20
285 #define PCI_CB_MEMORY_BASE_1 0x24
286 #define PCI_CB_MEMORY_LIMIT_1 0x28
287 #define PCI_CB_IO_BASE_0 0x2c
288 #define PCI_CB_IO_BASE_0_HI 0x2e
289 #define PCI_CB_IO_LIMIT_0 0x30
290 #define PCI_CB_IO_LIMIT_0_HI 0x32
291 #define PCI_CB_IO_BASE_1 0x34
292 #define PCI_CB_IO_BASE_1_HI 0x36
293 #define PCI_CB_IO_LIMIT_1 0x38
294 #define PCI_CB_IO_LIMIT_1_HI 0x3a
295 #define PCI_CB_IO_RANGE_MASK ~0x03
296 /* 0x3c-0x3d are same as for htype 0 */
297 #define PCI_CB_BRIDGE_CONTROL 0x3e
298 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
299 #define PCI_CB_BRIDGE_CTL_SERR 0x02
300 #define PCI_CB_BRIDGE_CTL_ISA 0x04
301 #define PCI_CB_BRIDGE_CTL_VGA 0x08
302 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
303 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
304 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
305 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
306 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
307 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
308 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
309 #define PCI_CB_SUBSYSTEM_ID 0x42
310 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
311 /* 0x48-0x7f reserved */
313 /* Capability lists */
315 #define PCI_CAP_LIST_ID 0 /* Capability ID */
316 #define PCI_CAP_ID_PM 0x01 /* Power Management */
317 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
318 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
319 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
320 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
321 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
322 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
323 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */
324 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
325 #define PCI_CAP_ID_DBG 0x0A /* Debug port */
326 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
327 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
328 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
329 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
330 #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
331 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
332 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
333 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
334 #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
335 #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
336 #define PCI_CAP_ID_MAX PCI_CAP_ID_EA
337 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
338 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
339 #define PCI_CAP_SIZEOF 4
341 /* Power Management Registers */
343 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
344 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
345 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
346 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
347 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
348 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
349 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
350 #define PCI_PM_CTRL 4 /* PM control and status register */
351 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
352 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
353 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
354 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
355 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
356 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
357 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
358 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
359 #define PCI_PM_DATA_REGISTER 7 /* (??) */
360 #define PCI_PM_SIZEOF 8
364 #define PCI_AGP_VERSION 2 /* BCD version number */
365 #define PCI_AGP_RFU 3 /* Rest of capability flags */
366 #define PCI_AGP_STATUS 4 /* Status register */
367 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
368 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
369 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
370 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
371 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
372 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
373 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
374 #define PCI_AGP_COMMAND 8 /* Control register */
375 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
376 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
377 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
378 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
379 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
380 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
381 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
382 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
383 #define PCI_AGP_SIZEOF 12
385 /* PCI-X registers */
387 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
388 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
389 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
390 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
391 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
394 /* Slot Identification */
396 #define PCI_SID_ESR 2 /* Expansion Slot Register */
397 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
398 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
399 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
401 /* Message Signalled Interrupts registers */
403 #define PCI_MSI_FLAGS 2 /* Various flags */
404 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
405 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
406 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
407 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
408 #define PCI_MSI_RFU 3 /* Rest of capability flags */
409 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
410 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
411 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
412 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
414 #define PCI_MAX_PCI_DEVICES 32
415 #define PCI_MAX_PCI_FUNCTIONS 8
417 #define PCI_FIND_CAP_TTL 0x48
418 #define CAP_START_POS 0x40
420 /* Extended Capabilities (PCI-X 2.0 and Express) */
421 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
422 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
423 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
425 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
426 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
427 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
428 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
429 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
430 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
431 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
432 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
433 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
434 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
435 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
436 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
437 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
438 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
439 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
440 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
441 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
442 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
443 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
444 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
445 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
446 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
447 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
448 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
449 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
450 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
451 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
452 #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
453 #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
454 #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
455 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
457 /* Include the ID list */
463 #ifdef CONFIG_SYS_PCI_64BIT
464 typedef u64 pci_addr_t;
465 typedef u64 pci_size_t;
467 typedef u32 pci_addr_t;
468 typedef u32 pci_size_t;
472 pci_addr_t bus_start; /* Start on the bus */
473 phys_addr_t phys_start; /* Start in physical address space */
474 pci_size_t size; /* Size */
475 unsigned long flags; /* Resource flags */
477 pci_addr_t bus_lower;
480 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
481 #define PCI_REGION_IO 0x00000001 /* PCI IO space */
482 #define PCI_REGION_TYPE 0x00000001
483 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
485 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
486 #define PCI_REGION_RO 0x00000200 /* Read-only memory */
488 static inline void pci_set_region(struct pci_region *reg,
489 pci_addr_t bus_start,
490 phys_addr_t phys_start,
492 unsigned long flags) {
493 reg->bus_start = bus_start;
494 reg->phys_start = phys_start;
499 typedef int pci_dev_t;
501 #define PCI_BUS(d) (((d) >> 16) & 0xff)
504 * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot
505 * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.
506 * Please see the Linux header include/uapi/linux/pci.h for more details.
507 * This is relevant for the following macros:
508 * PCI_DEV, PCI_FUNC, PCI_DEVFN
509 * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with
510 * the remark from above (input d in bits 15-8 instead of 7-0.
512 #define PCI_DEV(d) (((d) >> 11) & 0x1f)
513 #define PCI_FUNC(d) (((d) >> 8) & 0x7)
514 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
516 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
517 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
518 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
519 #define PCI_VENDEV(v, d) (((v) << 16) | (d))
520 #define PCI_ANY_ID (~0)
522 struct pci_device_id {
523 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
524 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
525 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
526 unsigned long driver_data; /* Data private to the driver */
529 struct pci_controller;
531 struct pci_config_table {
532 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
533 unsigned int class; /* Class ID, or PCI_ANY_ID */
534 unsigned int bus; /* Bus number, or PCI_ANY_ID */
535 unsigned int dev; /* Device number, or PCI_ANY_ID */
536 unsigned int func; /* Function number, or PCI_ANY_ID */
538 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
539 struct pci_config_table *);
540 unsigned long priv[3];
543 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
544 struct pci_config_table *);
545 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
546 struct pci_config_table *);
548 #ifdef CONFIG_NR_DRAM_BANKS
549 #define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7)
551 #define MAX_PCI_REGIONS 7
554 #define INDIRECT_TYPE_NO_PCIE_LINK 1
557 * Structure of a PCI controller (host bridge)
559 * With driver model this is dev_get_uclass_priv(bus)
561 struct pci_controller {
564 struct udevice *ctlr;
566 struct pci_controller *next;
572 volatile unsigned int *cfg_addr;
573 volatile unsigned char *cfg_data;
578 * TODO(sjg@chromium.org): With driver model we use struct
579 * pci_controller for both the controller and any bridge devices
580 * attached to it. But there is only one region list and it is in the
581 * top-level controller.
583 * This could be changed so that struct pci_controller is only used
584 * for PCI controllers and a separate UCLASS (or perhaps
585 * UCLASS_PCI_GENERIC) is used for bridges.
587 struct pci_region regions[MAX_PCI_REGIONS];
590 struct pci_config_table *config_table;
592 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
593 #ifndef CONFIG_DM_PCI
594 /* Low-level architecture-dependent routines */
595 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
596 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
597 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
598 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
599 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
600 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
603 /* Used by auto config */
604 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
606 #ifndef CONFIG_DM_PCI
613 #ifndef CONFIG_DM_PCI
614 static inline void pci_set_ops(struct pci_controller *hose,
615 int (*read_byte)(struct pci_controller*,
616 pci_dev_t, int where, u8 *),
617 int (*read_word)(struct pci_controller*,
618 pci_dev_t, int where, u16 *),
619 int (*read_dword)(struct pci_controller*,
620 pci_dev_t, int where, u32 *),
621 int (*write_byte)(struct pci_controller*,
622 pci_dev_t, int where, u8),
623 int (*write_word)(struct pci_controller*,
624 pci_dev_t, int where, u16),
625 int (*write_dword)(struct pci_controller*,
626 pci_dev_t, int where, u32)) {
627 hose->read_byte = read_byte;
628 hose->read_word = read_word;
629 hose->read_dword = read_dword;
630 hose->write_byte = write_byte;
631 hose->write_word = write_word;
632 hose->write_dword = write_dword;
636 #ifdef CONFIG_PCI_INDIRECT_BRIDGE
637 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
640 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
641 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
642 pci_addr_t addr, unsigned long flags);
643 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
644 phys_addr_t addr, unsigned long flags);
646 #define pci_phys_to_bus(dev, addr, flags) \
647 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
648 #define pci_bus_to_phys(dev, addr, flags) \
649 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
651 #define pci_virt_to_bus(dev, addr, flags) \
652 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
653 (virt_to_phys(addr)), (flags))
654 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
655 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
659 #define pci_phys_to_mem(dev, addr) \
660 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
661 #define pci_mem_to_phys(dev, addr) \
662 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
663 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
664 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
666 #define pci_virt_to_mem(dev, addr) \
667 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
668 #define pci_mem_to_virt(dev, addr, len, map_flags) \
669 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
670 #define pci_virt_to_io(dev, addr) \
671 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
672 #define pci_io_to_virt(dev, addr, len, map_flags) \
673 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
675 /* For driver model these are defined in macros in pci_compat.c */
676 extern int pci_hose_read_config_byte(struct pci_controller *hose,
677 pci_dev_t dev, int where, u8 *val);
678 extern int pci_hose_read_config_word(struct pci_controller *hose,
679 pci_dev_t dev, int where, u16 *val);
680 extern int pci_hose_read_config_dword(struct pci_controller *hose,
681 pci_dev_t dev, int where, u32 *val);
682 extern int pci_hose_write_config_byte(struct pci_controller *hose,
683 pci_dev_t dev, int where, u8 val);
684 extern int pci_hose_write_config_word(struct pci_controller *hose,
685 pci_dev_t dev, int where, u16 val);
686 extern int pci_hose_write_config_dword(struct pci_controller *hose,
687 pci_dev_t dev, int where, u32 val);
690 #ifndef CONFIG_DM_PCI
691 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
692 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
693 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
694 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
695 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
696 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
699 void pciauto_region_init(struct pci_region *res);
700 void pciauto_region_align(struct pci_region *res, pci_size_t size);
701 void pciauto_config_init(struct pci_controller *hose);
704 * pciauto_region_allocate() - Allocate resources from a PCI resource region
706 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
707 * false, the result will be guaranteed to fit in 32 bits.
709 * @res: PCI region to allocate from
710 * @size: Amount of bytes to allocate
711 * @bar: Returns the PCI bus address of the allocated resource
712 * @supports_64bit: Whether to allow allocations above the 32-bit boundary
713 * @return 0 if successful, -1 on failure
715 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
716 pci_addr_t *bar, bool supports_64bit);
718 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
719 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
720 pci_dev_t dev, int where, u8 *val);
721 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
722 pci_dev_t dev, int where, u16 *val);
723 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
724 pci_dev_t dev, int where, u8 val);
725 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
726 pci_dev_t dev, int where, u16 val);
728 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
729 extern void pci_register_hose(struct pci_controller* hose);
730 extern struct pci_controller* pci_bus_to_hose(int bus);
731 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
732 extern struct pci_controller *pci_get_hose_head(void);
734 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
735 extern int pci_hose_scan(struct pci_controller *hose);
736 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
738 extern void pciauto_setup_device(struct pci_controller *hose,
739 pci_dev_t dev, int bars_num,
740 struct pci_region *mem,
741 struct pci_region *prefetch,
742 struct pci_region *io);
743 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
744 pci_dev_t dev, int sub_bus);
745 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
746 pci_dev_t dev, int sub_bus);
747 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
749 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
750 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
751 pci_dev_t pci_find_class(unsigned int find_class, int index);
753 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
755 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
757 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
760 int pci_find_next_ext_capability(struct pci_controller *hose,
761 pci_dev_t dev, int start, int cap);
762 int pci_hose_find_ext_capability(struct pci_controller *hose,
763 pci_dev_t dev, int cap);
765 #ifdef CONFIG_PCI_FIXUP_DEV
766 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
767 unsigned short vendor,
768 unsigned short device,
769 unsigned short class);
771 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
773 const char * pci_class_str(u8 class);
774 int pci_last_busno(void);
776 #ifdef CONFIG_MPC85xx
777 extern void pci_mpc85xx_init (struct pci_controller *hose);
780 #ifdef CONFIG_PCIE_IMX
781 extern void imx_pcie_remove(void);
784 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
786 * pci_write_bar32() - Write the address of a BAR including control bits
788 * This writes a raw address (with control bits) to a bar. This can be used
789 * with devices which require hard-coded addresses, not part of the normal
790 * PCI enumeration process.
792 * @hose: PCI hose to use
793 * @dev: PCI device to update
794 * @barnum: BAR number (0-5)
795 * @addr: BAR address with control bits
797 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
801 * pci_read_bar32() - read the address of a bar
803 * @hose: PCI hose to use
804 * @dev: PCI device to inspect
805 * @barnum: BAR number (0-5)
806 * @return address of the bar, masking out any control bits
808 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
811 * pci_hose_find_devices() - Find devices by vendor/device ID
813 * @hose: PCI hose to search
814 * @busnum: Bus number to search
815 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
816 * @indexp: Pointer to device index to find. To find the first matching
817 * device, pass 0; to find the second, pass 1, etc. This
818 * parameter is decremented for each non-matching device so
819 * can be called repeatedly.
821 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
822 struct pci_device_id *ids, int *indexp);
823 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
825 /* Access sizes for PCI reads and writes */
836 * struct pci_child_platdata - information stored about each PCI device
838 * Every device on a PCI bus has this per-child data.
840 * It can be accessed using dev_get_parent_platdata(dev) if dev->parent is a
841 * PCI bus (i.e. UCLASS_PCI)
843 * @devfn: Encoded device and function index - see PCI_DEVFN()
844 * @vendor: PCI vendor ID (see pci_ids.h)
845 * @device: PCI device ID (see pci_ids.h)
846 * @class: PCI class, 3 bytes: (base, sub, prog-if)
848 struct pci_child_platdata {
850 unsigned short vendor;
851 unsigned short device;
855 /* PCI bus operations */
858 * read_config() - Read a PCI configuration value
860 * PCI buses must support reading and writing configuration values
861 * so that the bus can be scanned and its devices configured.
863 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
864 * If bridges exist it is possible to use the top-level bus to
865 * access a sub-bus. In that case @bus will be the top-level bus
866 * and PCI_BUS(bdf) will be a different (higher) value
868 * @bus: Bus to read from
869 * @bdf: Bus, device and function to read
870 * @offset: Byte offset within the device's configuration space
871 * @valuep: Place to put the returned value
873 * @return 0 if OK, -ve on error
875 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
876 ulong *valuep, enum pci_size_t size);
878 * write_config() - Write a PCI configuration value
880 * @bus: Bus to write to
881 * @bdf: Bus, device and function to write
882 * @offset: Byte offset within the device's configuration space
883 * @value: Value to write
885 * @return 0 if OK, -ve on error
887 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
888 ulong value, enum pci_size_t size);
891 /* Get access to a PCI bus' operations */
892 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
895 * dm_pci_get_bdf() - Get the BDF value for a device
897 * @dev: Device to check
898 * @return bus/device/function value (see PCI_BDF())
900 pci_dev_t dm_pci_get_bdf(struct udevice *dev);
903 * pci_bind_bus_devices() - scan a PCI bus and bind devices
905 * Scan a PCI bus looking for devices. Bind each one that is found. If
906 * devices are already bound that match the scanned devices, just update the
907 * child data so that the device can be used correctly (this happens when
908 * the device tree describes devices we expect to see on the bus).
910 * Devices that are bound in this way will use a generic PCI driver which
911 * does nothing. The device can still be accessed but will not provide any
914 * @bus: Bus containing devices to bind
915 * @return 0 if OK, -ve on error
917 int pci_bind_bus_devices(struct udevice *bus);
920 * pci_auto_config_devices() - configure bus devices ready for use
922 * This works through all devices on a bus by scanning the driver model
923 * data structures (normally these have been set up by pci_bind_bus_devices()
926 * Space is allocated for each PCI base address register (BAR) so that the
927 * devices are mapped into memory and I/O space ready for use.
929 * @bus: Bus containing devices to bind
930 * @return 0 if OK, -ve on error
932 int pci_auto_config_devices(struct udevice *bus);
935 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
937 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
938 * @devp: Returns the device for this address, if found
939 * @return 0 if OK, -ENODEV if not found
941 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
944 * pci_bus_find_devfn() - Find a device on a bus
946 * @find_devfn: PCI device address (device and function only)
947 * @devp: Returns the device for this address, if found
948 * @return 0 if OK, -ENODEV if not found
950 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
951 struct udevice **devp);
954 * pci_find_first_device() - return the first available PCI device
956 * This function and pci_find_first_device() allow iteration through all
957 * available PCI devices on all buses. Assuming there are any, this will
958 * return the first one.
960 * @devp: Set to the first available device, or NULL if no more are left
962 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
964 int pci_find_first_device(struct udevice **devp);
967 * pci_find_next_device() - return the next available PCI device
969 * Finds the next available PCI device after the one supplied, or sets @devp
970 * to NULL if there are no more.
972 * @devp: On entry, the last device returned. Set to the next available
973 * device, or NULL if no more are left or we got an error
974 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
976 int pci_find_next_device(struct udevice **devp);
979 * pci_get_ff() - Returns a mask for the given access size
982 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
985 int pci_get_ff(enum pci_size_t size);
988 * pci_bus_find_devices () - Find devices on a bus
990 * @bus: Bus to search
991 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
992 * @indexp: Pointer to device index to find. To find the first matching
993 * device, pass 0; to find the second, pass 1, etc. This
994 * parameter is decremented for each non-matching device so
995 * can be called repeatedly.
996 * @devp: Returns matching device if found
997 * @return 0 if found, -ENODEV if not
999 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
1000 int *indexp, struct udevice **devp);
1003 * pci_find_device_id() - Find a device on any bus
1005 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1006 * @index: Index number of device to find, 0 for the first match, 1 for
1008 * @devp: Returns matching device if found
1009 * @return 0 if found, -ENODEV if not
1011 int pci_find_device_id(struct pci_device_id *ids, int index,
1012 struct udevice **devp);
1015 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
1017 * This probes the given bus which causes it to be scanned for devices. The
1018 * devices will be bound but not probed.
1020 * @hose specifies the PCI hose that will be used for the scan. This is
1021 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
1022 * in @bdf, and is a subordinate bus reachable from @hose.
1024 * @hose: PCI hose to scan
1025 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
1026 * @return 0 if OK, -ve on error
1028 int dm_pci_hose_probe_bus(struct udevice *bus);
1031 * pci_bus_read_config() - Read a configuration value from a device
1033 * TODO(sjg@chromium.org): We should be able to pass just a device and have
1034 * it do the right thing. It would be good to have that function also.
1036 * @bus: Bus to read from
1037 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1038 * @offset: Register offset to read
1039 * @valuep: Place to put the returned value
1040 * @size: Access size
1041 * @return 0 if OK, -ve on error
1043 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
1044 unsigned long *valuep, enum pci_size_t size);
1047 * pci_bus_write_config() - Write a configuration value to a device
1049 * @bus: Bus to write from
1050 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1051 * @offset: Register offset to write
1052 * @value: Value to write
1053 * @size: Access size
1054 * @return 0 if OK, -ve on error
1056 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1057 unsigned long value, enum pci_size_t size);
1060 * pci_bus_clrset_config32() - Update a configuration value for a device
1062 * The register at @offset is updated to (oldvalue & ~clr) | set.
1064 * @bus: Bus to access
1065 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1066 * @offset: Register offset to update
1067 * @clr: Bits to clear
1069 * @return 0 if OK, -ve on error
1071 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1075 * Driver model PCI config access functions. Use these in preference to others
1076 * when you have a valid device
1078 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
1079 enum pci_size_t size);
1081 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
1082 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
1083 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
1085 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1086 enum pci_size_t size);
1088 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1089 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1090 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1093 * These permit convenient read/modify/write on PCI configuration. The
1094 * register is updated to (oldvalue & ~clr) | set.
1096 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1097 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1098 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
1101 * The following functions provide access to the above without needing the
1102 * size parameter. We are trying to encourage the use of the 8/16/32-style
1103 * functions, rather than byte/word/dword. But both are supported.
1105 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
1106 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1107 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1108 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1109 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1110 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
1113 * pci_generic_mmap_write_config() - Generic helper for writing to
1114 * memory-mapped PCI configuration space.
1115 * @bus: Pointer to the PCI bus
1116 * @addr_f: Callback for calculating the config space address
1117 * @bdf: Identifies the PCI device to access
1118 * @offset: The offset into the device's configuration space
1119 * @value: The value to write
1120 * @size: Indicates the size of access to perform
1122 * Write the value @value of size @size from offset @offset within the
1123 * configuration space of the device identified by the bus, device & function
1124 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
1125 * responsible for calculating the CPU address of the respective configuration
1128 * Return: 0 on success, else -EINVAL
1130 int pci_generic_mmap_write_config(
1131 struct udevice *bus,
1132 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1136 enum pci_size_t size);
1139 * pci_generic_mmap_read_config() - Generic helper for reading from
1140 * memory-mapped PCI configuration space.
1141 * @bus: Pointer to the PCI bus
1142 * @addr_f: Callback for calculating the config space address
1143 * @bdf: Identifies the PCI device to access
1144 * @offset: The offset into the device's configuration space
1145 * @valuep: A pointer at which to store the read value
1146 * @size: Indicates the size of access to perform
1148 * Read a value of size @size from offset @offset within the configuration
1149 * space of the device identified by the bus, device & function numbers in @bdf
1150 * on the PCI bus @bus. The callback function @addr_f is responsible for
1151 * calculating the CPU address of the respective configuration space offset.
1153 * Return: 0 on success, else -EINVAL
1155 int pci_generic_mmap_read_config(
1156 struct udevice *bus,
1157 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1161 enum pci_size_t size);
1163 #ifdef CONFIG_DM_PCI_COMPAT
1164 /* Compatibility with old naming */
1165 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1168 return pci_write_config32(pcidev, offset, value);
1171 /* Compatibility with old naming */
1172 static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1175 return pci_write_config16(pcidev, offset, value);
1178 /* Compatibility with old naming */
1179 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1182 return pci_write_config8(pcidev, offset, value);
1185 /* Compatibility with old naming */
1186 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1189 return pci_read_config32(pcidev, offset, valuep);
1192 /* Compatibility with old naming */
1193 static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1196 return pci_read_config16(pcidev, offset, valuep);
1199 /* Compatibility with old naming */
1200 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1203 return pci_read_config8(pcidev, offset, valuep);
1205 #endif /* CONFIG_DM_PCI_COMPAT */
1208 * dm_pciauto_config_device() - configure a device ready for use
1210 * Space is allocated for each PCI base address register (BAR) so that the
1211 * devices are mapped into memory and I/O space ready for use.
1213 * @dev: Device to configure
1214 * @return 0 if OK, -ve on error
1216 int dm_pciauto_config_device(struct udevice *dev);
1219 * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1221 * Some PCI buses must always perform 32-bit reads. The data must then be
1222 * shifted and masked to reflect the required access size and offset. This
1223 * function performs this transformation.
1225 * @value: Value to transform (32-bit value read from @offset & ~3)
1226 * @offset: Register offset that was read
1227 * @size: Required size of the result
1228 * @return the value that would have been obtained if the read had been
1229 * performed at the given offset with the correct size
1231 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1234 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1236 * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1237 * write the old 32-bit data must be read, updated with the required new data
1238 * and written back as a 32-bit value. This function performs the
1239 * transformation from the old value to the new value.
1241 * @value: Value to transform (32-bit value read from @offset & ~3)
1242 * @offset: Register offset that should be written
1243 * @size: Required size of the write
1244 * @return the value that should be written as a 32-bit access to @offset & ~3.
1246 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1247 enum pci_size_t size);
1250 * pci_get_controller() - obtain the controller to use for a bus
1252 * @dev: Device to check
1253 * @return pointer to the controller device for this bus
1255 struct udevice *pci_get_controller(struct udevice *dev);
1258 * pci_get_regions() - obtain pointers to all the region types
1260 * @dev: Device to check
1261 * @iop: Returns a pointer to the I/O region, or NULL if none
1262 * @memp: Returns a pointer to the memory region, or NULL if none
1263 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
1264 * @return the number of non-NULL regions returned, normally 3
1266 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1267 struct pci_region **memp, struct pci_region **prefp);
1270 * dm_pci_write_bar32() - Write the address of a BAR
1272 * This writes a raw address to a bar
1274 * @dev: PCI device to update
1275 * @barnum: BAR number (0-5)
1276 * @addr: BAR address
1278 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1281 * dm_pci_read_bar32() - read a base address register from a device
1283 * @dev: Device to check
1284 * @barnum: Bar number to read (numbered from 0)
1285 * @return: value of BAR
1287 u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
1290 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
1292 * @dev: Device containing the PCI address
1293 * @addr: PCI address to convert
1294 * @flags: Flags for the region type (PCI_REGION_...)
1295 * @return physical address corresponding to that PCI bus address
1297 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1298 unsigned long flags);
1301 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1303 * @dev: Device containing the bus address
1304 * @addr: Physical address to convert
1305 * @flags: Flags for the region type (PCI_REGION_...)
1306 * @return PCI bus address corresponding to that physical address
1308 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1309 unsigned long flags);
1312 * dm_pci_map_bar() - get a virtual address associated with a BAR region
1314 * Looks up a base address register and finds the physical memory address
1315 * that corresponds to it
1317 * @dev: Device to check
1318 * @bar: Bar number to read (numbered from 0)
1319 * @flags: Flags for the region type (PCI_REGION_...)
1320 * @return: pointer to the virtual address to use
1322 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
1325 * dm_pci_find_next_capability() - find a capability starting from an offset
1327 * Tell if a device supports a given PCI capability. Returns the
1328 * address of the requested capability structure within the device's
1329 * PCI configuration space or 0 in case the device does not support it.
1331 * Possible values for @cap:
1333 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1334 * %PCI_CAP_ID_PCIX PCI-X
1335 * %PCI_CAP_ID_EXP PCI Express
1336 * %PCI_CAP_ID_MSIX MSI-X
1338 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1340 * @dev: PCI device to query
1341 * @start: offset to start from
1342 * @cap: capability code
1343 * @return: capability address or 0 if not supported
1345 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
1348 * dm_pci_find_capability() - find a capability
1350 * Tell if a device supports a given PCI capability. Returns the
1351 * address of the requested capability structure within the device's
1352 * PCI configuration space or 0 in case the device does not support it.
1354 * Possible values for @cap:
1356 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1357 * %PCI_CAP_ID_PCIX PCI-X
1358 * %PCI_CAP_ID_EXP PCI Express
1359 * %PCI_CAP_ID_MSIX MSI-X
1361 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1363 * @dev: PCI device to query
1364 * @cap: capability code
1365 * @return: capability address or 0 if not supported
1367 int dm_pci_find_capability(struct udevice *dev, int cap);
1370 * dm_pci_find_next_ext_capability() - find an extended capability
1371 * starting from an offset
1373 * Tell if a device supports a given PCI express extended capability.
1374 * Returns the address of the requested extended capability structure
1375 * within the device's PCI configuration space or 0 in case the device
1376 * does not support it.
1378 * Possible values for @cap:
1380 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1381 * %PCI_EXT_CAP_ID_VC Virtual Channel
1382 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1383 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1385 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1387 * @dev: PCI device to query
1388 * @start: offset to start from
1389 * @cap: extended capability code
1390 * @return: extended capability address or 0 if not supported
1392 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
1395 * dm_pci_find_ext_capability() - find an extended capability
1397 * Tell if a device supports a given PCI express extended capability.
1398 * Returns the address of the requested extended capability structure
1399 * within the device's PCI configuration space or 0 in case the device
1400 * does not support it.
1402 * Possible values for @cap:
1404 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1405 * %PCI_EXT_CAP_ID_VC Virtual Channel
1406 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1407 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1409 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1411 * @dev: PCI device to query
1412 * @cap: extended capability code
1413 * @return: extended capability address or 0 if not supported
1415 int dm_pci_find_ext_capability(struct udevice *dev, int cap);
1417 #define dm_pci_virt_to_bus(dev, addr, flags) \
1418 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1419 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1420 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1423 #define dm_pci_phys_to_mem(dev, addr) \
1424 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1425 #define dm_pci_mem_to_phys(dev, addr) \
1426 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1427 #define dm_pci_phys_to_io(dev, addr) \
1428 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1429 #define dm_pci_io_to_phys(dev, addr) \
1430 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1432 #define dm_pci_virt_to_mem(dev, addr) \
1433 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1434 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1435 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1436 #define dm_pci_virt_to_io(dev, addr) \
1437 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
1438 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
1439 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
1442 * dm_pci_find_device() - find a device by vendor/device ID
1444 * @vendor: Vendor ID
1445 * @device: Device ID
1446 * @index: 0 to find the first match, 1 for second, etc.
1447 * @devp: Returns pointer to the device, if found
1448 * @return 0 if found, -ve on error
1450 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1451 struct udevice **devp);
1454 * dm_pci_find_class() - find a device by class
1456 * @find_class: 3-byte (24-bit) class value to find
1457 * @index: 0 to find the first match, 1 for second, etc.
1458 * @devp: Returns pointer to the device, if found
1459 * @return 0 if found, -ve on error
1461 int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1464 * struct dm_pci_emul_ops - PCI device emulator operations
1466 struct dm_pci_emul_ops {
1468 * get_devfn(): Check which device and function this emulators
1470 * @dev: device to check
1471 * @return the device and function this emulates, or -ve on error
1473 int (*get_devfn)(struct udevice *dev);
1475 * read_config() - Read a PCI configuration value
1477 * @dev: Emulated device to read from
1478 * @offset: Byte offset within the device's configuration space
1479 * @valuep: Place to put the returned value
1480 * @size: Access size
1481 * @return 0 if OK, -ve on error
1483 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
1484 enum pci_size_t size);
1486 * write_config() - Write a PCI configuration value
1488 * @dev: Emulated device to write to
1489 * @offset: Byte offset within the device's configuration space
1490 * @value: Value to write
1491 * @size: Access size
1492 * @return 0 if OK, -ve on error
1494 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1495 enum pci_size_t size);
1497 * read_io() - Read a PCI I/O value
1499 * @dev: Emulated device to read from
1500 * @addr: I/O address to read
1501 * @valuep: Place to put the returned value
1502 * @size: Access size
1503 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1504 * other -ve value on error
1506 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1507 enum pci_size_t size);
1509 * write_io() - Write a PCI I/O value
1511 * @dev: Emulated device to write from
1512 * @addr: I/O address to write
1513 * @value: Value to write
1514 * @size: Access size
1515 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1516 * other -ve value on error
1518 int (*write_io)(struct udevice *dev, unsigned int addr,
1519 ulong value, enum pci_size_t size);
1521 * map_physmem() - Map a device into sandbox memory
1523 * @dev: Emulated device to map
1524 * @addr: Memory address, normally corresponding to a PCI BAR.
1525 * The device should have been configured to have a BAR
1527 * @lenp: On entry, the size of the area to map, On exit it is
1528 * updated to the size actually mapped, which may be less
1529 * if the device has less space
1530 * @ptrp: Returns a pointer to the mapped address. The device's
1531 * space can be accessed as @lenp bytes starting here
1532 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1533 * other -ve value on error
1535 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1536 unsigned long *lenp, void **ptrp);
1538 * unmap_physmem() - undo a memory mapping
1540 * This must be called after map_physmem() to undo the mapping.
1541 * Some devices can use this to check what has been written into
1542 * their mapped memory and perform an operations they require on it.
1543 * In this way, map/unmap can be used as a sort of handshake between
1544 * the emulated device and its users.
1546 * @dev: Emuated device to unmap
1547 * @vaddr: Mapped memory address, as passed to map_physmem()
1548 * @len: Size of area mapped, as returned by map_physmem()
1549 * @return 0 if OK, -ve on error
1551 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1555 /* Get access to a PCI device emulator's operations */
1556 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1559 * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1561 * Searches for a suitable emulator for the given PCI bus device
1563 * @bus: PCI bus to search
1564 * @find_devfn: PCI device and function address (PCI_DEVFN())
1565 * @containerp: Returns container device if found
1566 * @emulp: Returns emulated device if found
1567 * @return 0 if found, -ENODEV if not found
1569 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
1570 struct udevice **containerp, struct udevice **emulp);
1573 * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device
1575 * Get devfn from fdt_pci_addr of the specifified device
1578 * @return devfn in bits 15...8 if found, -ENODEV if not found
1580 int pci_get_devfn(struct udevice *dev);
1582 #endif /* CONFIG_DM_PCI */
1585 * PCI_DEVICE - macro used to describe a specific pci device
1586 * @vend: the 16 bit PCI Vendor ID
1587 * @dev: the 16 bit PCI Device ID
1589 * This macro is used to create a struct pci_device_id that matches a
1590 * specific device. The subvendor and subdevice fields will be set to
1593 #define PCI_DEVICE(vend, dev) \
1594 .vendor = (vend), .device = (dev), \
1595 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1598 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1599 * @vend: the 16 bit PCI Vendor ID
1600 * @dev: the 16 bit PCI Device ID
1601 * @subvend: the 16 bit PCI Subvendor ID
1602 * @subdev: the 16 bit PCI Subdevice ID
1604 * This macro is used to create a struct pci_device_id that matches a
1605 * specific device with subsystem information.
1607 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1608 .vendor = (vend), .device = (dev), \
1609 .subvendor = (subvend), .subdevice = (subdev)
1612 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1613 * @dev_class: the class, subclass, prog-if triple for this device
1614 * @dev_class_mask: the class mask for this device
1616 * This macro is used to create a struct pci_device_id that matches a
1617 * specific PCI class. The vendor, device, subvendor, and subdevice
1618 * fields will be set to PCI_ANY_ID.
1620 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1621 .class = (dev_class), .class_mask = (dev_class_mask), \
1622 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1623 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1626 * PCI_VDEVICE - macro used to describe a specific pci device in short form
1627 * @vend: the vendor name
1628 * @dev: the 16 bit PCI Device ID
1630 * This macro is used to create a struct pci_device_id that matches a
1631 * specific PCI device. The subvendor, and subdevice fields will be set
1632 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1636 #define PCI_VDEVICE(vend, dev) \
1637 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1638 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1641 * struct pci_driver_entry - Matches a driver to its pci_device_id list
1642 * @driver: Driver to use
1643 * @match: List of match records for this driver, terminated by {}
1645 struct pci_driver_entry {
1646 struct driver *driver;
1647 const struct pci_device_id *match;
1650 #define U_BOOT_PCI_DEVICE(__name, __match) \
1651 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1652 .driver = llsym(struct driver, __name, driver), \
1656 #endif /* __ASSEMBLY__ */