1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
13 #define PCI_CFG_SPACE_SIZE 256
14 #define PCI_CFG_SPACE_EXP_SIZE 4096
17 * Under PCI, each device has 256 bytes of configuration address space,
18 * of which the first 64 bytes are standardized as follows:
20 #define PCI_VENDOR_ID 0x00 /* 16 bits */
21 #define PCI_DEVICE_ID 0x02 /* 16 bits */
22 #define PCI_COMMAND 0x04 /* 16 bits */
23 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
24 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
25 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
26 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
27 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
28 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
29 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
30 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
31 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
32 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
34 #define PCI_STATUS 0x06 /* 16 bits */
35 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
36 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
37 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
38 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
39 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
40 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
41 #define PCI_STATUS_DEVSEL_FAST 0x000
42 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
43 #define PCI_STATUS_DEVSEL_SLOW 0x400
44 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
45 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
46 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
47 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
48 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
50 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
52 #define PCI_REVISION_ID 0x08 /* Revision ID */
53 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
54 #define PCI_CLASS_DEVICE 0x0a /* Device class */
55 #define PCI_CLASS_CODE 0x0b /* Device class code */
56 #define PCI_CLASS_CODE_TOO_OLD 0x00
57 #define PCI_CLASS_CODE_STORAGE 0x01
58 #define PCI_CLASS_CODE_NETWORK 0x02
59 #define PCI_CLASS_CODE_DISPLAY 0x03
60 #define PCI_CLASS_CODE_MULTIMEDIA 0x04
61 #define PCI_CLASS_CODE_MEMORY 0x05
62 #define PCI_CLASS_CODE_BRIDGE 0x06
63 #define PCI_CLASS_CODE_COMM 0x07
64 #define PCI_CLASS_CODE_PERIPHERAL 0x08
65 #define PCI_CLASS_CODE_INPUT 0x09
66 #define PCI_CLASS_CODE_DOCKING 0x0A
67 #define PCI_CLASS_CODE_PROCESSOR 0x0B
68 #define PCI_CLASS_CODE_SERIAL 0x0C
69 #define PCI_CLASS_CODE_WIRELESS 0x0D
70 #define PCI_CLASS_CODE_I2O 0x0E
71 #define PCI_CLASS_CODE_SATELLITE 0x0F
72 #define PCI_CLASS_CODE_CRYPTO 0x10
73 #define PCI_CLASS_CODE_DATA 0x11
74 /* Base Class 0x12 - 0xFE is reserved */
75 #define PCI_CLASS_CODE_OTHER 0xFF
77 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
78 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
79 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
80 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
81 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
82 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
83 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
84 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
85 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
86 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
87 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
88 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
89 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
90 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
91 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
92 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
93 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
94 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
95 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
96 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
97 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
98 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
99 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
100 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
101 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
102 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
105 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
106 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
107 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
108 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
109 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
110 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
111 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
112 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
113 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
114 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
115 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
116 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
117 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
118 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
119 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
120 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
121 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
122 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
123 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
124 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
125 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
126 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
127 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
128 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
134 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
135 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
136 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
137 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
138 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
139 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
140 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
141 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
142 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
143 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
144 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
145 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
146 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
147 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
148 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
149 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
150 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
151 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
152 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
153 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
154 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
155 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
156 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
157 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
158 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
159 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
160 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
161 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
162 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
163 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
164 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
165 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
166 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
167 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
168 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
169 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
170 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
171 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
172 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
173 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
174 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
175 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
176 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
177 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
178 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
179 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
181 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
182 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
183 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
184 #define PCI_HEADER_TYPE_NORMAL 0
185 #define PCI_HEADER_TYPE_BRIDGE 1
186 #define PCI_HEADER_TYPE_CARDBUS 2
188 #define PCI_BIST 0x0f /* 8 bits */
189 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
190 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
191 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
194 * Base addresses specify locations in memory or I/O space.
195 * Decoded size can be determined by writing a value of
196 * 0xffffffff to the register, and reading it back. Only
197 * 1 bits are decoded.
199 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
200 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
201 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
202 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
203 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
204 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
205 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
206 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
207 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
208 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
209 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
210 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
211 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
212 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
213 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
214 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
215 /* bit 1 is reserved if address_space = 1 */
217 /* Header type 0 (normal devices) */
218 #define PCI_CARDBUS_CIS 0x28
219 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
220 #define PCI_SUBSYSTEM_ID 0x2e
221 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
222 #define PCI_ROM_ADDRESS_ENABLE 0x01
223 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
225 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
227 /* 0x35-0x3b are reserved */
228 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
229 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
230 #define PCI_MIN_GNT 0x3e /* 8 bits */
231 #define PCI_MAX_LAT 0x3f /* 8 bits */
233 #define PCI_INTERRUPT_LINE_DISABLE 0xff
235 /* Header type 1 (PCI-to-PCI bridges) */
236 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
237 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
238 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
239 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
240 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
241 #define PCI_IO_LIMIT 0x1d
242 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
243 #define PCI_IO_RANGE_TYPE_16 0x00
244 #define PCI_IO_RANGE_TYPE_32 0x01
245 #define PCI_IO_RANGE_MASK ~0x0f
246 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
247 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
248 #define PCI_MEMORY_LIMIT 0x22
249 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
250 #define PCI_MEMORY_RANGE_MASK ~0x0f
251 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
252 #define PCI_PREF_MEMORY_LIMIT 0x26
253 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
254 #define PCI_PREF_RANGE_TYPE_32 0x00
255 #define PCI_PREF_RANGE_TYPE_64 0x01
256 #define PCI_PREF_RANGE_MASK ~0x0f
257 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
258 #define PCI_PREF_LIMIT_UPPER32 0x2c
259 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
260 #define PCI_IO_LIMIT_UPPER16 0x32
261 /* 0x34 same as for htype 0 */
262 /* 0x35-0x3b is reserved */
263 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
264 /* 0x3c-0x3d are same as for htype 0 */
265 #define PCI_BRIDGE_CONTROL 0x3e
266 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
267 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
268 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
269 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
270 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
271 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
272 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
274 /* Header type 2 (CardBus bridges) */
275 #define PCI_CB_CAPABILITY_LIST 0x14
277 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
278 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
279 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
280 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
281 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
282 #define PCI_CB_MEMORY_BASE_0 0x1c
283 #define PCI_CB_MEMORY_LIMIT_0 0x20
284 #define PCI_CB_MEMORY_BASE_1 0x24
285 #define PCI_CB_MEMORY_LIMIT_1 0x28
286 #define PCI_CB_IO_BASE_0 0x2c
287 #define PCI_CB_IO_BASE_0_HI 0x2e
288 #define PCI_CB_IO_LIMIT_0 0x30
289 #define PCI_CB_IO_LIMIT_0_HI 0x32
290 #define PCI_CB_IO_BASE_1 0x34
291 #define PCI_CB_IO_BASE_1_HI 0x36
292 #define PCI_CB_IO_LIMIT_1 0x38
293 #define PCI_CB_IO_LIMIT_1_HI 0x3a
294 #define PCI_CB_IO_RANGE_MASK ~0x03
295 /* 0x3c-0x3d are same as for htype 0 */
296 #define PCI_CB_BRIDGE_CONTROL 0x3e
297 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
298 #define PCI_CB_BRIDGE_CTL_SERR 0x02
299 #define PCI_CB_BRIDGE_CTL_ISA 0x04
300 #define PCI_CB_BRIDGE_CTL_VGA 0x08
301 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
302 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
303 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
304 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
305 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
306 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
307 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
308 #define PCI_CB_SUBSYSTEM_ID 0x42
309 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
310 /* 0x48-0x7f reserved */
312 /* Capability lists */
314 #define PCI_CAP_LIST_ID 0 /* Capability ID */
315 #define PCI_CAP_ID_PM 0x01 /* Power Management */
316 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
317 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
318 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
319 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
320 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
321 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
322 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
323 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
324 #define PCI_CAP_SIZEOF 4
326 /* Power Management Registers */
328 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
329 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
330 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
331 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
332 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
333 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
334 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
335 #define PCI_PM_CTRL 4 /* PM control and status register */
336 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
337 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
338 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
339 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
340 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
341 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
342 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
343 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
344 #define PCI_PM_DATA_REGISTER 7 /* (??) */
345 #define PCI_PM_SIZEOF 8
349 #define PCI_AGP_VERSION 2 /* BCD version number */
350 #define PCI_AGP_RFU 3 /* Rest of capability flags */
351 #define PCI_AGP_STATUS 4 /* Status register */
352 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
353 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
354 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
355 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
356 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
357 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
358 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
359 #define PCI_AGP_COMMAND 8 /* Control register */
360 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
361 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
362 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
363 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
364 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
365 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
366 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
367 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
368 #define PCI_AGP_SIZEOF 12
370 /* PCI-X registers */
372 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
373 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
374 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
375 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
376 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
379 /* Slot Identification */
381 #define PCI_SID_ESR 2 /* Expansion Slot Register */
382 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
383 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
384 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
386 /* Message Signalled Interrupts registers */
388 #define PCI_MSI_FLAGS 2 /* Various flags */
389 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
390 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
391 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
392 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
393 #define PCI_MSI_RFU 3 /* Rest of capability flags */
394 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
395 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
396 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
397 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
399 #define PCI_MAX_PCI_DEVICES 32
400 #define PCI_MAX_PCI_FUNCTIONS 8
402 #define PCI_FIND_CAP_TTL 0x48
403 #define CAP_START_POS 0x40
405 /* Extended Capabilities (PCI-X 2.0 and Express) */
406 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
407 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
408 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
410 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
411 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
412 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
413 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
414 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
415 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
416 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
417 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
418 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
419 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
420 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
421 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
422 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
423 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
424 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
425 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
426 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
427 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
428 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
429 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
430 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
431 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
432 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
433 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
434 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
435 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
436 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
438 /* Include the ID list */
444 #ifdef CONFIG_SYS_PCI_64BIT
445 typedef u64 pci_addr_t;
446 typedef u64 pci_size_t;
448 typedef u32 pci_addr_t;
449 typedef u32 pci_size_t;
453 pci_addr_t bus_start; /* Start on the bus */
454 phys_addr_t phys_start; /* Start in physical address space */
455 pci_size_t size; /* Size */
456 unsigned long flags; /* Resource flags */
458 pci_addr_t bus_lower;
461 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
462 #define PCI_REGION_IO 0x00000001 /* PCI IO space */
463 #define PCI_REGION_TYPE 0x00000001
464 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
466 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
467 #define PCI_REGION_RO 0x00000200 /* Read-only memory */
469 static inline void pci_set_region(struct pci_region *reg,
470 pci_addr_t bus_start,
471 phys_addr_t phys_start,
473 unsigned long flags) {
474 reg->bus_start = bus_start;
475 reg->phys_start = phys_start;
480 typedef int pci_dev_t;
482 #define PCI_BUS(d) (((d) >> 16) & 0xff)
483 #define PCI_DEV(d) (((d) >> 11) & 0x1f)
484 #define PCI_FUNC(d) (((d) >> 8) & 0x7)
485 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
486 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
487 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
488 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
489 #define PCI_VENDEV(v, d) (((v) << 16) | (d))
490 #define PCI_ANY_ID (~0)
492 struct pci_device_id {
493 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
494 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
495 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
496 unsigned long driver_data; /* Data private to the driver */
499 struct pci_controller;
501 struct pci_config_table {
502 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
503 unsigned int class; /* Class ID, or PCI_ANY_ID */
504 unsigned int bus; /* Bus number, or PCI_ANY_ID */
505 unsigned int dev; /* Device number, or PCI_ANY_ID */
506 unsigned int func; /* Function number, or PCI_ANY_ID */
508 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
509 struct pci_config_table *);
510 unsigned long priv[3];
513 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
514 struct pci_config_table *);
515 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
516 struct pci_config_table *);
518 #define MAX_PCI_REGIONS 7
520 #define INDIRECT_TYPE_NO_PCIE_LINK 1
523 * Structure of a PCI controller (host bridge)
525 * With driver model this is dev_get_uclass_priv(bus)
527 struct pci_controller {
530 struct udevice *ctlr;
532 struct pci_controller *next;
538 volatile unsigned int *cfg_addr;
539 volatile unsigned char *cfg_data;
544 * TODO(sjg@chromium.org): With driver model we use struct
545 * pci_controller for both the controller and any bridge devices
546 * attached to it. But there is only one region list and it is in the
547 * top-level controller.
549 * This could be changed so that struct pci_controller is only used
550 * for PCI controllers and a separate UCLASS (or perhaps
551 * UCLASS_PCI_GENERIC) is used for bridges.
553 struct pci_region regions[MAX_PCI_REGIONS];
556 struct pci_config_table *config_table;
558 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
559 #ifndef CONFIG_DM_PCI
560 /* Low-level architecture-dependent routines */
561 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
562 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
563 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
564 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
565 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
566 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
569 /* Used by auto config */
570 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
572 #ifndef CONFIG_DM_PCI
579 #ifndef CONFIG_DM_PCI
580 static inline void pci_set_ops(struct pci_controller *hose,
581 int (*read_byte)(struct pci_controller*,
582 pci_dev_t, int where, u8 *),
583 int (*read_word)(struct pci_controller*,
584 pci_dev_t, int where, u16 *),
585 int (*read_dword)(struct pci_controller*,
586 pci_dev_t, int where, u32 *),
587 int (*write_byte)(struct pci_controller*,
588 pci_dev_t, int where, u8),
589 int (*write_word)(struct pci_controller*,
590 pci_dev_t, int where, u16),
591 int (*write_dword)(struct pci_controller*,
592 pci_dev_t, int where, u32)) {
593 hose->read_byte = read_byte;
594 hose->read_word = read_word;
595 hose->read_dword = read_dword;
596 hose->write_byte = write_byte;
597 hose->write_word = write_word;
598 hose->write_dword = write_dword;
602 #ifdef CONFIG_PCI_INDIRECT_BRIDGE
603 extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
606 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
607 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
608 pci_addr_t addr, unsigned long flags);
609 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
610 phys_addr_t addr, unsigned long flags);
612 #define pci_phys_to_bus(dev, addr, flags) \
613 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
614 #define pci_bus_to_phys(dev, addr, flags) \
615 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
617 #define pci_virt_to_bus(dev, addr, flags) \
618 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
619 (virt_to_phys(addr)), (flags))
620 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
621 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
625 #define pci_phys_to_mem(dev, addr) \
626 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
627 #define pci_mem_to_phys(dev, addr) \
628 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
629 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
630 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
632 #define pci_virt_to_mem(dev, addr) \
633 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
634 #define pci_mem_to_virt(dev, addr, len, map_flags) \
635 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
636 #define pci_virt_to_io(dev, addr) \
637 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
638 #define pci_io_to_virt(dev, addr, len, map_flags) \
639 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
641 /* For driver model these are defined in macros in pci_compat.c */
642 extern int pci_hose_read_config_byte(struct pci_controller *hose,
643 pci_dev_t dev, int where, u8 *val);
644 extern int pci_hose_read_config_word(struct pci_controller *hose,
645 pci_dev_t dev, int where, u16 *val);
646 extern int pci_hose_read_config_dword(struct pci_controller *hose,
647 pci_dev_t dev, int where, u32 *val);
648 extern int pci_hose_write_config_byte(struct pci_controller *hose,
649 pci_dev_t dev, int where, u8 val);
650 extern int pci_hose_write_config_word(struct pci_controller *hose,
651 pci_dev_t dev, int where, u16 val);
652 extern int pci_hose_write_config_dword(struct pci_controller *hose,
653 pci_dev_t dev, int where, u32 val);
656 #ifndef CONFIG_DM_PCI
657 extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
658 extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
659 extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
660 extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
661 extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
662 extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
665 void pciauto_region_init(struct pci_region *res);
666 void pciauto_region_align(struct pci_region *res, pci_size_t size);
667 void pciauto_config_init(struct pci_controller *hose);
670 * pciauto_region_allocate() - Allocate resources from a PCI resource region
672 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
673 * false, the result will be guaranteed to fit in 32 bits.
675 * @res: PCI region to allocate from
676 * @size: Amount of bytes to allocate
677 * @bar: Returns the PCI bus address of the allocated resource
678 * @supports_64bit: Whether to allow allocations above the 32-bit boundary
679 * @return 0 if successful, -1 on failure
681 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
682 pci_addr_t *bar, bool supports_64bit);
684 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
685 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
686 pci_dev_t dev, int where, u8 *val);
687 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
688 pci_dev_t dev, int where, u16 *val);
689 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
690 pci_dev_t dev, int where, u8 val);
691 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
692 pci_dev_t dev, int where, u16 val);
694 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
695 extern void pci_register_hose(struct pci_controller* hose);
696 extern struct pci_controller* pci_bus_to_hose(int bus);
697 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
698 extern struct pci_controller *pci_get_hose_head(void);
700 extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
701 extern int pci_hose_scan(struct pci_controller *hose);
702 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
704 extern void pciauto_setup_device(struct pci_controller *hose,
705 pci_dev_t dev, int bars_num,
706 struct pci_region *mem,
707 struct pci_region *prefetch,
708 struct pci_region *io);
709 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
710 pci_dev_t dev, int sub_bus);
711 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
712 pci_dev_t dev, int sub_bus);
713 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
715 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
716 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
717 pci_dev_t pci_find_class(unsigned int find_class, int index);
719 extern int pci_hose_config_device(struct pci_controller *hose,
723 unsigned long command);
725 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
727 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
729 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
732 int pci_find_next_ext_capability(struct pci_controller *hose,
733 pci_dev_t dev, int start, int cap);
734 int pci_hose_find_ext_capability(struct pci_controller *hose,
735 pci_dev_t dev, int cap);
737 #ifdef CONFIG_PCI_FIXUP_DEV
738 extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
739 unsigned short vendor,
740 unsigned short device,
741 unsigned short class);
743 #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
745 const char * pci_class_str(u8 class);
746 int pci_last_busno(void);
748 #ifdef CONFIG_MPC85xx
749 extern void pci_mpc85xx_init (struct pci_controller *hose);
752 #ifdef CONFIG_PCIE_IMX
753 extern void imx_pcie_remove(void);
756 #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
758 * pci_write_bar32() - Write the address of a BAR including control bits
760 * This writes a raw address (with control bits) to a bar. This can be used
761 * with devices which require hard-coded addresses, not part of the normal
762 * PCI enumeration process.
764 * @hose: PCI hose to use
765 * @dev: PCI device to update
766 * @barnum: BAR number (0-5)
767 * @addr: BAR address with control bits
769 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
773 * pci_read_bar32() - read the address of a bar
775 * @hose: PCI hose to use
776 * @dev: PCI device to inspect
777 * @barnum: BAR number (0-5)
778 * @return address of the bar, masking out any control bits
780 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
783 * pci_hose_find_devices() - Find devices by vendor/device ID
785 * @hose: PCI hose to search
786 * @busnum: Bus number to search
787 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
788 * @indexp: Pointer to device index to find. To find the first matching
789 * device, pass 0; to find the second, pass 1, etc. This
790 * parameter is decremented for each non-matching device so
791 * can be called repeatedly.
793 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
794 struct pci_device_id *ids, int *indexp);
795 #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
797 /* Access sizes for PCI reads and writes */
808 * struct pci_child_platdata - information stored about each PCI device
810 * Every device on a PCI bus has this per-child data.
812 * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a
813 * PCI bus (i.e. UCLASS_PCI)
815 * @devfn: Encoded device and function index - see PCI_DEVFN()
816 * @vendor: PCI vendor ID (see pci_ids.h)
817 * @device: PCI device ID (see pci_ids.h)
818 * @class: PCI class, 3 bytes: (base, sub, prog-if)
820 struct pci_child_platdata {
822 unsigned short vendor;
823 unsigned short device;
827 /* PCI bus operations */
830 * read_config() - Read a PCI configuration value
832 * PCI buses must support reading and writing configuration values
833 * so that the bus can be scanned and its devices configured.
835 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
836 * If bridges exist it is possible to use the top-level bus to
837 * access a sub-bus. In that case @bus will be the top-level bus
838 * and PCI_BUS(bdf) will be a different (higher) value
840 * @bus: Bus to read from
841 * @bdf: Bus, device and function to read
842 * @offset: Byte offset within the device's configuration space
843 * @valuep: Place to put the returned value
845 * @return 0 if OK, -ve on error
847 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
848 ulong *valuep, enum pci_size_t size);
850 * write_config() - Write a PCI configuration value
852 * @bus: Bus to write to
853 * @bdf: Bus, device and function to write
854 * @offset: Byte offset within the device's configuration space
855 * @value: Value to write
857 * @return 0 if OK, -ve on error
859 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
860 ulong value, enum pci_size_t size);
863 /* Get access to a PCI bus' operations */
864 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
867 * dm_pci_get_bdf() - Get the BDF value for a device
869 * @dev: Device to check
870 * @return bus/device/function value (see PCI_BDF())
872 pci_dev_t dm_pci_get_bdf(struct udevice *dev);
875 * pci_bind_bus_devices() - scan a PCI bus and bind devices
877 * Scan a PCI bus looking for devices. Bind each one that is found. If
878 * devices are already bound that match the scanned devices, just update the
879 * child data so that the device can be used correctly (this happens when
880 * the device tree describes devices we expect to see on the bus).
882 * Devices that are bound in this way will use a generic PCI driver which
883 * does nothing. The device can still be accessed but will not provide any
886 * @bus: Bus containing devices to bind
887 * @return 0 if OK, -ve on error
889 int pci_bind_bus_devices(struct udevice *bus);
892 * pci_auto_config_devices() - configure bus devices ready for use
894 * This works through all devices on a bus by scanning the driver model
895 * data structures (normally these have been set up by pci_bind_bus_devices()
898 * Space is allocated for each PCI base address register (BAR) so that the
899 * devices are mapped into memory and I/O space ready for use.
901 * @bus: Bus containing devices to bind
902 * @return 0 if OK, -ve on error
904 int pci_auto_config_devices(struct udevice *bus);
907 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
909 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
910 * @devp: Returns the device for this address, if found
911 * @return 0 if OK, -ENODEV if not found
913 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
916 * pci_bus_find_devfn() - Find a device on a bus
918 * @find_devfn: PCI device address (device and function only)
919 * @devp: Returns the device for this address, if found
920 * @return 0 if OK, -ENODEV if not found
922 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
923 struct udevice **devp);
926 * pci_find_first_device() - return the first available PCI device
928 * This function and pci_find_first_device() allow iteration through all
929 * available PCI devices on all buses. Assuming there are any, this will
930 * return the first one.
932 * @devp: Set to the first available device, or NULL if no more are left
934 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
936 int pci_find_first_device(struct udevice **devp);
939 * pci_find_next_device() - return the next available PCI device
941 * Finds the next available PCI device after the one supplied, or sets @devp
942 * to NULL if there are no more.
944 * @devp: On entry, the last device returned. Set to the next available
945 * device, or NULL if no more are left or we got an error
946 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
948 int pci_find_next_device(struct udevice **devp);
951 * pci_get_ff() - Returns a mask for the given access size
954 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
957 int pci_get_ff(enum pci_size_t size);
960 * pci_bus_find_devices () - Find devices on a bus
962 * @bus: Bus to search
963 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
964 * @indexp: Pointer to device index to find. To find the first matching
965 * device, pass 0; to find the second, pass 1, etc. This
966 * parameter is decremented for each non-matching device so
967 * can be called repeatedly.
968 * @devp: Returns matching device if found
969 * @return 0 if found, -ENODEV if not
971 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
972 int *indexp, struct udevice **devp);
975 * pci_find_device_id() - Find a device on any bus
977 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
978 * @index: Index number of device to find, 0 for the first match, 1 for
980 * @devp: Returns matching device if found
981 * @return 0 if found, -ENODEV if not
983 int pci_find_device_id(struct pci_device_id *ids, int index,
984 struct udevice **devp);
987 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
989 * This probes the given bus which causes it to be scanned for devices. The
990 * devices will be bound but not probed.
992 * @hose specifies the PCI hose that will be used for the scan. This is
993 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
994 * in @bdf, and is a subordinate bus reachable from @hose.
996 * @hose: PCI hose to scan
997 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
998 * @return 0 if OK, -ve on error
1000 int dm_pci_hose_probe_bus(struct udevice *bus);
1003 * pci_bus_read_config() - Read a configuration value from a device
1005 * TODO(sjg@chromium.org): We should be able to pass just a device and have
1006 * it do the right thing. It would be good to have that function also.
1008 * @bus: Bus to read from
1009 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1010 * @offset: Register offset to read
1011 * @valuep: Place to put the returned value
1012 * @size: Access size
1013 * @return 0 if OK, -ve on error
1015 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
1016 unsigned long *valuep, enum pci_size_t size);
1019 * pci_bus_write_config() - Write a configuration value to a device
1021 * @bus: Bus to write from
1022 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1023 * @offset: Register offset to write
1024 * @value: Value to write
1025 * @size: Access size
1026 * @return 0 if OK, -ve on error
1028 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1029 unsigned long value, enum pci_size_t size);
1032 * pci_bus_clrset_config32() - Update a configuration value for a device
1034 * The register at @offset is updated to (oldvalue & ~clr) | set.
1036 * @bus: Bus to access
1037 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1038 * @offset: Register offset to update
1039 * @clr: Bits to clear
1041 * @return 0 if OK, -ve on error
1043 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1047 * Driver model PCI config access functions. Use these in preference to others
1048 * when you have a valid device
1050 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
1051 enum pci_size_t size);
1053 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
1054 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
1055 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
1057 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1058 enum pci_size_t size);
1060 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1061 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1062 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1065 * These permit convenient read/modify/write on PCI configuration. The
1066 * register is updated to (oldvalue & ~clr) | set.
1068 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1069 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1070 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
1073 * The following functions provide access to the above without needing the
1074 * size parameter. We are trying to encourage the use of the 8/16/32-style
1075 * functions, rather than byte/word/dword. But both are supported.
1077 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
1078 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1079 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1080 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1081 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1082 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
1085 * pci_generic_mmap_write_config() - Generic helper for writing to
1086 * memory-mapped PCI configuration space.
1087 * @bus: Pointer to the PCI bus
1088 * @addr_f: Callback for calculating the config space address
1089 * @bdf: Identifies the PCI device to access
1090 * @offset: The offset into the device's configuration space
1091 * @value: The value to write
1092 * @size: Indicates the size of access to perform
1094 * Write the value @value of size @size from offset @offset within the
1095 * configuration space of the device identified by the bus, device & function
1096 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
1097 * responsible for calculating the CPU address of the respective configuration
1100 * Return: 0 on success, else -EINVAL
1102 int pci_generic_mmap_write_config(
1103 struct udevice *bus,
1104 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1108 enum pci_size_t size);
1111 * pci_generic_mmap_read_config() - Generic helper for reading from
1112 * memory-mapped PCI configuration space.
1113 * @bus: Pointer to the PCI bus
1114 * @addr_f: Callback for calculating the config space address
1115 * @bdf: Identifies the PCI device to access
1116 * @offset: The offset into the device's configuration space
1117 * @valuep: A pointer at which to store the read value
1118 * @size: Indicates the size of access to perform
1120 * Read a value of size @size from offset @offset within the configuration
1121 * space of the device identified by the bus, device & function numbers in @bdf
1122 * on the PCI bus @bus. The callback function @addr_f is responsible for
1123 * calculating the CPU address of the respective configuration space offset.
1125 * Return: 0 on success, else -EINVAL
1127 int pci_generic_mmap_read_config(
1128 struct udevice *bus,
1129 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1133 enum pci_size_t size);
1135 #ifdef CONFIG_DM_PCI_COMPAT
1136 /* Compatibility with old naming */
1137 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1140 return pci_write_config32(pcidev, offset, value);
1143 /* Compatibility with old naming */
1144 static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1147 return pci_write_config16(pcidev, offset, value);
1150 /* Compatibility with old naming */
1151 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1154 return pci_write_config8(pcidev, offset, value);
1157 /* Compatibility with old naming */
1158 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1161 return pci_read_config32(pcidev, offset, valuep);
1164 /* Compatibility with old naming */
1165 static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1168 return pci_read_config16(pcidev, offset, valuep);
1171 /* Compatibility with old naming */
1172 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1175 return pci_read_config8(pcidev, offset, valuep);
1177 #endif /* CONFIG_DM_PCI_COMPAT */
1180 * dm_pciauto_config_device() - configure a device ready for use
1182 * Space is allocated for each PCI base address register (BAR) so that the
1183 * devices are mapped into memory and I/O space ready for use.
1185 * @dev: Device to configure
1186 * @return 0 if OK, -ve on error
1188 int dm_pciauto_config_device(struct udevice *dev);
1191 * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1193 * Some PCI buses must always perform 32-bit reads. The data must then be
1194 * shifted and masked to reflect the required access size and offset. This
1195 * function performs this transformation.
1197 * @value: Value to transform (32-bit value read from @offset & ~3)
1198 * @offset: Register offset that was read
1199 * @size: Required size of the result
1200 * @return the value that would have been obtained if the read had been
1201 * performed at the given offset with the correct size
1203 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1206 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1208 * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1209 * write the old 32-bit data must be read, updated with the required new data
1210 * and written back as a 32-bit value. This function performs the
1211 * transformation from the old value to the new value.
1213 * @value: Value to transform (32-bit value read from @offset & ~3)
1214 * @offset: Register offset that should be written
1215 * @size: Required size of the write
1216 * @return the value that should be written as a 32-bit access to @offset & ~3.
1218 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1219 enum pci_size_t size);
1222 * pci_get_controller() - obtain the controller to use for a bus
1224 * @dev: Device to check
1225 * @return pointer to the controller device for this bus
1227 struct udevice *pci_get_controller(struct udevice *dev);
1230 * pci_get_regions() - obtain pointers to all the region types
1232 * @dev: Device to check
1233 * @iop: Returns a pointer to the I/O region, or NULL if none
1234 * @memp: Returns a pointer to the memory region, or NULL if none
1235 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
1236 * @return the number of non-NULL regions returned, normally 3
1238 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1239 struct pci_region **memp, struct pci_region **prefp);
1242 * dm_pci_write_bar32() - Write the address of a BAR
1244 * This writes a raw address to a bar
1246 * @dev: PCI device to update
1247 * @barnum: BAR number (0-5)
1248 * @addr: BAR address
1250 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1253 * dm_pci_read_bar32() - read a base address register from a device
1255 * @dev: Device to check
1256 * @barnum: Bar number to read (numbered from 0)
1257 * @return: value of BAR
1259 u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
1262 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
1264 * @dev: Device containing the PCI address
1265 * @addr: PCI address to convert
1266 * @flags: Flags for the region type (PCI_REGION_...)
1267 * @return physical address corresponding to that PCI bus address
1269 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1270 unsigned long flags);
1273 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1275 * @dev: Device containing the bus address
1276 * @addr: Physical address to convert
1277 * @flags: Flags for the region type (PCI_REGION_...)
1278 * @return PCI bus address corresponding to that physical address
1280 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1281 unsigned long flags);
1284 * dm_pci_map_bar() - get a virtual address associated with a BAR region
1286 * Looks up a base address register and finds the physical memory address
1287 * that corresponds to it
1289 * @dev: Device to check
1290 * @bar: Bar number to read (numbered from 0)
1291 * @flags: Flags for the region type (PCI_REGION_...)
1292 * @return: pointer to the virtual address to use
1294 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
1296 #define dm_pci_virt_to_bus(dev, addr, flags) \
1297 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1298 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1299 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1302 #define dm_pci_phys_to_mem(dev, addr) \
1303 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1304 #define dm_pci_mem_to_phys(dev, addr) \
1305 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1306 #define dm_pci_phys_to_io(dev, addr) \
1307 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1308 #define dm_pci_io_to_phys(dev, addr) \
1309 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1311 #define dm_pci_virt_to_mem(dev, addr) \
1312 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1313 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1314 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1315 #define dm_pci_virt_to_io(dev, addr) \
1316 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
1317 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
1318 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
1321 * dm_pci_find_device() - find a device by vendor/device ID
1323 * @vendor: Vendor ID
1324 * @device: Device ID
1325 * @index: 0 to find the first match, 1 for second, etc.
1326 * @devp: Returns pointer to the device, if found
1327 * @return 0 if found, -ve on error
1329 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1330 struct udevice **devp);
1333 * dm_pci_find_class() - find a device by class
1335 * @find_class: 3-byte (24-bit) class value to find
1336 * @index: 0 to find the first match, 1 for second, etc.
1337 * @devp: Returns pointer to the device, if found
1338 * @return 0 if found, -ve on error
1340 int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1343 * struct dm_pci_emul_ops - PCI device emulator operations
1345 struct dm_pci_emul_ops {
1347 * get_devfn(): Check which device and function this emulators
1349 * @dev: device to check
1350 * @return the device and function this emulates, or -ve on error
1352 int (*get_devfn)(struct udevice *dev);
1354 * read_config() - Read a PCI configuration value
1356 * @dev: Emulated device to read from
1357 * @offset: Byte offset within the device's configuration space
1358 * @valuep: Place to put the returned value
1359 * @size: Access size
1360 * @return 0 if OK, -ve on error
1362 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
1363 enum pci_size_t size);
1365 * write_config() - Write a PCI configuration value
1367 * @dev: Emulated device to write to
1368 * @offset: Byte offset within the device's configuration space
1369 * @value: Value to write
1370 * @size: Access size
1371 * @return 0 if OK, -ve on error
1373 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1374 enum pci_size_t size);
1376 * read_io() - Read a PCI I/O value
1378 * @dev: Emulated device to read from
1379 * @addr: I/O address to read
1380 * @valuep: Place to put the returned value
1381 * @size: Access size
1382 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1383 * other -ve value on error
1385 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1386 enum pci_size_t size);
1388 * write_io() - Write a PCI I/O value
1390 * @dev: Emulated device to write from
1391 * @addr: I/O address to write
1392 * @value: Value to write
1393 * @size: Access size
1394 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1395 * other -ve value on error
1397 int (*write_io)(struct udevice *dev, unsigned int addr,
1398 ulong value, enum pci_size_t size);
1400 * map_physmem() - Map a device into sandbox memory
1402 * @dev: Emulated device to map
1403 * @addr: Memory address, normally corresponding to a PCI BAR.
1404 * The device should have been configured to have a BAR
1406 * @lenp: On entry, the size of the area to map, On exit it is
1407 * updated to the size actually mapped, which may be less
1408 * if the device has less space
1409 * @ptrp: Returns a pointer to the mapped address. The device's
1410 * space can be accessed as @lenp bytes starting here
1411 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1412 * other -ve value on error
1414 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1415 unsigned long *lenp, void **ptrp);
1417 * unmap_physmem() - undo a memory mapping
1419 * This must be called after map_physmem() to undo the mapping.
1420 * Some devices can use this to check what has been written into
1421 * their mapped memory and perform an operations they require on it.
1422 * In this way, map/unmap can be used as a sort of handshake between
1423 * the emulated device and its users.
1425 * @dev: Emuated device to unmap
1426 * @vaddr: Mapped memory address, as passed to map_physmem()
1427 * @len: Size of area mapped, as returned by map_physmem()
1428 * @return 0 if OK, -ve on error
1430 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1434 /* Get access to a PCI device emulator's operations */
1435 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1438 * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1440 * Searches for a suitable emulator for the given PCI bus device
1442 * @bus: PCI bus to search
1443 * @find_devfn: PCI device and function address (PCI_DEVFN())
1444 * @emulp: Returns emulated device if found
1445 * @return 0 if found, -ENODEV if not found
1447 int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
1448 struct udevice **emulp);
1450 #endif /* CONFIG_DM_PCI */
1453 * PCI_DEVICE - macro used to describe a specific pci device
1454 * @vend: the 16 bit PCI Vendor ID
1455 * @dev: the 16 bit PCI Device ID
1457 * This macro is used to create a struct pci_device_id that matches a
1458 * specific device. The subvendor and subdevice fields will be set to
1461 #define PCI_DEVICE(vend, dev) \
1462 .vendor = (vend), .device = (dev), \
1463 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1466 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1467 * @vend: the 16 bit PCI Vendor ID
1468 * @dev: the 16 bit PCI Device ID
1469 * @subvend: the 16 bit PCI Subvendor ID
1470 * @subdev: the 16 bit PCI Subdevice ID
1472 * This macro is used to create a struct pci_device_id that matches a
1473 * specific device with subsystem information.
1475 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1476 .vendor = (vend), .device = (dev), \
1477 .subvendor = (subvend), .subdevice = (subdev)
1480 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1481 * @dev_class: the class, subclass, prog-if triple for this device
1482 * @dev_class_mask: the class mask for this device
1484 * This macro is used to create a struct pci_device_id that matches a
1485 * specific PCI class. The vendor, device, subvendor, and subdevice
1486 * fields will be set to PCI_ANY_ID.
1488 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1489 .class = (dev_class), .class_mask = (dev_class_mask), \
1490 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1491 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1494 * PCI_VDEVICE - macro used to describe a specific pci device in short form
1495 * @vend: the vendor name
1496 * @dev: the 16 bit PCI Device ID
1498 * This macro is used to create a struct pci_device_id that matches a
1499 * specific PCI device. The subvendor, and subdevice fields will be set
1500 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1504 #define PCI_VDEVICE(vend, dev) \
1505 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1506 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1509 * struct pci_driver_entry - Matches a driver to its pci_device_id list
1510 * @driver: Driver to use
1511 * @match: List of match records for this driver, terminated by {}
1513 struct pci_driver_entry {
1514 struct driver *driver;
1515 const struct pci_device_id *match;
1518 #define U_BOOT_PCI_DEVICE(__name, __match) \
1519 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1520 .driver = llsym(struct driver, __name, driver), \
1524 #endif /* __ASSEMBLY__ */