1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Copyright (c) 2021 Maciej W. Rozycki <macro@orcam.me.uk>
14 #define PCI_CFG_SPACE_SIZE 256
15 #define PCI_CFG_SPACE_EXP_SIZE 4096
18 * Under PCI, each device has 256 bytes of configuration address space,
19 * of which the first 64 bytes are standardized as follows:
21 #define PCI_STD_HEADER_SIZEOF 64
22 #define PCI_VENDOR_ID 0x00 /* 16 bits */
23 #define PCI_DEVICE_ID 0x02 /* 16 bits */
24 #define PCI_COMMAND 0x04 /* 16 bits */
25 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
26 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
27 #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
28 #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
29 #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
30 #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
31 #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
32 #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
33 #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
34 #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
36 #define PCI_STATUS 0x06 /* 16 bits */
37 #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
38 #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
39 #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
40 #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
41 #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
42 #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
43 #define PCI_STATUS_DEVSEL_FAST 0x000
44 #define PCI_STATUS_DEVSEL_MEDIUM 0x200
45 #define PCI_STATUS_DEVSEL_SLOW 0x400
46 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
47 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
48 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
49 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
50 #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
52 #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
54 #define PCI_REVISION_ID 0x08 /* Revision ID */
55 #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
56 #define PCI_CLASS_DEVICE 0x0a /* Device class */
57 #define PCI_CLASS_CODE 0x0b /* Device class code */
58 #define PCI_CLASS_CODE_TOO_OLD 0x00
59 #define PCI_CLASS_CODE_STORAGE 0x01
60 #define PCI_CLASS_CODE_NETWORK 0x02
61 #define PCI_CLASS_CODE_DISPLAY 0x03
62 #define PCI_CLASS_CODE_MULTIMEDIA 0x04
63 #define PCI_CLASS_CODE_MEMORY 0x05
64 #define PCI_CLASS_CODE_BRIDGE 0x06
65 #define PCI_CLASS_CODE_COMM 0x07
66 #define PCI_CLASS_CODE_PERIPHERAL 0x08
67 #define PCI_CLASS_CODE_INPUT 0x09
68 #define PCI_CLASS_CODE_DOCKING 0x0A
69 #define PCI_CLASS_CODE_PROCESSOR 0x0B
70 #define PCI_CLASS_CODE_SERIAL 0x0C
71 #define PCI_CLASS_CODE_WIRELESS 0x0D
72 #define PCI_CLASS_CODE_I2O 0x0E
73 #define PCI_CLASS_CODE_SATELLITE 0x0F
74 #define PCI_CLASS_CODE_CRYPTO 0x10
75 #define PCI_CLASS_CODE_DATA 0x11
76 /* Base Class 0x12 - 0xFE is reserved */
77 #define PCI_CLASS_CODE_OTHER 0xFF
79 #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
80 #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
81 #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
82 #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
83 #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
84 #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
85 #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
86 #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
87 #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
88 #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
89 #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
90 #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
91 #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
92 #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
93 #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
94 #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
95 #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
96 #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
97 #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
98 #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
99 #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
100 #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
101 #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
102 #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
103 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
104 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
105 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
106 #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
107 #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
108 #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
109 #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
110 #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
111 #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
112 #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
113 #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
114 #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
115 #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
116 #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
117 #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
118 #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
119 #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
120 #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
121 #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
122 #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
123 #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
124 #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
125 #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
126 #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
127 #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
128 #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
129 #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
130 #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
131 #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
132 #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
133 #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
134 #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
135 #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
136 #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
137 #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
138 #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
139 #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
140 #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
141 #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
142 #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
143 #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
144 #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
145 #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
146 #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
147 #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
148 #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
149 #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
150 #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
151 #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
152 #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
153 #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
154 #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
155 #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
156 #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
157 #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
158 #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
159 #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
160 #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
161 #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
162 #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
163 #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
164 #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
165 #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
166 #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
167 #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
168 #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
169 #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
170 #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
171 #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
172 #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
173 #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
174 #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
175 #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
176 #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
177 #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
178 #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
179 #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
180 #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
181 #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
183 #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
184 #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
185 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
186 #define PCI_HEADER_TYPE_NORMAL 0
187 #define PCI_HEADER_TYPE_BRIDGE 1
188 #define PCI_HEADER_TYPE_CARDBUS 2
190 #define PCI_BIST 0x0f /* 8 bits */
191 #define PCI_BIST_CODE_MASK 0x0f /* Return result */
192 #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
193 #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
196 * Base addresses specify locations in memory or I/O space.
197 * Decoded size can be determined by writing a value of
198 * 0xffffffff to the register, and reading it back. Only
199 * 1 bits are decoded.
201 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
202 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
203 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
204 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
205 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
206 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
207 #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
208 #define PCI_BASE_ADDRESS_SPACE_IO 0x01
209 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
210 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
211 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
212 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
213 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
214 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
215 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
216 #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
217 /* bit 1 is reserved if address_space = 1 */
219 /* Convert a regsister address (e.g. PCI_BASE_ADDRESS_1) to a bar # (e.g. 1) */
220 #define pci_offset_to_barnum(offset) \
221 (((offset) - PCI_BASE_ADDRESS_0) / sizeof(u32))
223 /* Header type 0 (normal devices) */
224 #define PCI_CARDBUS_CIS 0x28
225 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
226 #define PCI_SUBSYSTEM_ID 0x2e
227 #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
228 #define PCI_ROM_ADDRESS_ENABLE 0x01
229 #define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
231 #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
233 /* 0x35-0x3b are reserved */
234 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
235 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
236 #define PCI_MIN_GNT 0x3e /* 8 bits */
237 #define PCI_MAX_LAT 0x3f /* 8 bits */
239 #define PCI_INTERRUPT_LINE_DISABLE 0xff
241 /* Header type 1 (PCI-to-PCI bridges) */
242 #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
243 #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
244 #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
245 #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
246 #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
247 #define PCI_IO_LIMIT 0x1d
248 #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
249 #define PCI_IO_RANGE_TYPE_16 0x00
250 #define PCI_IO_RANGE_TYPE_32 0x01
251 #define PCI_IO_RANGE_MASK ~0x0f
252 #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
253 #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
254 #define PCI_MEMORY_LIMIT 0x22
255 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
256 #define PCI_MEMORY_RANGE_MASK ~0x0f
257 #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
258 #define PCI_PREF_MEMORY_LIMIT 0x26
259 #define PCI_PREF_RANGE_TYPE_MASK 0x0f
260 #define PCI_PREF_RANGE_TYPE_32 0x00
261 #define PCI_PREF_RANGE_TYPE_64 0x01
262 #define PCI_PREF_RANGE_MASK ~0x0f
263 #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
264 #define PCI_PREF_LIMIT_UPPER32 0x2c
265 #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
266 #define PCI_IO_LIMIT_UPPER16 0x32
267 /* 0x34 same as for htype 0 */
268 /* 0x35-0x3b is reserved */
269 #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
270 /* 0x3c-0x3d are same as for htype 0 */
271 #define PCI_BRIDGE_CONTROL 0x3e
272 #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
273 #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
274 #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
275 #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
276 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
277 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
278 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
280 /* Header type 2 (CardBus bridges) */
281 #define PCI_CB_CAPABILITY_LIST 0x14
283 #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
284 #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
285 #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
286 #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
287 #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
288 #define PCI_CB_MEMORY_BASE_0 0x1c
289 #define PCI_CB_MEMORY_LIMIT_0 0x20
290 #define PCI_CB_MEMORY_BASE_1 0x24
291 #define PCI_CB_MEMORY_LIMIT_1 0x28
292 #define PCI_CB_IO_BASE_0 0x2c
293 #define PCI_CB_IO_BASE_0_HI 0x2e
294 #define PCI_CB_IO_LIMIT_0 0x30
295 #define PCI_CB_IO_LIMIT_0_HI 0x32
296 #define PCI_CB_IO_BASE_1 0x34
297 #define PCI_CB_IO_BASE_1_HI 0x36
298 #define PCI_CB_IO_LIMIT_1 0x38
299 #define PCI_CB_IO_LIMIT_1_HI 0x3a
300 #define PCI_CB_IO_RANGE_MASK ~0x03
301 /* 0x3c-0x3d are same as for htype 0 */
302 #define PCI_CB_BRIDGE_CONTROL 0x3e
303 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
304 #define PCI_CB_BRIDGE_CTL_SERR 0x02
305 #define PCI_CB_BRIDGE_CTL_ISA 0x04
306 #define PCI_CB_BRIDGE_CTL_VGA 0x08
307 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
308 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
309 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
310 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
311 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
312 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
313 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
314 #define PCI_CB_SUBSYSTEM_ID 0x42
315 #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
316 /* 0x48-0x7f reserved */
318 /* Capability lists */
320 #define PCI_CAP_LIST_ID 0 /* Capability ID */
321 #define PCI_CAP_ID_PM 0x01 /* Power Management */
322 #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
323 #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
324 #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
325 #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
326 #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
327 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
328 #define PCI_CAP_ID_HT 0x08 /* HyperTransport */
329 #define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
330 #define PCI_CAP_ID_DBG 0x0A /* Debug port */
331 #define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
332 #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
333 #define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
334 #define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
335 #define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
336 #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
337 #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
338 #define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
339 #define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
340 #define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
341 #define PCI_CAP_ID_MAX PCI_CAP_ID_EA
342 #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
343 #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
344 #define PCI_CAP_SIZEOF 4
346 /* Power Management Registers */
348 #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
349 #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
350 #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
351 #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
352 #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
353 #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
354 #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
355 #define PCI_PM_CTRL 4 /* PM control and status register */
356 #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
357 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
358 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
359 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
360 #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
361 #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
362 #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
363 #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
364 #define PCI_PM_DATA_REGISTER 7 /* (??) */
365 #define PCI_PM_SIZEOF 8
369 #define PCI_AGP_VERSION 2 /* BCD version number */
370 #define PCI_AGP_RFU 3 /* Rest of capability flags */
371 #define PCI_AGP_STATUS 4 /* Status register */
372 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
373 #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
374 #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
375 #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
376 #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
377 #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
378 #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
379 #define PCI_AGP_COMMAND 8 /* Control register */
380 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
381 #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
382 #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
383 #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
384 #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
385 #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
386 #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
387 #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
388 #define PCI_AGP_SIZEOF 12
390 /* PCI-X registers */
392 #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
393 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
394 #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
395 #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
396 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
399 /* Slot Identification */
401 #define PCI_SID_ESR 2 /* Expansion Slot Register */
402 #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
403 #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
404 #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
406 /* Message Signalled Interrupts registers */
408 #define PCI_MSI_FLAGS 2 /* Various flags */
409 #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
410 #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
411 #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
412 #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
413 #define PCI_MSI_FLAGS_MASKBIT 0x0100 /* Per-vector masking capable */
414 #define PCI_MSI_RFU 3 /* Rest of capability flags */
415 #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
416 #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
417 #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
418 #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
420 #define PCI_MAX_PCI_DEVICES 32
421 #define PCI_MAX_PCI_FUNCTIONS 8
423 #define PCI_FIND_CAP_TTL 0x48
424 #define CAP_START_POS 0x40
426 /* Extended Capabilities (PCI-X 2.0 and Express) */
427 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
428 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
429 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
431 #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
432 #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
433 #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
434 #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
435 #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
436 #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
437 #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
438 #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
439 #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
440 #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
441 #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
442 #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
443 #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
444 #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
445 #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
446 #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
447 #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
448 #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
449 #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
450 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
451 #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
452 #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
453 #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
454 #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
455 #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
456 #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
457 #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
458 #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
459 #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
460 #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
461 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
463 /* Enhanced Allocation Registers */
464 #define PCI_EA_NUM_ENT 2 /* Number of Capability Entries */
465 #define PCI_EA_NUM_ENT_MASK 0x3f /* Num Entries Mask */
466 #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */
467 #define PCI_EA_ES 0x00000007 /* Entry Size */
468 #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */
469 /* 9-14 map to VF BARs 0-5 respectively */
470 #define PCI_EA_BEI_VF_BAR0 9
471 #define PCI_EA_BEI_VF_BAR5 14
472 /* Base, MaxOffset registers */
473 /* bit 0 is reserved */
474 #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */
475 #define PCI_EA_FIELD_MASK 0xfffffffc /* For Base & Max Offset */
477 /* PCI Express capabilities */
478 #define PCI_EXP_FLAGS 2 /* Capabilities register */
479 #define PCI_EXP_FLAGS_VERS 0x000f /* Capability Version */
480 #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
481 #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
482 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
483 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
484 #define PCI_EXP_DEVCAP 4 /* Device capabilities */
485 #define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
486 #define PCI_EXP_DEVCTL 8 /* Device Control */
487 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
488 #define PCI_EXP_DEVCTL_PAYLOAD_128B 0x0000 /* 128 Bytes */
489 #define PCI_EXP_DEVCTL_PAYLOAD_256B 0x0020 /* 256 Bytes */
490 #define PCI_EXP_DEVCTL_PAYLOAD_512B 0x0040 /* 512 Bytes */
491 #define PCI_EXP_DEVCTL_PAYLOAD_1024B 0x0060 /* 1024 Bytes */
492 #define PCI_EXP_DEVCTL_PAYLOAD_2048B 0x0080 /* 2048 Bytes */
493 #define PCI_EXP_DEVCTL_PAYLOAD_4096B 0x00a0 /* 4096 Bytes */
494 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
495 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
496 #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
497 #define PCI_EXP_DEVCTL_READRQ_128B 0x0000 /* 128 Bytes */
498 #define PCI_EXP_DEVCTL_READRQ_256B 0x1000 /* 256 Bytes */
499 #define PCI_EXP_DEVCTL_READRQ_512B 0x2000 /* 512 Bytes */
500 #define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 /* 1024 Bytes */
501 #define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 /* 2048 Bytes */
502 #define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 /* 4096 Bytes */
503 #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
504 #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
505 #define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
506 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 /* LNKCAP2 SLS Vector bit 0 */
507 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 /* LNKCAP2 SLS Vector bit 1 */
508 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */
509 #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
510 #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
511 #define PCI_EXP_LNKCTL 16 /* Link Control */
512 #define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
513 #define PCI_EXP_LNKSTA 18 /* Link Status */
514 #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
515 #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 /* Current Link Speed 2.5GT/s */
516 #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 /* Current Link Speed 5.0GT/s */
517 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 /* Current Link Speed 8.0GT/s */
518 #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Negotiated Link Width */
519 #define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
520 #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
521 #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
522 #define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
523 #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
524 #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
525 #define PCI_EXP_RTCTL 28 /* Root Control */
526 #define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */
527 #define PCI_EXP_RTCAP 30 /* Root Capabilities */
528 #define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
529 #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
530 #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */
531 #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
532 #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
533 #define PCI_EXP_LNKCAP2 44 /* Link Capability 2 */
534 #define PCI_EXP_LNKCAP2_SLS 0x000000fe /* Supported Link Speeds Vector */
535 #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
536 #define PCI_EXP_LNKCTL2_TLS 0x000f /* Target Link Speed */
537 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Target Link Speed 2.5GT/s */
538 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Target Link Speed 5.0GT/s */
539 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Target Link Speed 8.0GT/s */
541 /* Advanced Error Reporting */
542 #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
543 #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
544 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
545 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
546 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
547 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
549 /* Single Root I/O Virtualization Registers */
550 #define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
551 #define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
552 #define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
553 #define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
554 #define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
555 #define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
556 #define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
557 #define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
558 #define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
559 #define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
560 #define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
562 /* Include the ID list */
567 * Config Address for PCI Configuration Mechanism #1
569 * See PCI Local Bus Specification, Revision 3.0,
570 * Section 3.2.2.3.2, Figure 3-2, p. 50.
573 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
574 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
575 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
577 #define PCI_CONF1_BUS_MASK 0xff
578 #define PCI_CONF1_DEV_MASK 0x1f
579 #define PCI_CONF1_FUNC_MASK 0x7
580 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
582 #define PCI_CONF1_ENABLE BIT(31)
583 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
584 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
585 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
586 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
588 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
589 (PCI_CONF1_ENABLE | \
590 PCI_CONF1_BUS(bus) | \
591 PCI_CONF1_DEV(dev) | \
592 PCI_CONF1_FUNC(func) | \
596 * Extension of PCI Config Address for accessing extended PCIe registers
598 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
599 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
600 * are used for specifying additional 4 high bits of PCI Express register.
603 #define PCI_CONF1_EXT_REG_SHIFT 16
604 #define PCI_CONF1_EXT_REG_MASK 0xf00
605 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
607 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
608 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
609 PCI_CONF1_EXT_REG(reg))
612 * Enhanced Configuration Access Mechanism (ECAM)
614 * See PCI Express Base Specification, Revision 5.0, Version 1.0,
615 * Section 7.2.2, Table 7-1, p. 677.
617 #define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */
618 #define PCIE_ECAM_DEV_SHIFT 15 /* Device number */
619 #define PCIE_ECAM_FUNC_SHIFT 12 /* Function number */
621 #define PCIE_ECAM_BUS_MASK 0xff
622 #define PCIE_ECAM_DEV_MASK 0x1f
623 #define PCIE_ECAM_FUNC_MASK 0x7
624 #define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */
626 #define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT)
627 #define PCIE_ECAM_DEV(x) (((x) & PCIE_ECAM_DEV_MASK) << PCIE_ECAM_DEV_SHIFT)
628 #define PCIE_ECAM_FUNC(x) (((x) & PCIE_ECAM_FUNC_MASK) << PCIE_ECAM_FUNC_SHIFT)
629 #define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK)
631 #define PCIE_ECAM_OFFSET(bus, dev, func, where) \
632 (PCIE_ECAM_BUS(bus) | \
633 PCIE_ECAM_DEV(dev) | \
634 PCIE_ECAM_FUNC(func) | \
635 PCIE_ECAM_REG(where))
641 #ifdef CONFIG_SYS_PCI_64BIT
642 typedef u64 pci_addr_t;
643 typedef u64 pci_size_t;
645 typedef unsigned long pci_addr_t;
646 typedef unsigned long pci_size_t;
650 pci_addr_t bus_start; /* Start on the bus */
651 phys_addr_t phys_start; /* Start in physical address space */
652 pci_size_t size; /* Size */
653 unsigned long flags; /* Resource flags */
655 pci_addr_t bus_lower;
658 #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
659 #define PCI_REGION_IO 0x00000001 /* PCI IO space */
660 #define PCI_REGION_TYPE 0x00000001
661 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
663 #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
664 #define PCI_REGION_RO 0x00000200 /* Read-only memory */
666 static inline void pci_set_region(struct pci_region *reg,
667 pci_addr_t bus_start,
668 phys_addr_t phys_start,
670 unsigned long flags) {
671 reg->bus_start = bus_start;
672 reg->phys_start = phys_start;
677 typedef int pci_dev_t;
679 #define PCI_BUS(d) (((d) >> 16) & 0xff)
682 * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot
683 * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0.
684 * Please see the Linux header include/uapi/linux/pci.h for more details.
685 * This is relevant for the following macros:
686 * PCI_DEV, PCI_FUNC, PCI_DEVFN
687 * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with
688 * the remark from above (input is in bits 15-8 instead of 7-0.
690 #define PCI_DEV(d) (((d) >> 11) & 0x1f)
691 #define PCI_FUNC(d) (((d) >> 8) & 0x7)
692 #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
694 #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
695 #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
696 #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
697 #define PCI_ANY_ID (~0)
699 /* Convert from Linux format to U-Boot format */
700 #define PCI_TO_BDF(val) ((val) << 8)
702 struct pci_device_id {
703 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
704 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
705 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
706 unsigned long driver_data; /* Data private to the driver */
709 struct pci_controller;
711 struct pci_config_table {
712 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
713 unsigned int class; /* Class ID, or PCI_ANY_ID */
714 unsigned int bus; /* Bus number, or PCI_ANY_ID */
715 unsigned int dev; /* Device number, or PCI_ANY_ID */
716 unsigned int func; /* Function number, or PCI_ANY_ID */
718 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
719 struct pci_config_table *);
720 unsigned long priv[3];
723 extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
724 struct pci_config_table *);
725 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
726 struct pci_config_table *);
728 #define INDIRECT_TYPE_NO_PCIE_LINK 1
731 * Structure of a PCI controller (host bridge)
733 * With driver model this is dev_get_uclass_priv(bus)
735 * @skip_auto_config_until_reloc: true to avoid auto-config until U-Boot has
736 * relocated. Normally if PCI is used before relocation, this happens
737 * before relocation also. Some platforms set up static configuration in
738 * TPL/SPL to reduce code size and boot time, since these phases only know
739 * about a small subset of PCI devices. This is normally false.
741 struct pci_controller {
743 struct udevice *ctlr;
744 bool skip_auto_config_until_reloc;
749 volatile unsigned int *cfg_addr;
750 volatile unsigned char *cfg_data;
755 * TODO(sjg@chromium.org): With driver model we use struct
756 * pci_controller for both the controller and any bridge devices
757 * attached to it. But there is only one region list and it is in the
758 * top-level controller.
760 * This could be changed so that struct pci_controller is only used
761 * for PCI controllers and a separate UCLASS (or perhaps
762 * UCLASS_PCI_GENERIC) is used for bridges.
764 struct pci_region *regions;
767 struct pci_config_table *config_table;
769 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
771 /* Used by auto config */
772 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
775 #if defined(CONFIG_DM_PCI_COMPAT)
776 extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
777 pci_addr_t addr, unsigned long flags);
778 extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
779 phys_addr_t addr, unsigned long flags);
781 #define pci_phys_to_bus(dev, addr, flags) \
782 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
783 #define pci_bus_to_phys(dev, addr, flags) \
784 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
786 #define pci_virt_to_bus(dev, addr, flags) \
787 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
788 (virt_to_phys(addr)), (flags))
789 #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
790 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
794 #define pci_phys_to_mem(dev, addr) \
795 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
796 #define pci_mem_to_phys(dev, addr) \
797 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
798 #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
799 #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
801 #define pci_virt_to_mem(dev, addr) \
802 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
803 #define pci_mem_to_virt(dev, addr, len, map_flags) \
804 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
805 #define pci_virt_to_io(dev, addr) \
806 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
807 #define pci_io_to_virt(dev, addr, len, map_flags) \
808 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
810 /* For driver model these are defined in macros in pci_compat.c */
811 extern int pci_hose_read_config_byte(struct pci_controller *hose,
812 pci_dev_t dev, int where, u8 *val);
813 extern int pci_hose_read_config_word(struct pci_controller *hose,
814 pci_dev_t dev, int where, u16 *val);
815 extern int pci_hose_read_config_dword(struct pci_controller *hose,
816 pci_dev_t dev, int where, u32 *val);
817 extern int pci_hose_write_config_byte(struct pci_controller *hose,
818 pci_dev_t dev, int where, u8 val);
819 extern int pci_hose_write_config_word(struct pci_controller *hose,
820 pci_dev_t dev, int where, u16 val);
821 extern int pci_hose_write_config_dword(struct pci_controller *hose,
822 pci_dev_t dev, int where, u32 val);
825 void pciauto_region_init(struct pci_region *res);
826 void pciauto_region_align(struct pci_region *res, pci_size_t size);
827 void pciauto_config_init(struct pci_controller *hose);
830 * pciauto_region_allocate() - Allocate resources from a PCI resource region
832 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
833 * false, the result will be guaranteed to fit in 32 bits.
835 * @res: PCI region to allocate from
836 * @size: Amount of bytes to allocate
837 * @bar: Returns the PCI bus address of the allocated resource
838 * @supports_64bit: Whether to allow allocations above the 32-bit boundary
839 * Return: 0 if successful, -1 on failure
841 int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
842 pci_addr_t *bar, bool supports_64bit);
843 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
845 #if defined(CONFIG_DM_PCI_COMPAT)
846 extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
847 pci_dev_t dev, int where, u8 *val);
848 extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
849 pci_dev_t dev, int where, u16 *val);
850 extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
851 pci_dev_t dev, int where, u8 val);
852 extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
853 pci_dev_t dev, int where, u16 val);
855 extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
856 extern void pci_register_hose(struct pci_controller* hose);
857 extern struct pci_controller* pci_bus_to_hose(int bus);
858 extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
859 extern struct pci_controller *pci_get_hose_head(void);
861 extern int pci_hose_scan(struct pci_controller *hose);
862 extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
864 extern void pciauto_setup_device(struct pci_controller *hose,
865 pci_dev_t dev, int bars_num,
866 struct pci_region *mem,
867 struct pci_region *prefetch,
868 struct pci_region *io);
869 extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
870 pci_dev_t dev, int sub_bus);
871 extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
872 pci_dev_t dev, int sub_bus);
873 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
875 extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
876 extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
877 pci_dev_t pci_find_class(unsigned int find_class, int index);
879 extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
881 extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
883 extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
886 int pci_find_next_ext_capability(struct pci_controller *hose,
887 pci_dev_t dev, int start, int cap);
888 int pci_hose_find_ext_capability(struct pci_controller *hose,
889 pci_dev_t dev, int cap);
891 #endif /* defined(CONFIG_DM_PCI_COMPAT) */
893 const char * pci_class_str(u8 class);
894 int pci_last_busno(void);
896 #ifdef CONFIG_MPC85xx
897 extern void pci_mpc85xx_init (struct pci_controller *hose);
901 * pci_write_bar32() - Write the address of a BAR including control bits
903 * This writes a raw address (with control bits) to a bar. This can be used
904 * with devices which require hard-coded addresses, not part of the normal
905 * PCI enumeration process.
907 * This is only available if CONFIG_DM_PCI_COMPAT is enabled
909 * @hose: PCI hose to use
910 * @dev: PCI device to update
911 * @barnum: BAR number (0-5)
912 * @addr: BAR address with control bits
914 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
918 * pci_read_bar32() - read the address of a bar
920 * This is only available if CONFIG_DM_PCI_COMPAT is enabled
922 * @hose: PCI hose to use
923 * @dev: PCI device to inspect
924 * @barnum: BAR number (0-5)
925 * Return: address of the bar, masking out any control bits
927 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
930 * pci_hose_find_devices() - Find devices by vendor/device ID
932 * This is only available if CONFIG_DM_PCI_COMPAT is enabled
934 * @hose: PCI hose to search
935 * @busnum: Bus number to search
936 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
937 * @indexp: Pointer to device index to find. To find the first matching
938 * device, pass 0; to find the second, pass 1, etc. This
939 * parameter is decremented for each non-matching device so
940 * can be called repeatedly.
942 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
943 struct pci_device_id *ids, int *indexp);
945 /* Access sizes for PCI reads and writes */
955 * struct pci_child_plat - information stored about each PCI device
957 * Every device on a PCI bus has this per-child data.
959 * It can be accessed using dev_get_parent_plat(dev) if dev->parent is a
960 * PCI bus (i.e. UCLASS_PCI)
962 * @devfn: Encoded device and function index - see PCI_DEVFN()
963 * @vendor: PCI vendor ID (see pci_ids.h)
964 * @device: PCI device ID (see pci_ids.h)
965 * @class: PCI class, 3 bytes: (base, sub, prog-if)
966 * @is_virtfn: True for Virtual Function device
967 * @pfdev: Handle to Physical Function device
968 * @virtid: Virtual Function Index
970 struct pci_child_plat {
972 unsigned short vendor;
973 unsigned short device;
976 /* Variables for CONFIG_PCI_SRIOV */
978 struct udevice *pfdev;
982 /* PCI bus operations */
985 * read_config() - Read a PCI configuration value
987 * PCI buses must support reading and writing configuration values
988 * so that the bus can be scanned and its devices configured.
990 * Normally PCI_BUS(@bdf) is the same as @dev_seq(bus), but not always.
991 * If bridges exist it is possible to use the top-level bus to
992 * access a sub-bus. In that case @bus will be the top-level bus
993 * and PCI_BUS(bdf) will be a different (higher) value
995 * @bus: Bus to read from
996 * @bdf: Bus, device and function to read
997 * @offset: Byte offset within the device's configuration space
998 * @valuep: Place to put the returned value
1000 * @return 0 if OK, -ve on error
1002 int (*read_config)(const struct udevice *bus, pci_dev_t bdf,
1003 uint offset, ulong *valuep, enum pci_size_t size);
1005 * write_config() - Write a PCI configuration value
1007 * @bus: Bus to write to
1008 * @bdf: Bus, device and function to write
1009 * @offset: Byte offset within the device's configuration space
1010 * @value: Value to write
1011 * @size: Access size
1012 * @return 0 if OK, -ve on error
1014 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
1015 ulong value, enum pci_size_t size);
1018 /* Get access to a PCI bus' operations */
1019 #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
1022 * dm_pci_get_bdf() - Get the BDF value for a device
1024 * @dev: Device to check
1025 * Return: bus/device/function value (see PCI_BDF())
1027 pci_dev_t dm_pci_get_bdf(const struct udevice *dev);
1030 * pci_bind_bus_devices() - scan a PCI bus and bind devices
1032 * Scan a PCI bus looking for devices. Bind each one that is found. If
1033 * devices are already bound that match the scanned devices, just update the
1034 * child data so that the device can be used correctly (this happens when
1035 * the device tree describes devices we expect to see on the bus).
1037 * Devices that are bound in this way will use a generic PCI driver which
1038 * does nothing. The device can still be accessed but will not provide any
1041 * @bus: Bus containing devices to bind
1042 * Return: 0 if OK, -ve on error
1044 int pci_bind_bus_devices(struct udevice *bus);
1047 * pci_auto_config_devices() - configure bus devices ready for use
1049 * This works through all devices on a bus by scanning the driver model
1050 * data structures (normally these have been set up by pci_bind_bus_devices()
1053 * Space is allocated for each PCI base address register (BAR) so that the
1054 * devices are mapped into memory and I/O space ready for use.
1056 * @bus: Bus containing devices to bind
1057 * Return: 0 if OK, -ve on error
1059 int pci_auto_config_devices(struct udevice *bus);
1062 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
1064 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1065 * @devp: Returns the device for this address, if found
1066 * Return: 0 if OK, -ENODEV if not found
1068 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
1071 * pci_bus_find_devfn() - Find a device on a bus
1073 * @find_devfn: PCI device address (device and function only)
1074 * @devp: Returns the device for this address, if found
1075 * Return: 0 if OK, -ENODEV if not found
1077 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
1078 struct udevice **devp);
1081 * pci_find_first_device() - return the first available PCI device
1083 * This function and pci_find_first_device() allow iteration through all
1084 * available PCI devices on all buses. Assuming there are any, this will
1085 * return the first one.
1087 * @devp: Set to the first available device, or NULL if no more are left
1088 * or we got an error
1089 * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
1091 int pci_find_first_device(struct udevice **devp);
1094 * pci_find_next_device() - return the next available PCI device
1096 * Finds the next available PCI device after the one supplied, or sets @devp
1097 * to NULL if there are no more.
1099 * @devp: On entry, the last device returned. Set to the next available
1100 * device, or NULL if no more are left or we got an error
1101 * Return: 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
1103 int pci_find_next_device(struct udevice **devp);
1106 * pci_get_ff() - Returns a mask for the given access size
1108 * @size: Access size
1109 * Return: 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
1112 int pci_get_ff(enum pci_size_t size);
1115 * pci_bus_find_devices () - Find devices on a bus
1117 * @bus: Bus to search
1118 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1119 * @indexp: Pointer to device index to find. To find the first matching
1120 * device, pass 0; to find the second, pass 1, etc. This
1121 * parameter is decremented for each non-matching device so
1122 * can be called repeatedly.
1123 * @devp: Returns matching device if found
1124 * Return: 0 if found, -ENODEV if not
1126 int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
1127 int *indexp, struct udevice **devp);
1130 * pci_find_device_id() - Find a device on any bus
1132 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
1133 * @index: Index number of device to find, 0 for the first match, 1 for
1135 * @devp: Returns matching device if found
1136 * Return: 0 if found, -ENODEV if not
1138 int pci_find_device_id(const struct pci_device_id *ids, int index,
1139 struct udevice **devp);
1142 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
1144 * This probes the given bus which causes it to be scanned for devices. The
1145 * devices will be bound but not probed.
1147 * @hose specifies the PCI hose that will be used for the scan. This is
1148 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
1149 * in @bdf, and is a subordinate bus reachable from @hose.
1151 * @hose: PCI hose to scan
1152 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
1153 * Return: 0 if OK, -ve on error
1155 int dm_pci_hose_probe_bus(struct udevice *bus);
1158 * pci_bus_read_config() - Read a configuration value from a device
1160 * TODO(sjg@chromium.org): We should be able to pass just a device and have
1161 * it do the right thing. It would be good to have that function also.
1163 * @bus: Bus to read from
1164 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1165 * @offset: Register offset to read
1166 * @valuep: Place to put the returned value
1167 * @size: Access size
1168 * Return: 0 if OK, -ve on error
1170 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
1171 unsigned long *valuep, enum pci_size_t size);
1174 * pci_bus_write_config() - Write a configuration value to a device
1176 * @bus: Bus to write from
1177 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1178 * @offset: Register offset to write
1179 * @value: Value to write
1180 * @size: Access size
1181 * Return: 0 if OK, -ve on error
1183 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1184 unsigned long value, enum pci_size_t size);
1187 * pci_bus_clrset_config32() - Update a configuration value for a device
1189 * The register at @offset is updated to (oldvalue & ~clr) | set.
1191 * @bus: Bus to access
1192 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1193 * @offset: Register offset to update
1194 * @clr: Bits to clear
1196 * Return: 0 if OK, -ve on error
1198 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1202 * Driver model PCI config access functions. Use these in preference to others
1203 * when you have a valid device
1205 int dm_pci_read_config(const struct udevice *dev, int offset,
1206 unsigned long *valuep, enum pci_size_t size);
1208 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep);
1209 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep);
1210 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep);
1212 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1213 enum pci_size_t size);
1215 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1216 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1217 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1220 * These permit convenient read/modify/write on PCI configuration. The
1221 * register is updated to (oldvalue & ~clr) | set.
1223 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1224 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1225 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
1228 * The following functions provide access to the above without needing the
1229 * size parameter. We are trying to encourage the use of the 8/16/32-style
1230 * functions, rather than byte/word/dword. But both are supported.
1232 int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
1233 int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1234 int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1235 int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1236 int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1237 int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
1240 * pci_generic_mmap_write_config() - Generic helper for writing to
1241 * memory-mapped PCI configuration space.
1242 * @bus: Pointer to the PCI bus
1243 * @addr_f: Callback for calculating the config space address
1244 * @bdf: Identifies the PCI device to access
1245 * @offset: The offset into the device's configuration space
1246 * @value: The value to write
1247 * @size: Indicates the size of access to perform
1249 * Write the value @value of size @size from offset @offset within the
1250 * configuration space of the device identified by the bus, device & function
1251 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
1252 * responsible for calculating the CPU address of the respective configuration
1255 * Return: 0 on success, else -EINVAL
1257 int pci_generic_mmap_write_config(
1258 const struct udevice *bus,
1259 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
1264 enum pci_size_t size);
1267 * pci_generic_mmap_read_config() - Generic helper for reading from
1268 * memory-mapped PCI configuration space.
1269 * @bus: Pointer to the PCI bus
1270 * @addr_f: Callback for calculating the config space address
1271 * @bdf: Identifies the PCI device to access
1272 * @offset: The offset into the device's configuration space
1273 * @valuep: A pointer at which to store the read value
1274 * @size: Indicates the size of access to perform
1276 * Read a value of size @size from offset @offset within the configuration
1277 * space of the device identified by the bus, device & function numbers in @bdf
1278 * on the PCI bus @bus. The callback function @addr_f is responsible for
1279 * calculating the CPU address of the respective configuration space offset.
1281 * Return: 0 on success, else -EINVAL
1283 int pci_generic_mmap_read_config(
1284 const struct udevice *bus,
1285 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
1290 enum pci_size_t size);
1292 #if defined(CONFIG_PCI_SRIOV)
1294 * pci_sriov_init() - Scan Virtual Function devices
1296 * @pdev: Physical Function udevice handle
1297 * @vf_en: Number of Virtual Function devices to enable
1298 * Return: 0 on success, -ve on error
1300 int pci_sriov_init(struct udevice *pdev, int vf_en);
1303 * pci_sriov_get_totalvfs() - Get total available Virtual Function devices
1305 * @pdev: Physical Function udevice handle
1306 * Return: count on success, -ve on error
1308 int pci_sriov_get_totalvfs(struct udevice *pdev);
1311 #ifdef CONFIG_DM_PCI_COMPAT
1312 /* Compatibility with old naming */
1313 static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1316 return pci_write_config32(pcidev, offset, value);
1319 /* Compatibility with old naming */
1320 static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1323 return pci_write_config16(pcidev, offset, value);
1326 /* Compatibility with old naming */
1327 static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1330 return pci_write_config8(pcidev, offset, value);
1333 /* Compatibility with old naming */
1334 static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1337 return pci_read_config32(pcidev, offset, valuep);
1340 /* Compatibility with old naming */
1341 static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1344 return pci_read_config16(pcidev, offset, valuep);
1347 /* Compatibility with old naming */
1348 static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1351 return pci_read_config8(pcidev, offset, valuep);
1353 #endif /* CONFIG_DM_PCI_COMPAT */
1356 * dm_pciauto_config_device() - configure a device ready for use
1358 * Space is allocated for each PCI base address register (BAR) so that the
1359 * devices are mapped into memory and I/O space ready for use.
1361 * @dev: Device to configure
1362 * Return: 0 if OK, -ve on error
1364 int dm_pciauto_config_device(struct udevice *dev);
1367 * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1369 * Some PCI buses must always perform 32-bit reads. The data must then be
1370 * shifted and masked to reflect the required access size and offset. This
1371 * function performs this transformation.
1373 * @value: Value to transform (32-bit value read from @offset & ~3)
1374 * @offset: Register offset that was read
1375 * @size: Required size of the result
1376 * Return: the value that would have been obtained if the read had been
1377 * performed at the given offset with the correct size
1379 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1382 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1384 * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1385 * write the old 32-bit data must be read, updated with the required new data
1386 * and written back as a 32-bit value. This function performs the
1387 * transformation from the old value to the new value.
1389 * @value: Value to transform (32-bit value read from @offset & ~3)
1390 * @offset: Register offset that should be written
1391 * @size: Required size of the write
1392 * Return: the value that should be written as a 32-bit access to @offset & ~3.
1394 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1395 enum pci_size_t size);
1398 * pci_get_controller() - obtain the controller to use for a bus
1400 * @dev: Device to check
1401 * Return: pointer to the controller device for this bus
1403 struct udevice *pci_get_controller(struct udevice *dev);
1406 * pci_get_regions() - obtain pointers to all the region types
1408 * @dev: Device to check
1409 * @iop: Returns a pointer to the I/O region, or NULL if none
1410 * @memp: Returns a pointer to the memory region, or NULL if none
1411 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
1412 * Return: the number of non-NULL regions returned, normally 3
1414 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1415 struct pci_region **memp, struct pci_region **prefp);
1417 pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index);
1419 * dm_pci_write_bar32() - Write the address of a BAR
1421 * This writes a raw address to a bar
1423 * @dev: PCI device to update
1424 * @barnum: BAR number (0-5)
1425 * @addr: BAR address
1427 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1430 * dm_pci_read_bar32() - read a base address register from a device
1432 * @dev: Device to check
1433 * @barnum: Bar number to read (numbered from 0)
1434 * @return: value of BAR
1436 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum);
1439 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
1441 * @dev: Device containing the PCI address
1442 * @addr: PCI address to convert
1443 * @flags: Flags for the region type (PCI_REGION_...)
1444 * Return: physical address corresponding to that PCI bus address
1446 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1447 unsigned long flags);
1450 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1452 * @dev: Device containing the bus address
1453 * @addr: Physical address to convert
1454 * @flags: Flags for the region type (PCI_REGION_...)
1455 * Return: PCI bus address corresponding to that physical address
1457 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1458 unsigned long flags);
1461 * dm_pci_map_bar() - get a virtual address associated with a BAR region
1463 * Looks up a base address register and finds the physical memory address
1464 * that corresponds to it.
1465 * Can be used for 32b BARs 0-5 on type 0 functions and for 32b BARs 0-1 on
1467 * Can also be used on type 0 functions that support Enhanced Allocation for
1468 * 32b/64b BARs. Note that duplicate BEI entries are not supported.
1470 * @dev: Device to check
1471 * @bar: Bar register offset (PCI_BASE_ADDRESS_...)
1472 * @flags: Flags for the region type (PCI_REGION_...)
1473 * @return: pointer to the virtual address to use or 0 on error
1475 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
1478 * dm_pci_find_next_capability() - find a capability starting from an offset
1480 * Tell if a device supports a given PCI capability. Returns the
1481 * address of the requested capability structure within the device's
1482 * PCI configuration space or 0 in case the device does not support it.
1484 * Possible values for @cap:
1486 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1487 * %PCI_CAP_ID_PCIX PCI-X
1488 * %PCI_CAP_ID_EXP PCI Express
1489 * %PCI_CAP_ID_MSIX MSI-X
1491 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1493 * @dev: PCI device to query
1494 * @start: offset to start from
1495 * @cap: capability code
1496 * @return: capability address or 0 if not supported
1498 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
1501 * dm_pci_find_capability() - find a capability
1503 * Tell if a device supports a given PCI capability. Returns the
1504 * address of the requested capability structure within the device's
1505 * PCI configuration space or 0 in case the device does not support it.
1507 * Possible values for @cap:
1509 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1510 * %PCI_CAP_ID_PCIX PCI-X
1511 * %PCI_CAP_ID_EXP PCI Express
1512 * %PCI_CAP_ID_MSIX MSI-X
1514 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1516 * @dev: PCI device to query
1517 * @cap: capability code
1518 * @return: capability address or 0 if not supported
1520 int dm_pci_find_capability(struct udevice *dev, int cap);
1523 * dm_pci_find_next_ext_capability() - find an extended capability
1524 * starting from an offset
1526 * Tell if a device supports a given PCI express extended capability.
1527 * Returns the address of the requested extended capability structure
1528 * within the device's PCI configuration space or 0 in case the device
1529 * does not support it.
1531 * Possible values for @cap:
1533 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1534 * %PCI_EXT_CAP_ID_VC Virtual Channel
1535 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1536 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1538 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1540 * @dev: PCI device to query
1541 * @start: offset to start from
1542 * @cap: extended capability code
1543 * @return: extended capability address or 0 if not supported
1545 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
1548 * dm_pci_find_ext_capability() - find an extended capability
1550 * Tell if a device supports a given PCI express extended capability.
1551 * Returns the address of the requested extended capability structure
1552 * within the device's PCI configuration space or 0 in case the device
1553 * does not support it.
1555 * Possible values for @cap:
1557 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1558 * %PCI_EXT_CAP_ID_VC Virtual Channel
1559 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1560 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1562 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1564 * @dev: PCI device to query
1565 * @cap: extended capability code
1566 * @return: extended capability address or 0 if not supported
1568 int dm_pci_find_ext_capability(struct udevice *dev, int cap);
1571 * dm_pci_flr() - Perform FLR if the device suppoorts it
1573 * @dev: PCI device to reset
1574 * @return: 0 if OK, -ENOENT if FLR is not supported by dev
1576 int dm_pci_flr(struct udevice *dev);
1578 #define dm_pci_virt_to_bus(dev, addr, flags) \
1579 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1580 #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1581 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1584 #define dm_pci_phys_to_mem(dev, addr) \
1585 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1586 #define dm_pci_mem_to_phys(dev, addr) \
1587 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1588 #define dm_pci_phys_to_io(dev, addr) \
1589 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1590 #define dm_pci_io_to_phys(dev, addr) \
1591 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1593 #define dm_pci_virt_to_mem(dev, addr) \
1594 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1595 #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1596 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1597 #define dm_pci_virt_to_io(dev, addr) \
1598 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
1599 #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
1600 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
1603 * dm_pci_find_device() - find a device by vendor/device ID
1605 * @vendor: Vendor ID
1606 * @device: Device ID
1607 * @index: 0 to find the first match, 1 for second, etc.
1608 * @devp: Returns pointer to the device, if found
1609 * Return: 0 if found, -ve on error
1611 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1612 struct udevice **devp);
1615 * dm_pci_find_class() - find a device by class
1617 * @find_class: 3-byte (24-bit) class value to find
1618 * @index: 0 to find the first match, 1 for second, etc.
1619 * @devp: Returns pointer to the device, if found
1620 * Return: 0 if found, -ve on error
1622 int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1625 * struct pci_emul_uc_priv - holds info about an emulator device
1627 * There is always at most one emulator per client
1629 * @client: Client device if any, else NULL
1631 struct pci_emul_uc_priv {
1632 struct udevice *client;
1636 * struct dm_pci_emul_ops - PCI device emulator operations
1638 struct dm_pci_emul_ops {
1640 * read_config() - Read a PCI configuration value
1642 * @dev: Emulated device to read from
1643 * @offset: Byte offset within the device's configuration space
1644 * @valuep: Place to put the returned value
1645 * @size: Access size
1646 * @return 0 if OK, -ve on error
1648 int (*read_config)(const struct udevice *dev, uint offset,
1649 ulong *valuep, enum pci_size_t size);
1651 * write_config() - Write a PCI configuration value
1653 * @dev: Emulated device to write to
1654 * @offset: Byte offset within the device's configuration space
1655 * @value: Value to write
1656 * @size: Access size
1657 * @return 0 if OK, -ve on error
1659 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1660 enum pci_size_t size);
1662 * read_io() - Read a PCI I/O value
1664 * @dev: Emulated device to read from
1665 * @addr: I/O address to read
1666 * @valuep: Place to put the returned value
1667 * @size: Access size
1668 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1669 * other -ve value on error
1671 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1672 enum pci_size_t size);
1674 * write_io() - Write a PCI I/O value
1676 * @dev: Emulated device to write from
1677 * @addr: I/O address to write
1678 * @value: Value to write
1679 * @size: Access size
1680 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1681 * other -ve value on error
1683 int (*write_io)(struct udevice *dev, unsigned int addr,
1684 ulong value, enum pci_size_t size);
1686 * map_physmem() - Map a device into sandbox memory
1688 * @dev: Emulated device to map
1689 * @addr: Memory address, normally corresponding to a PCI BAR.
1690 * The device should have been configured to have a BAR
1692 * @lenp: On entry, the size of the area to map, On exit it is
1693 * updated to the size actually mapped, which may be less
1694 * if the device has less space
1695 * @ptrp: Returns a pointer to the mapped address. The device's
1696 * space can be accessed as @lenp bytes starting here
1697 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1698 * other -ve value on error
1700 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1701 unsigned long *lenp, void **ptrp);
1703 * unmap_physmem() - undo a memory mapping
1705 * This must be called after map_physmem() to undo the mapping.
1706 * Some devices can use this to check what has been written into
1707 * their mapped memory and perform an operations they require on it.
1708 * In this way, map/unmap can be used as a sort of handshake between
1709 * the emulated device and its users.
1711 * @dev: Emuated device to unmap
1712 * @vaddr: Mapped memory address, as passed to map_physmem()
1713 * @len: Size of area mapped, as returned by map_physmem()
1714 * @return 0 if OK, -ve on error
1716 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1720 /* Get access to a PCI device emulator's operations */
1721 #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1724 * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1726 * Searches for a suitable emulator for the given PCI bus device
1728 * @bus: PCI bus to search
1729 * @find_devfn: PCI device and function address (PCI_DEVFN())
1730 * @containerp: Returns container device if found
1731 * @emulp: Returns emulated device if found
1732 * Return: 0 if found, -ENODEV if not found
1734 int sandbox_pci_get_emul(const struct udevice *bus, pci_dev_t find_devfn,
1735 struct udevice **containerp, struct udevice **emulp);
1738 * sandbox_pci_get_client() - Find the client for an emulation device
1740 * @emul: Emulation device to check
1741 * @devp: Returns the client device emulated by this device
1742 * Return: 0 if OK, -ENOENT if the device has no client yet
1744 int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
1747 * board_pci_fixup_dev() - Board callback for PCI device fixups
1752 extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev);
1755 * PCI_DEVICE - macro used to describe a specific pci device
1756 * @vend: the 16 bit PCI Vendor ID
1757 * @dev: the 16 bit PCI Device ID
1759 * This macro is used to create a struct pci_device_id that matches a
1760 * specific device. The subvendor and subdevice fields will be set to
1763 #define PCI_DEVICE(vend, dev) \
1764 .vendor = (vend), .device = (dev), \
1765 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1768 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1769 * @vend: the 16 bit PCI Vendor ID
1770 * @dev: the 16 bit PCI Device ID
1771 * @subvend: the 16 bit PCI Subvendor ID
1772 * @subdev: the 16 bit PCI Subdevice ID
1774 * This macro is used to create a struct pci_device_id that matches a
1775 * specific device with subsystem information.
1777 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1778 .vendor = (vend), .device = (dev), \
1779 .subvendor = (subvend), .subdevice = (subdev)
1782 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1783 * @dev_class: the class, subclass, prog-if triple for this device
1784 * @dev_class_mask: the class mask for this device
1786 * This macro is used to create a struct pci_device_id that matches a
1787 * specific PCI class. The vendor, device, subvendor, and subdevice
1788 * fields will be set to PCI_ANY_ID.
1790 #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1791 .class = (dev_class), .class_mask = (dev_class_mask), \
1792 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1793 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1796 * PCI_VDEVICE - macro used to describe a specific pci device in short form
1797 * @vend: the vendor name
1798 * @dev: the 16 bit PCI Device ID
1800 * This macro is used to create a struct pci_device_id that matches a
1801 * specific PCI device. The subvendor, and subdevice fields will be set
1802 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1806 #define PCI_VDEVICE(vend, dev) \
1807 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1808 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1811 * struct pci_driver_entry - Matches a driver to its pci_device_id list
1812 * @driver: Driver to use
1813 * @match: List of match records for this driver, terminated by {}
1815 struct pci_driver_entry {
1816 struct driver *driver;
1817 const struct pci_device_id *match;
1820 #define U_BOOT_PCI_DEVICE(__name, __match) \
1821 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1822 .driver = llsym(struct driver, __name, driver), \
1826 #endif /* __ASSEMBLY__ */