1 /* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 1, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
25 /* The opcode table is an array of struct powerpc_opcode. */
29 /* The opcode name. */
32 /* The opcode itself. Those bits which will be filled in with
33 operands are zeroes. */
36 /* The opcode mask. This is used by the disassembler. This is a
37 mask containing ones indicating those bits which must match the
38 opcode field, and zeroes indicating those bits which need not
39 match (and are presumably filled in by operands). */
42 /* One bit flags for the opcode. These are used to indicate which
43 specific processors support the instructions. The defined values
47 /* An array of operand codes. Each code is an index into the
48 operand table. They appear in the order which the operands must
49 appear in assembly code, and are terminated by a zero. */
50 unsigned char operands[8];
53 /* The table itself is sorted by major opcode number, and is otherwise
54 in the order in which the disassembler should consider
56 extern const struct powerpc_opcode powerpc_opcodes[];
57 extern const int powerpc_num_opcodes;
59 /* Values defined for the flags field of a struct powerpc_opcode. */
61 /* Opcode is defined for the PowerPC architecture. */
62 #define PPC_OPCODE_PPC 1
64 /* Opcode is defined for the POWER (RS/6000) architecture. */
65 #define PPC_OPCODE_POWER 2
67 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
68 #define PPC_OPCODE_POWER2 4
70 /* Opcode is only defined on 32 bit architectures. */
71 #define PPC_OPCODE_32 8
73 /* Opcode is only defined on 64 bit architectures. */
74 #define PPC_OPCODE_64 0x10
76 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
77 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
78 but it also supports many additional POWER instructions. */
79 #define PPC_OPCODE_601 0x20
81 /* Opcode is supported in both the Power and PowerPC architectures
82 (ie, compiler's -mcpu=common or assembler's -mcom). */
83 #define PPC_OPCODE_COMMON 0x40
85 /* Opcode is supported for any Power or PowerPC platform (this is
86 for the assembler's -many option, and it eliminates duplicates). */
87 #define PPC_OPCODE_ANY 0x80
89 /* Opcode is supported as part of the 64-bit bridge. */
90 #define PPC_OPCODE_64_BRIDGE 0x100
92 /* Opcode is supported by Altivec Vector Unit */
93 #define PPC_OPCODE_ALTIVEC 0x200
95 /* Opcode is supported by PowerPC 403 processor. */
96 #define PPC_OPCODE_403 0x400
98 /* Opcode is supported by PowerPC BookE processor. */
99 #define PPC_OPCODE_BOOKE 0x800
101 /* Opcode is only supported by 64-bit PowerPC BookE processor. */
102 #define PPC_OPCODE_BOOKE64 0x1000
104 /* Opcode is supported by PowerPC 440 processor. */
105 #define PPC_OPCODE_440 0x2000
107 /* Opcode is only supported by Power4 architecture. */
108 #define PPC_OPCODE_POWER4 0x4000
110 /* Opcode isn't supported by Power4 architecture. */
111 #define PPC_OPCODE_NOPOWER4 0x8000
113 /* Opcode is only supported by POWERPC Classic architecture. */
114 #define PPC_OPCODE_CLASSIC 0x10000
116 /* Opcode is only supported by e500x2 Core. */
117 #define PPC_OPCODE_SPE 0x20000
119 /* Opcode is supported by e500x2 Integer select APU. */
120 #define PPC_OPCODE_ISEL 0x40000
122 /* Opcode is an e500 SPE floating point instruction. */
123 #define PPC_OPCODE_EFS 0x80000
125 /* Opcode is supported by branch locking APU. */
126 #define PPC_OPCODE_BRLOCK 0x100000
128 /* Opcode is supported by performance monitor APU. */
129 #define PPC_OPCODE_PMR 0x200000
131 /* Opcode is supported by cache locking APU. */
132 #define PPC_OPCODE_CACHELCK 0x400000
134 /* Opcode is supported by machine check APU. */
135 #define PPC_OPCODE_RFMCI 0x800000
137 /* A macro to extract the major opcode from an instruction. */
138 #define PPC_OP(i) (((i) >> 26) & 0x3f)
140 /* The operands table is an array of struct powerpc_operand. */
142 struct powerpc_operand
144 /* The number of bits in the operand. */
147 /* How far the operand is left shifted in the instruction. */
150 /* Insertion function. This is used by the assembler. To insert an
151 operand value into an instruction, check this field.
153 If it is NULL, execute
154 i |= (op & ((1 << o->bits) - 1)) << o->shift;
155 (i is the instruction which we are filling in, o is a pointer to
156 this structure, and op is the opcode value; this assumes twos
157 complement arithmetic).
159 If this field is not NULL, then simply call it with the
160 instruction and the operand value. It will return the new value
161 of the instruction. If the ERRMSG argument is not NULL, then if
162 the operand value is illegal, *ERRMSG will be set to a warning
163 string (the operand will be inserted in any case). If the
164 operand value is legal, *ERRMSG will be unchanged (most operands
165 can accept any value). */
166 unsigned long (*insert)
167 (unsigned long instruction, long op, int dialect, const char **errmsg);
169 /* Extraction function. This is used by the disassembler. To
170 extract this operand type from an instruction, check this field.
172 If it is NULL, compute
173 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
174 if ((o->flags & PPC_OPERAND_SIGNED) != 0
175 && (op & (1 << (o->bits - 1))) != 0)
177 (i is the instruction, o is a pointer to this structure, and op
178 is the result; this assumes twos complement arithmetic).
180 If this field is not NULL, then simply call it with the
181 instruction value. It will return the value of the operand. If
182 the INVALID argument is not NULL, *INVALID will be set to
183 non-zero if this operand type can not actually be extracted from
184 this operand (i.e., the instruction does not match). If the
185 operand is valid, *INVALID will not be changed. */
186 long (*extract) (unsigned long instruction, int dialect, int *invalid);
188 /* One bit syntax flags. */
192 /* Elements in the table are retrieved by indexing with values from
193 the operands field of the powerpc_opcodes table. */
195 extern const struct powerpc_operand powerpc_operands[];
197 /* Values defined for the flags field of a struct powerpc_operand. */
199 /* This operand takes signed values. */
200 #define PPC_OPERAND_SIGNED (01)
202 /* This operand takes signed values, but also accepts a full positive
203 range of values when running in 32 bit mode. That is, if bits is
204 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
205 this flag is ignored. */
206 #define PPC_OPERAND_SIGNOPT (02)
208 /* This operand does not actually exist in the assembler input. This
209 is used to support extended mnemonics such as mr, for which two
210 operands fields are identical. The assembler should call the
211 insert function with any op value. The disassembler should call
212 the extract function, ignore the return value, and check the value
213 placed in the valid argument. */
214 #define PPC_OPERAND_FAKE (04)
216 /* The next operand should be wrapped in parentheses rather than
217 separated from this one by a comma. This is used for the load and
218 store instructions which want their operands to look like
219 reg,displacement(reg)
221 #define PPC_OPERAND_PARENS (010)
223 /* This operand may use the symbolic names for the CR fields, which
225 lt 0 gt 1 eq 2 so 3 un 3
226 cr0 0 cr1 1 cr2 2 cr3 3
227 cr4 4 cr5 5 cr6 6 cr7 7
228 These may be combined arithmetically, as in cr2*4+gt. These are
229 only supported on the PowerPC, not the POWER. */
230 #define PPC_OPERAND_CR (020)
232 /* This operand names a register. The disassembler uses this to print
233 register names with a leading 'r'. */
234 #define PPC_OPERAND_GPR (040)
236 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
237 #define PPC_OPERAND_GPR_0 (0100)
239 /* This operand names a floating point register. The disassembler
240 prints these with a leading 'f'. */
241 #define PPC_OPERAND_FPR (0200)
243 /* This operand is a relative branch displacement. The disassembler
244 prints these symbolically if possible. */
245 #define PPC_OPERAND_RELATIVE (0400)
247 /* This operand is an absolute branch address. The disassembler
248 prints these symbolically if possible. */
249 #define PPC_OPERAND_ABSOLUTE (01000)
251 /* This operand is optional, and is zero if omitted. This is used for
252 example, in the optional BF field in the comparison instructions. The
253 assembler must count the number of operands remaining on the line,
254 and the number of operands remaining for the opcode, and decide
255 whether this operand is present or not. The disassembler should
256 print this operand out only if it is not zero. */
257 #define PPC_OPERAND_OPTIONAL (02000)
259 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
260 is omitted, then for the next operand use this operand value plus
261 1, ignoring the next operand field for the opcode. This wretched
262 hack is needed because the Power rotate instructions can take
263 either 4 or 5 operands. The disassembler should print this operand
264 out regardless of the PPC_OPERAND_OPTIONAL field. */
265 #define PPC_OPERAND_NEXT (04000)
267 /* This operand should be regarded as a negative number for the
268 purposes of overflow checking (i.e., the normal most negative
269 number is disallowed and one more than the normal most positive
270 number is allowed). This flag will only be set for a signed
272 #define PPC_OPERAND_NEGATIVE (010000)
274 /* This operand names a vector unit register. The disassembler
275 prints these with a leading 'v'. */
276 #define PPC_OPERAND_VR (020000)
278 /* This operand is for the DS field in a DS form instruction. */
279 #define PPC_OPERAND_DS (040000)
281 /* This operand is for the DQ field in a DQ form instruction. */
282 #define PPC_OPERAND_DQ (0100000)
284 /* The POWER and PowerPC assemblers use a few macros. We keep them
285 with the operands table for simplicity. The macro table is an
286 array of struct powerpc_macro. */
290 /* The macro name. */
293 /* The number of operands the macro takes. */
294 unsigned int operands;
296 /* One bit flags for the opcode. These are used to indicate which
297 specific processors support the instructions. The values are the
298 same as those for the struct powerpc_opcode flags field. */
301 /* A format string to turn the macro into a normal instruction.
302 Each %N in the string is replaced with operand number N (zero
307 extern const struct powerpc_macro powerpc_macros[];
308 extern const int powerpc_num_macros;