1 /* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 1, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 /* The opcode table is an array of struct powerpc_opcode. */
29 /* The opcode name. */
32 /* The opcode itself. Those bits which will be filled in with
33 operands are zeroes. */
36 /* The opcode mask. This is used by the disassembler. This is a
37 mask containing ones indicating those bits which must match the
38 opcode field, and zeroes indicating those bits which need not
39 match (and are presumably filled in by operands). */
42 /* One bit flags for the opcode. These are used to indicate which
43 specific processors support the instructions. The defined values
47 /* An array of operand codes. Each code is an index into the
48 operand table. They appear in the order which the operands must
49 appear in assembly code, and are terminated by a zero. */
50 unsigned char operands[8];
53 /* The table itself is sorted by major opcode number, and is otherwise
54 in the order in which the disassembler should consider
56 extern const struct powerpc_opcode powerpc_opcodes[];
57 extern const int powerpc_num_opcodes;
59 /* Values defined for the flags field of a struct powerpc_opcode. */
61 /* Opcode is defined for the PowerPC architecture. */
62 #define PPC_OPCODE_PPC (01)
64 /* Opcode is defined for the POWER (RS/6000) architecture. */
65 #define PPC_OPCODE_POWER (02)
67 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
68 #define PPC_OPCODE_POWER2 (04)
70 /* Opcode is only defined on 32 bit architectures. */
71 #define PPC_OPCODE_32 (010)
73 /* Opcode is only defined on 64 bit architectures. */
74 #define PPC_OPCODE_64 (020)
76 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
77 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
78 but it also supports many additional POWER instructions. */
79 #define PPC_OPCODE_601 (040)
81 /* Opcode is supported in both the Power and PowerPC architectures
82 (ie, compiler's -mcpu=common or assembler's -mcom). */
83 #define PPC_OPCODE_COMMON (0100)
85 /* Opcode is supported for any Power or PowerPC platform (this is
86 for the assembler's -many option, and it eliminates duplicates). */
87 #define PPC_OPCODE_ANY (0200)
89 /* Opcode is supported as part of the 64-bit bridge. */
90 #define PPC_OPCODE_64_BRIDGE (0400)
92 /* Opcode is supported by Altivec Vector Unit */
93 #define PPC_OPCODE_ALTIVEC (01000)
95 /* Opcode is supported by PowerPC 403 processor. */
96 #define PPC_OPCODE_403 (02000)
98 /* Opcode is supported by PowerPC BookE processor. */
99 #define PPC_OPCODE_BOOKE (04000)
101 /* Opcode is only supported by 64-bit PowerPC BookE processor. */
102 #define PPC_OPCODE_BOOKE64 (010000)
104 /* Opcode is only supported by Power4 architecture. */
105 #define PPC_OPCODE_POWER4 (020000)
107 /* Opcode isn't supported by Power4 architecture. */
108 #define PPC_OPCODE_NOPOWER4 (040000)
110 /* Opcode is only supported by POWERPC Classic architecture. */
111 #define PPC_OPCODE_CLASSIC (0100000)
113 /* Opcode is only supported by e500x2 Core. */
114 #define PPC_OPCODE_SPE (0200000)
116 /* Opcode is supported by e500x2 Integer select APU. */
117 #define PPC_OPCODE_ISEL (0400000)
119 /* Opcode is an e500 SPE floating point instruction. */
120 #define PPC_OPCODE_EFS (01000000)
122 /* Opcode is supported by branch locking APU. */
123 #define PPC_OPCODE_BRLOCK (02000000)
125 /* Opcode is supported by performance monitor APU. */
126 #define PPC_OPCODE_PMR (04000000)
128 /* Opcode is supported by cache locking APU. */
129 #define PPC_OPCODE_CACHELCK (010000000)
131 /* Opcode is supported by machine check APU. */
132 #define PPC_OPCODE_RFMCI (020000000)
134 /* A macro to extract the major opcode from an instruction. */
135 #define PPC_OP(i) (((i) >> 26) & 0x3f)
137 /* The operands table is an array of struct powerpc_operand. */
139 struct powerpc_operand
141 /* The number of bits in the operand. */
144 /* How far the operand is left shifted in the instruction. */
147 /* Insertion function. This is used by the assembler. To insert an
148 operand value into an instruction, check this field.
150 If it is NULL, execute
151 i |= (op & ((1 << o->bits) - 1)) << o->shift;
152 (i is the instruction which we are filling in, o is a pointer to
153 this structure, and op is the opcode value; this assumes twos
154 complement arithmetic).
156 If this field is not NULL, then simply call it with the
157 instruction and the operand value. It will return the new value
158 of the instruction. If the ERRMSG argument is not NULL, then if
159 the operand value is illegal, *ERRMSG will be set to a warning
160 string (the operand will be inserted in any case). If the
161 operand value is legal, *ERRMSG will be unchanged (most operands
162 can accept any value). */
163 unsigned long (*insert)
164 (unsigned long instruction, long op, int dialect, const char **errmsg);
166 /* Extraction function. This is used by the disassembler. To
167 extract this operand type from an instruction, check this field.
169 If it is NULL, compute
170 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
171 if ((o->flags & PPC_OPERAND_SIGNED) != 0
172 && (op & (1 << (o->bits - 1))) != 0)
174 (i is the instruction, o is a pointer to this structure, and op
175 is the result; this assumes twos complement arithmetic).
177 If this field is not NULL, then simply call it with the
178 instruction value. It will return the value of the operand. If
179 the INVALID argument is not NULL, *INVALID will be set to
180 non-zero if this operand type can not actually be extracted from
181 this operand (i.e., the instruction does not match). If the
182 operand is valid, *INVALID will not be changed. */
183 long (*extract) (unsigned long instruction, int dialect, int *invalid);
185 /* One bit syntax flags. */
189 /* Elements in the table are retrieved by indexing with values from
190 the operands field of the powerpc_opcodes table. */
192 extern const struct powerpc_operand powerpc_operands[];
194 /* Values defined for the flags field of a struct powerpc_operand. */
196 /* This operand takes signed values. */
197 #define PPC_OPERAND_SIGNED (01)
199 /* This operand takes signed values, but also accepts a full positive
200 range of values when running in 32 bit mode. That is, if bits is
201 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
202 this flag is ignored. */
203 #define PPC_OPERAND_SIGNOPT (02)
205 /* This operand does not actually exist in the assembler input. This
206 is used to support extended mnemonics such as mr, for which two
207 operands fields are identical. The assembler should call the
208 insert function with any op value. The disassembler should call
209 the extract function, ignore the return value, and check the value
210 placed in the valid argument. */
211 #define PPC_OPERAND_FAKE (04)
213 /* The next operand should be wrapped in parentheses rather than
214 separated from this one by a comma. This is used for the load and
215 store instructions which want their operands to look like
216 reg,displacement(reg)
218 #define PPC_OPERAND_PARENS (010)
220 /* This operand may use the symbolic names for the CR fields, which
222 lt 0 gt 1 eq 2 so 3 un 3
223 cr0 0 cr1 1 cr2 2 cr3 3
224 cr4 4 cr5 5 cr6 6 cr7 7
225 These may be combined arithmetically, as in cr2*4+gt. These are
226 only supported on the PowerPC, not the POWER. */
227 #define PPC_OPERAND_CR (020)
229 /* This operand names a register. The disassembler uses this to print
230 register names with a leading 'r'. */
231 #define PPC_OPERAND_GPR (040)
233 /* This operand names a floating point register. The disassembler
234 prints these with a leading 'f'. */
235 #define PPC_OPERAND_FPR (0100)
237 /* This operand is a relative branch displacement. The disassembler
238 prints these symbolically if possible. */
239 #define PPC_OPERAND_RELATIVE (0200)
241 /* This operand is an absolute branch address. The disassembler
242 prints these symbolically if possible. */
243 #define PPC_OPERAND_ABSOLUTE (0400)
245 /* This operand is optional, and is zero if omitted. This is used for
246 the optional BF and L fields in the comparison instructions. The
247 assembler must count the number of operands remaining on the line,
248 and the number of operands remaining for the opcode, and decide
249 whether this operand is present or not. The disassembler should
250 print this operand out only if it is not zero. */
251 #define PPC_OPERAND_OPTIONAL (01000)
253 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
254 is omitted, then for the next operand use this operand value plus
255 1, ignoring the next operand field for the opcode. This wretched
256 hack is needed because the Power rotate instructions can take
257 either 4 or 5 operands. The disassembler should print this operand
258 out regardless of the PPC_OPERAND_OPTIONAL field. */
259 #define PPC_OPERAND_NEXT (02000)
261 /* This operand should be regarded as a negative number for the
262 purposes of overflow checking (i.e., the normal most negative
263 number is disallowed and one more than the normal most positive
264 number is allowed). This flag will only be set for a signed
266 #define PPC_OPERAND_NEGATIVE (04000)
268 /* This operand names a vector unit register. The disassembler
269 prints these with a leading 'v'. */
270 #define PPC_OPERAND_VR (010000)
272 /* This operand is for the DS field in a DS form instruction. */
273 #define PPC_OPERAND_DS (020000)
275 /* This operand is for the DQ field in a DQ form instruction. */
276 #define PPC_OPERAND_DQ (040000)
278 /* The POWER and PowerPC assemblers use a few macros. We keep them
279 with the operands table for simplicity. The macro table is an
280 array of struct powerpc_macro. */
284 /* The macro name. */
287 /* The number of operands the macro takes. */
288 unsigned int operands;
290 /* One bit flags for the opcode. These are used to indicate which
291 specific processors support the instructions. The values are the
292 same as those for the struct powerpc_opcode flags field. */
295 /* A format string to turn the macro into a normal instruction.
296 Each %N in the string is replaced with operand number N (zero
301 extern const struct powerpc_macro powerpc_macros[];
302 extern const int powerpc_num_macros;