1 /* ppc.h -- Header file for PowerPC opcode table
2 Copyright 1994, 1995, 1999, 2000 Free Software Foundation, Inc.
3 Written by Ian Lance Taylor, Cygnus Support
5 This file is part of GDB, GAS, and the GNU binutils.
7 GDB, GAS, and the GNU binutils are free software; you can redistribute
8 them and/or modify them under the terms of the GNU General Public
9 License as published by the Free Software Foundation; either version
10 1, or (at your option) any later version.
12 GDB, GAS, and the GNU binutils are distributed in the hope that they
13 will be useful, but WITHOUT ANY WARRANTY; without even the implied
14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
15 the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this file; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 /* The opcode table is an array of struct powerpc_opcode. */
28 /* The opcode name. */
31 /* The opcode itself. Those bits which will be filled in with
32 operands are zeroes. */
35 /* The opcode mask. This is used by the disassembler. This is a
36 mask containing ones indicating those bits which must match the
37 opcode field, and zeroes indicating those bits which need not
38 match (and are presumably filled in by operands). */
41 /* One bit flags for the opcode. These are used to indicate which
42 specific processors support the instructions. The defined values
46 /* An array of operand codes. Each code is an index into the
47 operand table. They appear in the order which the operands must
48 appear in assembly code, and are terminated by a zero. */
49 unsigned char operands[8];
52 /* The table itself is sorted by major opcode number, and is otherwise
53 in the order in which the disassembler should consider
55 extern const struct powerpc_opcode powerpc_opcodes[];
56 extern const int powerpc_num_opcodes;
58 /* Values defined for the flags field of a struct powerpc_opcode. */
60 /* Opcode is defined for the PowerPC architecture. */
61 #define PPC_OPCODE_PPC (01)
63 /* Opcode is defined for the POWER (RS/6000) architecture. */
64 #define PPC_OPCODE_POWER (02)
66 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
67 #define PPC_OPCODE_POWER2 (04)
69 /* Opcode is only defined on 32 bit architectures. */
70 #define PPC_OPCODE_32 (010)
72 /* Opcode is only defined on 64 bit architectures. */
73 #define PPC_OPCODE_64 (020)
75 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
76 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
77 but it also supports many additional POWER instructions. */
78 #define PPC_OPCODE_601 (040)
80 /* Opcode is supported in both the Power and PowerPC architectures
81 (ie, compiler's -mcpu=common or assembler's -mcom). */
82 #define PPC_OPCODE_COMMON (0100)
84 /* Opcode is supported for any Power or PowerPC platform (this is
85 for the assembler's -many option, and it eliminates duplicates). */
86 #define PPC_OPCODE_ANY (0200)
88 /* Opcode is supported as part of the 64-bit bridge. */
89 #define PPC_OPCODE_64_BRIDGE (0400)
91 /* Opcode is supported by Altivec Vector Unit */
92 #define PPC_OPCODE_ALTIVEC (01000)
94 /* A macro to extract the major opcode from an instruction. */
95 #define PPC_OP(i) (((i) >> 26) & 0x3f)
97 /* The operands table is an array of struct powerpc_operand. */
99 struct powerpc_operand
101 /* The number of bits in the operand. */
104 /* How far the operand is left shifted in the instruction. */
107 /* Insertion function. This is used by the assembler. To insert an
108 operand value into an instruction, check this field.
110 If it is NULL, execute
111 i |= (op & ((1 << o->bits) - 1)) << o->shift;
112 (i is the instruction which we are filling in, o is a pointer to
113 this structure, and op is the opcode value; this assumes twos
114 complement arithmetic).
116 If this field is not NULL, then simply call it with the
117 instruction and the operand value. It will return the new value
118 of the instruction. If the ERRMSG argument is not NULL, then if
119 the operand value is illegal, *ERRMSG will be set to a warning
120 string (the operand will be inserted in any case). If the
121 operand value is legal, *ERRMSG will be unchanged (most operands
122 can accept any value). */
123 unsigned long (*insert) PARAMS ((unsigned long instruction, long op,
124 const char **errmsg));
126 /* Extraction function. This is used by the disassembler. To
127 extract this operand type from an instruction, check this field.
129 If it is NULL, compute
130 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
131 if ((o->flags & PPC_OPERAND_SIGNED) != 0
132 && (op & (1 << (o->bits - 1))) != 0)
134 (i is the instruction, o is a pointer to this structure, and op
135 is the result; this assumes twos complement arithmetic).
137 If this field is not NULL, then simply call it with the
138 instruction value. It will return the value of the operand. If
139 the INVALID argument is not NULL, *INVALID will be set to
140 non-zero if this operand type can not actually be extracted from
141 this operand (i.e., the instruction does not match). If the
142 operand is valid, *INVALID will not be changed. */
143 long (*extract) PARAMS ((unsigned long instruction, int *invalid));
145 /* One bit syntax flags. */
150 /* Elements in the table are retrieved by indexing with values from
151 the operands field of the powerpc_opcodes table. */
153 extern const struct powerpc_operand powerpc_operands[];
155 /* Values defined for the flags field of a struct powerpc_operand. */
157 /* This operand takes signed values. */
158 #define PPC_OPERAND_SIGNED (01)
160 /* This operand takes signed values, but also accepts a full positive
161 range of values when running in 32 bit mode. That is, if bits is
162 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
163 this flag is ignored. */
164 #define PPC_OPERAND_SIGNOPT (02)
166 /* This operand does not actually exist in the assembler input. This
167 is used to support extended mnemonics such as mr, for which two
168 operands fields are identical. The assembler should call the
169 insert function with any op value. The disassembler should call
170 the extract function, ignore the return value, and check the value
171 placed in the valid argument. */
172 #define PPC_OPERAND_FAKE (04)
174 /* The next operand should be wrapped in parentheses rather than
175 separated from this one by a comma. This is used for the load and
176 store instructions which want their operands to look like
177 reg,displacement(reg)
179 #define PPC_OPERAND_PARENS (010)
181 /* This operand may use the symbolic names for the CR fields, which
183 lt 0 gt 1 eq 2 so 3 un 3
184 cr0 0 cr1 1 cr2 2 cr3 3
185 cr4 4 cr5 5 cr6 6 cr7 7
186 These may be combined arithmetically, as in cr2*4+gt. These are
187 only supported on the PowerPC, not the POWER. */
188 #define PPC_OPERAND_CR (020)
190 /* This operand names a register. The disassembler uses this to print
191 register names with a leading 'r'. */
192 #define PPC_OPERAND_GPR (040)
194 /* This operand names a floating point register. The disassembler
195 prints these with a leading 'f'. */
196 #define PPC_OPERAND_FPR (0100)
198 /* This operand is a relative branch displacement. The disassembler
199 prints these symbolically if possible. */
200 #define PPC_OPERAND_RELATIVE (0200)
202 /* This operand is an absolute branch address. The disassembler
203 prints these symbolically if possible. */
204 #define PPC_OPERAND_ABSOLUTE (0400)
206 /* This operand is optional, and is zero if omitted. This is used for
207 the optional BF and L fields in the comparison instructions. The
208 assembler must count the number of operands remaining on the line,
209 and the number of operands remaining for the opcode, and decide
210 whether this operand is present or not. The disassembler should
211 print this operand out only if it is not zero. */
212 #define PPC_OPERAND_OPTIONAL (01000)
214 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
215 is omitted, then for the next operand use this operand value plus
216 1, ignoring the next operand field for the opcode. This wretched
217 hack is needed because the Power rotate instructions can take
218 either 4 or 5 operands. The disassembler should print this operand
219 out regardless of the PPC_OPERAND_OPTIONAL field. */
220 #define PPC_OPERAND_NEXT (02000)
222 /* This operand should be regarded as a negative number for the
223 purposes of overflow checking (i.e., the normal most negative
224 number is disallowed and one more than the normal most positive
225 number is allowed). This flag will only be set for a signed
227 #define PPC_OPERAND_NEGATIVE (04000)
229 /* This operand names a vector unit register. The disassembler
230 prints these with a leading 'v'. */
231 #define PPC_OPERAND_VR (010000)
234 /* The POWER and PowerPC assemblers use a few macros. We keep them
235 with the operands table for simplicity. The macro table is an
236 array of struct powerpc_macro. */
240 /* The macro name. */
243 /* The number of operands the macro takes. */
244 unsigned int operands;
246 /* One bit flags for the opcode. These are used to indicate which
247 specific processors support the instructions. The values are the
248 same as those for the struct powerpc_opcode flags field. */
251 /* A format string to turn the macro into a normal instruction.
252 Each %N in the string is replaced with operand number N (zero
257 extern const struct powerpc_macro powerpc_macros[];
258 extern const int powerpc_num_macros;