1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright (C) 1993-2014 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version 3,
11 or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING3. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21 MA 02110-1301, USA. */
28 /* These are bit masks and shift counts to use to access the various
29 fields of an instruction. To retrieve the X field of an
30 instruction, use the expression
31 (i >> OP_SH_X) & OP_MASK_X
32 To set the same field (to j), use
33 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
35 Make sure you use fields that are appropriate for the instruction,
38 The 'i' format uses OP, RS, RT and IMMEDIATE.
40 The 'j' format uses OP and TARGET.
42 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
44 The 'b' format uses OP, RS, RT and DELTA.
46 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
48 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
50 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
51 breakpoint instruction are not defined; Kane says the breakpoint
52 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
53 only use ten bits). An optional two-operand form of break/sdbbp
54 allows the lower ten bits to be set too, and MIPS32 and later
55 architectures allow 20 bits to be set with a signal operand
58 The syscall instruction uses CODE20.
60 The general coprocessor instructions use COPZ. */
62 #define OP_MASK_OP 0x3f
64 #define OP_MASK_RS 0x1f
66 #define OP_MASK_FR 0x1f
68 #define OP_MASK_FMT 0x1f
70 #define OP_MASK_BCC 0x7
72 #define OP_MASK_CODE 0x3ff
74 #define OP_MASK_CODE2 0x3ff
76 #define OP_MASK_RT 0x1f
78 #define OP_MASK_FT 0x1f
80 #define OP_MASK_CACHE 0x1f
81 #define OP_SH_CACHE 16
82 #define OP_MASK_RD 0x1f
84 #define OP_MASK_FS 0x1f
86 #define OP_MASK_PREFX 0x1f
87 #define OP_SH_PREFX 11
88 #define OP_MASK_CCC 0x7
90 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
91 #define OP_SH_CODE20 6
92 #define OP_MASK_SHAMT 0x1f
94 #define OP_MASK_EXTLSB OP_MASK_SHAMT
95 #define OP_SH_EXTLSB OP_SH_SHAMT
96 #define OP_MASK_STYPE OP_MASK_SHAMT
97 #define OP_SH_STYPE OP_SH_SHAMT
98 #define OP_MASK_FD 0x1f
100 #define OP_MASK_TARGET 0x3ffffff
101 #define OP_SH_TARGET 0
102 #define OP_MASK_COPZ 0x1ffffff
104 #define OP_MASK_IMMEDIATE 0xffff
105 #define OP_SH_IMMEDIATE 0
106 #define OP_MASK_DELTA 0xffff
107 #define OP_SH_DELTA 0
108 #define OP_MASK_FUNCT 0x3f
109 #define OP_SH_FUNCT 0
110 #define OP_MASK_SPEC 0x3f
112 #define OP_SH_LOCC 8 /* FP condition code. */
113 #define OP_SH_HICC 18 /* FP condition code. */
114 #define OP_MASK_CC 0x7
115 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
116 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
117 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
118 #define OP_MASK_COP1SPEC 0xf
119 #define OP_MASK_COP1SCLR 0x4
120 #define OP_MASK_COP1CMP 0x3
121 #define OP_SH_COP1CMP 4
122 #define OP_SH_FORMAT 21 /* FP short format field. */
123 #define OP_MASK_FORMAT 0x7
124 #define OP_SH_TRUE 16
125 #define OP_MASK_TRUE 0x1
127 #define OP_MASK_GE 0x01
128 #define OP_SH_UNSIGNED 16
129 #define OP_MASK_UNSIGNED 0x1
130 #define OP_SH_HINT 16
131 #define OP_MASK_HINT 0x1f
132 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
133 #define OP_MASK_MMI 0x3f
134 #define OP_SH_MMISUB 6
135 #define OP_MASK_MMISUB 0x1f
136 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
137 #define OP_SH_PERFREG 1
138 #define OP_SH_SEL 0 /* Coprocessor select field. */
139 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
140 #define OP_SH_CODE19 6 /* 19 bit wait code. */
141 #define OP_MASK_CODE19 0x7ffff
143 #define OP_MASK_ALN 0x7
144 #define OP_SH_VSEL 21
145 #define OP_MASK_VSEL 0x1f
146 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
147 but 0x8-0xf don't select bytes. */
148 #define OP_SH_VECBYTE 22
149 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
150 #define OP_SH_VECALIGN 21
151 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
152 #define OP_SH_INSMSB 11
153 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
154 #define OP_SH_EXTMSBD 11
157 #define OP_SH_DSPACC 11
158 #define OP_MASK_DSPACC 0x3
159 #define OP_SH_DSPACC_S 21
160 #define OP_MASK_DSPACC_S 0x3
161 #define OP_SH_DSPSFT 20
162 #define OP_MASK_DSPSFT 0x3f
163 #define OP_SH_DSPSFT_7 19
164 #define OP_MASK_DSPSFT_7 0x7f
166 #define OP_MASK_SA3 0x7
168 #define OP_MASK_SA4 0xf
169 #define OP_SH_IMM8 16
170 #define OP_MASK_IMM8 0xff
171 #define OP_SH_IMM10 16
172 #define OP_MASK_IMM10 0x3ff
173 #define OP_SH_WRDSP 11
174 #define OP_MASK_WRDSP 0x3f
175 #define OP_SH_RDDSP 16
176 #define OP_MASK_RDDSP 0x3f
178 #define OP_MASK_BP 0x3
182 #define OP_MASK_MT_U 0x1
184 #define OP_MASK_MT_H 0x1
185 #define OP_SH_MTACC_T 18
186 #define OP_MASK_MTACC_T 0x3
187 #define OP_SH_MTACC_D 13
188 #define OP_MASK_MTACC_D 0x3
191 #define OP_MASK_3BITPOS 0x7
192 #define OP_SH_3BITPOS 12
193 #define OP_MASK_OFFSET12 0xfff
194 #define OP_SH_OFFSET12 0
196 #define OP_OP_COP0 0x10
197 #define OP_OP_COP1 0x11
198 #define OP_OP_COP2 0x12
199 #define OP_OP_COP3 0x13
200 #define OP_OP_LWC1 0x31
201 #define OP_OP_LWC2 0x32
202 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
203 #define OP_OP_LDC1 0x35
204 #define OP_OP_LDC2 0x36
205 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
206 #define OP_OP_SWC1 0x39
207 #define OP_OP_SWC2 0x3a
208 #define OP_OP_SWC3 0x3b
209 #define OP_OP_SDC1 0x3d
210 #define OP_OP_SDC2 0x3e
211 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
214 #define OP_MASK_CODE10 0x3ff
215 #define OP_SH_CODE10 11
217 /* Values in the 'VSEL' field. */
218 #define MDMX_FMTSEL_IMM_QH 0x1d
219 #define MDMX_FMTSEL_IMM_OB 0x1e
220 #define MDMX_FMTSEL_VEC_QH 0x15
221 #define MDMX_FMTSEL_VEC_OB 0x16
225 #define OP_MASK_UDI1 0x1f
227 #define OP_MASK_UDI2 0x3ff
229 #define OP_MASK_UDI3 0x7fff
231 #define OP_MASK_UDI4 0xfffff
234 #define OP_SH_BBITIND 16
235 #define OP_MASK_BBITIND 0x1f
236 #define OP_SH_CINSPOS 6
237 #define OP_MASK_CINSPOS 0x1f
238 #define OP_SH_CINSLM1 11
239 #define OP_MASK_CINSLM1 0x1f
241 #define OP_MASK_SEQI 0x3ff
244 #define OP_SH_OFFSET_A 6
245 #define OP_MASK_OFFSET_A 0xff
246 #define OP_SH_OFFSET_B 3
247 #define OP_MASK_OFFSET_B 0xff
248 #define OP_SH_OFFSET_C 6
249 #define OP_MASK_OFFSET_C 0x1ff
251 #define OP_MASK_RZ 0x1f
253 #define OP_MASK_FZ 0x1f
255 /* Every MICROMIPSOP_X definition requires a corresponding OP_X
256 definition, and vice versa. This simplifies various parts
257 of the operand handling in GAS. The fields below only exist
258 in the microMIPS encoding, so define each one to have an empty
260 #define OP_MASK_TRAP 0
262 #define OP_MASK_OFFSET10 0
263 #define OP_SH_OFFSET10 0
264 #define OP_MASK_RS3 0
292 #define OP_MASK_IMMA 0
294 #define OP_MASK_IMMB 0
296 #define OP_MASK_IMMC 0
298 #define OP_MASK_IMMF 0
300 #define OP_MASK_IMMG 0
302 #define OP_MASK_IMMH 0
304 #define OP_MASK_IMMI 0
306 #define OP_MASK_IMMJ 0
308 #define OP_MASK_IMML 0
310 #define OP_MASK_IMMM 0
312 #define OP_MASK_IMMN 0
314 #define OP_MASK_IMMO 0
316 #define OP_MASK_IMMP 0
318 #define OP_MASK_IMMQ 0
320 #define OP_MASK_IMMU 0
322 #define OP_MASK_IMMW 0
324 #define OP_MASK_IMMX 0
326 #define OP_MASK_IMMY 0
329 /* Enhanced VA Scheme */
330 #define OP_SH_EVAOFFSET 7
331 #define OP_MASK_EVAOFFSET 0x1ff
333 /* Enumerates the various types of MIPS operand. */
334 enum mips_operand_type {
335 /* Described by mips_int_operand. */
338 /* Described by mips_mapped_int_operand. */
341 /* Described by mips_msb_operand. */
344 /* Described by mips_reg_operand. */
347 /* Like OP_REG, but can be omitted if the register is the same as the
351 /* Described by mips_reg_pair_operand. */
354 /* Described by mips_pcrel_operand. */
357 /* A performance register. The field is 5 bits in size, but the supported
358 values are much more restricted. */
361 /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts
362 as a normal 9-bit signed offset that is multiplied by four, but there
363 are four special cases:
371 /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two
372 5-bit register fields, both of which must be set to the destination
376 /* A register list for a microMIPS LWM or SWM instruction. The operand
377 size determines whether the 16-bit or 32-bit encoding is required. */
380 /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */
383 /* The register list and frame size for a MIPS16 SAVE or RESTORE
385 OP_SAVE_RESTORE_LIST,
387 /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:
391 0EEE0 8 copies of $vN[E], OB format
392 0EE01 4 copies of $vN[E], QH format
393 10110 all 8 elements of $vN, OB format
394 10101 all 4 elements of $vN, QH format
395 11110 8 copies of immediate N, OB format
396 11101 4 copies of immediate N, QH format. */
399 /* A register operand that must match the destination register. */
402 /* A register operand that must match the previous register. */
405 /* $pc, which has no encoding in the architectural instruction. */
408 /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
412 /* Like OP_VU0_SUFFIX, but used when the operand's value has already
413 been set. Any suffix used here must match the previous value. */
416 /* An index selected by an integer, e.g. [1]. */
419 /* An index selected by a register, e.g. [$2]. */
423 /* Enumerates the types of MIPS register. */
424 enum mips_reg_operand_type {
425 /* General registers $0-$31. Software names like $at can also be used. */
428 /* Floating-point registers $f0-$f31. */
431 /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes
432 can also be written $fcc0-$fcc7. */
435 /* FPRs used in a vector capacity. They can be written $f0-$f31
436 or $v0-$v31, although the latter form is not used for the VR5400
437 vector instructions. */
440 /* DSP accumulator registers $ac0-$ac3. */
443 /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can
444 also be used in some contexts. */
447 /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
448 also be used in some contexts. */
451 /* Floating-point registers $vf0-$vf31. */
454 /* Integer registers $vi0-$vi31. */
457 /* R5900 VU0 registers $I, $Q, $R and $ACC. */
463 /* MSA registers $w0-$w31. */
466 /* MSA control registers $0-$31. */
470 /* Base class for all operands. */
473 /* The type of the operand. */
474 enum mips_operand_type type;
476 /* The operand occupies SIZE bits of the instruction, starting at LSB. */
481 /* Describes an integer operand with a regular encoding pattern. */
482 struct mips_int_operand
484 struct mips_operand root;
486 /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.
487 The cyclically previous field value encodes 1 << SHIFT less than that,
490 - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,
493 - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is
494 shifted left two places.
496 - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except
499 - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */
500 unsigned int max_val;
504 /* True if the operand should be printed as hex rather than decimal. */
505 bfd_boolean print_hex;
508 /* Uses a lookup table to describe a small integer operand. */
509 struct mips_mapped_int_operand
511 struct mips_operand root;
513 /* Maps each encoding value to the integer that it represents. */
516 /* True if the operand should be printed as hex rather than decimal. */
517 bfd_boolean print_hex;
520 /* An operand that encodes the most significant bit position of a bitfield.
521 Given a bitfield that spans bits [MSB, LSB], some operands of this type
522 encode MSB directly while others encode MSB - LSB. Each operand of this
523 type is preceded by an integer operand that specifies LSB.
525 The assembly form varies between instructions. For some instructions,
526 such as EXT, the operand is written as the bitfield size. For others,
527 such as EXTS, it is written in raw MSB - LSB form. */
528 struct mips_msb_operand
530 struct mips_operand root;
532 /* The assembly-level operand encoded by a field value of 0. */
535 /* True if the operand encodes MSB directly, false if it encodes
539 /* The maximum value of MSB + 1. */
543 /* Describes a single register operand. */
544 struct mips_reg_operand
546 struct mips_operand root;
548 /* The type of register. */
549 enum mips_reg_operand_type reg_type;
551 /* If nonnull, REG_MAP[N] gives the register associated with encoding N,
552 otherwise the encoding is the same as the register number. */
553 const unsigned char *reg_map;
556 /* Describes an operand that encodes a pair of registers. */
557 struct mips_reg_pair_operand
559 struct mips_operand root;
561 /* The type of register. */
562 enum mips_reg_operand_type reg_type;
564 /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */
565 unsigned char *reg1_map;
566 unsigned char *reg2_map;
569 /* Describes an operand that is calculated relative to a base PC.
570 The base PC is usually the address of the following instruction,
571 but the rules for MIPS16 instructions like ADDIUPC are more complicated. */
572 struct mips_pcrel_operand
574 /* Encodes the offset. */
575 struct mips_int_operand root;
577 /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',
578 which is then added to the offset encoded by ROOT. */
579 unsigned int align_log2 : 8;
581 /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
582 reinstated. This is true for jumps and branches and false for
583 PC-relative data instructions. */
584 unsigned int include_isa_bit : 1;
586 /* If FLIP_ISA_BIT, the ISA bit of the result is inverted.
587 This is true for JALX and false otherwise. */
588 unsigned int flip_isa_bit : 1;
591 /* Return true if the assembly syntax allows OPERAND to be omitted. */
593 static inline bfd_boolean
594 mips_optional_operand_p (const struct mips_operand *operand)
596 return (operand->type == OP_OPTIONAL_REG
597 || operand->type == OP_REPEAT_PREV_REG);
600 /* Return a version of INSN in which the field specified by OPERAND
603 static inline unsigned int
604 mips_insert_operand (const struct mips_operand *operand, unsigned int insn,
609 mask = (1 << operand->size) - 1;
610 insn &= ~(mask << operand->lsb);
611 insn |= (uval & mask) << operand->lsb;
615 /* Extract OPERAND from instruction INSN. */
617 static inline unsigned int
618 mips_extract_operand (const struct mips_operand *operand, unsigned int insn)
620 return (insn >> operand->lsb) & ((1 << operand->size) - 1);
623 /* UVAL is the value encoded by OPERAND. Return it in signed form. */
626 mips_signed_operand (const struct mips_operand *operand, unsigned int uval)
628 unsigned int sign_bit, mask;
630 mask = (1 << operand->size) - 1;
631 sign_bit = 1 << (operand->size - 1);
632 return ((uval + sign_bit) & mask) - sign_bit;
635 /* Return the integer that OPERAND encodes as UVAL. */
638 mips_decode_int_operand (const struct mips_int_operand *operand,
641 uval |= (operand->max_val - uval) & -(1 << operand->root.size);
642 uval += operand->bias;
643 uval <<= operand->shift;
647 /* Return the maximum value that can be encoded by OPERAND. */
650 mips_int_operand_max (const struct mips_int_operand *operand)
652 return (operand->max_val + operand->bias) << operand->shift;
655 /* Return the minimum value that can be encoded by OPERAND. */
658 mips_int_operand_min (const struct mips_int_operand *operand)
662 mask = (1 << operand->root.size) - 1;
663 return mips_int_operand_max (operand) - (mask << operand->shift);
666 /* Return the register that OPERAND encodes as UVAL. */
669 mips_decode_reg_operand (const struct mips_reg_operand *operand,
672 if (operand->reg_map)
673 uval = operand->reg_map[uval];
677 /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
678 Return the address that it encodes. */
680 static inline bfd_vma
681 mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand,
682 bfd_vma base_pc, unsigned int uval)
686 addr = base_pc & -(1 << operand->align_log2);
687 addr += mips_decode_int_operand (&operand->root, uval);
688 if (operand->include_isa_bit)
690 if (operand->flip_isa_bit)
695 /* This structure holds information for a particular instruction. */
699 /* The name of the instruction. */
701 /* A string describing the arguments for this instruction. */
703 /* The basic opcode for the instruction. When assembling, this
704 opcode is modified by the arguments to produce the actual opcode
705 that is used. If pinfo is INSN_MACRO, then this is 0. */
707 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
708 relevant portions of the opcode when disassembling. If the
709 actual opcode anded with the match field equals the opcode field,
710 then we have found the correct instruction. If pinfo is
711 INSN_MACRO, then this field is the macro identifier. */
713 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
714 of bits describing the instruction, notably any relevant hazard
717 /* A collection of additional bits describing the instruction. */
718 unsigned long pinfo2;
719 /* A collection of bits describing the instruction sets of which this
720 instruction or macro is a member. */
721 unsigned long membership;
722 /* A collection of bits describing the ASE of which this instruction
723 or macro is a member. */
725 /* A collection of bits describing the instruction sets of which this
726 instruction or macro is not a member. */
727 unsigned long exclusions;
730 /* These are the characters which may appear in the args field of an
731 instruction. They appear in the order in which the fields appear
732 when the instruction is used. Commas and parentheses in the args
733 string are ignored when assembling, and written into the output
736 Each of these characters corresponds to a mask field defined above.
738 "1" 5 bit sync type (OP_*_STYPE)
739 "<" 5 bit shift amount (OP_*_SHAMT)
740 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
741 "a" 26 bit target address (OP_*_TARGET)
742 "+i" likewise, but flips bit 0
743 "b" 5 bit base register (OP_*_RS)
744 "c" 10 bit breakpoint code (OP_*_CODE)
745 "d" 5 bit destination register specifier (OP_*_RD)
746 "h" 5 bit prefx hint (OP_*_PREFX)
747 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
748 "j" 16 bit signed immediate (OP_*_DELTA)
749 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
750 "o" 16 bit signed offset (OP_*_DELTA)
751 "p" 16 bit PC relative branch target address (OP_*_DELTA)
752 "q" 10 bit extra breakpoint code (OP_*_CODE2)
753 "r" 5 bit same register used as both source and target (OP_*_RS)
754 "s" 5 bit source register specifier (OP_*_RS)
755 "t" 5 bit target register (OP_*_RT)
756 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
757 "v" 5 bit same register used as both source and destination (OP_*_RS)
758 "w" 5 bit same register used as both target and destination (OP_*_RT)
759 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
760 (used by clo and clz)
761 "C" 25 bit coprocessor function code (OP_*_COPZ)
762 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
763 "J" 19 bit wait function code (OP_*_CODE19)
764 "x" accept and ignore register name
765 "z" must be zero register
766 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
767 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
768 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
769 microMIPS compatibility).
770 Enforces: 0 <= pos < 32.
771 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
772 Requires that "+A" or "+E" occur first to set position.
773 Enforces: 0 < (pos+size) <= 32.
774 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
775 Requires that "+A" or "+E" occur first to set position.
776 Enforces: 0 < (pos+size) <= 32.
777 (Also used by "dext" w/ different limits, but limits for
778 that are checked by the M_DEXT macro.)
779 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
780 Enforces: 32 <= pos < 64.
781 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
782 Requires that "+A" or "+E" occur first to set position.
783 Enforces: 32 < (pos+size) <= 64.
784 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
785 Requires that "+A" or "+E" occur first to set position.
786 Enforces: 32 < (pos+size) <= 64.
787 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
788 Requires that "+A" or "+E" occur first to set position.
789 Enforces: 32 < (pos+size) <= 64.
791 Floating point instructions:
792 "D" 5 bit destination register (OP_*_FD)
793 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
794 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
795 "S" 5 bit fs source 1 register (OP_*_FS)
796 "T" 5 bit ft source 2 register (OP_*_FT)
797 "R" 5 bit fr source 3 register (OP_*_FR)
798 "V" 5 bit same register used as floating source and destination (OP_*_FS)
799 "W" 5 bit same register used as floating target and destination (OP_*_FT)
801 Coprocessor instructions:
802 "E" 5 bit target register (OP_*_RT)
803 "G" 5 bit destination register (OP_*_RD)
804 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
805 "P" 5 bit performance-monitor register (OP_*_PERFREG)
806 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
807 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
810 "A" General 32 bit expression
811 "I" 32 bit immediate (value placed in imm_expr).
812 "F" 64 bit floating point constant in .rdata
813 "L" 64 bit floating point constant in .lit8
814 "f" 32 bit floating point constant
815 "l" 32 bit floating point constant in .lit4
817 MDMX and VR5400 instruction operands (note that while these use the
818 FP register fields, the MDMX instructions accept both $fN and $vN names
820 "O" alignment offset (OP_*_ALN)
821 "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
822 "X" destination register (OP_*_FD)
823 "Y" source register (OP_*_FS)
824 "Z" source register (OP_*_FT)
826 R5900 VU0 Macromode instructions:
827 "+5" 5 bit floating point register (FD)
828 "+6" 5 bit floating point register (FS)
829 "+7" 5 bit floating point register (FT)
830 "+8" 5 bit integer register (FD)
831 "+9" 5 bit integer register (FS)
832 "+0" 5 bit integer register (FT)
833 "+K" match an existing 4-bit channel mask starting at bit 21
834 "+L" 2-bit channel index starting at bit 21
835 "+M" 2-bit channel index starting at bit 23
836 "+N" match an existing 2-bit channel index starting at bit 0
837 "+f" 15 bit immediate for VCALLMS
838 "+g" 5 bit signed immediate for VIADDI
839 "+m" $ACC register (syntax only)
840 "+q" $Q register (syntax only)
841 "+r" $R register (syntax only)
842 "+y" $I register (syntax only)
843 "#+" "++" decorator in ($reg++) sequence
844 "#-" "--" decorator in (--$reg) sequence
847 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
848 "3" 3 bit unsigned immediate (OP_*_SA3)
849 "4" 4 bit unsigned immediate (OP_*_SA4)
850 "5" 8 bit unsigned immediate (OP_*_IMM8)
851 "6" 5 bit unsigned immediate (OP_*_RS)
852 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
853 "8" 6 bit unsigned immediate (OP_*_WRDSP)
854 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
855 "0" 6 bit signed immediate (OP_*_DSPSFT)
856 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
857 "'" 6 bit unsigned immediate (OP_*_RDDSP)
858 "@" 10 bit signed immediate (OP_*_IMM10)
861 "!" 1 bit usermode flag (OP_*_MT_U)
862 "$" 1 bit load high flag (OP_*_MT_H)
863 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
864 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
865 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
866 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
869 "~" 12 bit offset (OP_*_OFFSET12)
870 "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
873 "+J" 10-bit hypcall code (OP_*CODE10)
876 "+1" UDI immediate bits 6-10
877 "+2" UDI immediate bits 6-15
878 "+3" UDI immediate bits 6-20
879 "+4" UDI immediate bits 6-25
882 "+x" Bit index field of bbit. Enforces: 0 <= index < 32.
883 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
884 otherwise skips to next candidate.
885 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
886 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if
887 32 <= pos < 64, otherwise skips to next candidate.
888 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
889 "+s" Length-minus-one field of cins32/exts32. Requires msb position
890 of the field to be <= 31.
891 "+S" Length-minus-one field of cins/exts. Requires msb position
892 of the field to be <= 63.
895 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
896 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
897 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
898 "+z" 5-bit rz register (OP_*_RZ)
899 "+Z" 5-bit fz register (OP_*_FZ)
902 "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
905 "+d" 5-bit MSA register (FD)
906 "+e" 5-bit MSA register (FS)
907 "+h" 5-bit MSA register (FT)
908 "+k" 5-bit GPR at bit 6
909 "+l" 5-bit MSA control register at bit 6
910 "+n" 5-bit MSA control register at bit 11
911 "+o" 4-bit vector element index at bit 16
912 "+u" 3-bit vector element index at bit 16
913 "+v" 2-bit vector element index at bit 16
914 "+w" 1-bit vector element index at bit 16
915 "+T" (-512 .. 511) << 0 at bit 16
916 "+U" (-512 .. 511) << 1 at bit 16
917 "+V" (-512 .. 511) << 2 at bit 16
918 "+W" (-512 .. 511) << 3 at bit 16
919 "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
920 "+!" 3 bit unsigned bit position at bit 16
921 "+@" 4 bit unsigned bit position at bit 16
922 "+#" 6 bit unsigned bit position at bit 16
923 "+$" 5 bit unsigned immediate at bit 16
924 "+%" 5 bit signed immediate at bit 16
925 "+^" 10 bit signed immediate at bit 11
926 "+&" 0 vector element index
927 "+*" 5-bit register vector element index at bit 16
928 "+|" 8-bit mask at bit 16
931 "()" parens surrounding optional value
932 "," separates operands
933 "+" Start of extension sequence.
935 Characters used so far, for quick reference when adding more:
937 "%[]<>(),+:'@!#$*&\~"
938 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
939 "abcdefghijklopqrstuvwxz"
941 Extension character sequences used so far ("+" followed by the
942 following), for quick reference when adding more:
945 "ABCEFGHJKLMNPQSTUVWXZ"
946 "abcdefghijklmnopqrstuvwxyz"
949 /* These are the bits which may be set in the pinfo field of an
950 instructions, if it is not equal to INSN_MACRO. */
952 /* Writes to operand number N. */
953 #define INSN_WRITE_SHIFT 0
954 #define INSN_WRITE_1 0x00000001
955 #define INSN_WRITE_2 0x00000002
956 #define INSN_WRITE_ALL 0x00000003
957 /* Reads from operand number N. */
958 #define INSN_READ_SHIFT 2
959 #define INSN_READ_1 0x00000004
960 #define INSN_READ_2 0x00000008
961 #define INSN_READ_3 0x00000010
962 #define INSN_READ_4 0x00000020
963 #define INSN_READ_ALL 0x0000003c
964 /* Modifies general purpose register 31. */
965 #define INSN_WRITE_GPR_31 0x00000040
966 /* Modifies coprocessor condition code. */
967 #define INSN_WRITE_COND_CODE 0x00000080
968 /* Reads coprocessor condition code. */
969 #define INSN_READ_COND_CODE 0x00000100
971 #define INSN_TLB 0x00000200
972 /* Reads coprocessor register other than floating point register. */
973 #define INSN_COP 0x00000400
974 /* Instruction loads value from memory. */
975 #define INSN_LOAD_MEMORY 0x00000800
976 /* Instruction loads value from coprocessor, requiring delay. */
977 #define INSN_LOAD_COPROC_DELAY 0x00001000
978 /* Instruction has unconditional branch delay slot. */
979 #define INSN_UNCOND_BRANCH_DELAY 0x00002000
980 /* Instruction has conditional branch delay slot. */
981 #define INSN_COND_BRANCH_DELAY 0x00004000
982 /* Conditional branch likely: if branch not taken, insn nullified. */
983 #define INSN_COND_BRANCH_LIKELY 0x00008000
984 /* Moves to coprocessor register, requiring delay. */
985 #define INSN_COPROC_MOVE_DELAY 0x00010000
986 /* Loads coprocessor register from memory, requiring delay. */
987 #define INSN_COPROC_MEMORY_DELAY 0x00020000
988 /* Reads the HI register. */
989 #define INSN_READ_HI 0x00040000
990 /* Reads the LO register. */
991 #define INSN_READ_LO 0x00080000
992 /* Modifies the HI register. */
993 #define INSN_WRITE_HI 0x00100000
994 /* Modifies the LO register. */
995 #define INSN_WRITE_LO 0x00200000
996 /* Not to be placed in a branch delay slot, either architecturally
997 or for ease of handling (such as with instructions that take a trap). */
998 #define INSN_NO_DELAY_SLOT 0x00400000
999 /* Instruction stores value into memory. */
1000 #define INSN_STORE_MEMORY 0x00800000
1001 /* Instruction uses single precision floating point. */
1002 #define FP_S 0x01000000
1003 /* Instruction uses double precision floating point. */
1004 #define FP_D 0x02000000
1005 /* Instruction is part of the tx39's integer multiply family. */
1006 #define INSN_MULT 0x04000000
1007 /* Reads general purpose register 24. */
1008 #define INSN_READ_GPR_24 0x08000000
1009 /* Writes to general purpose register 24. */
1010 #define INSN_WRITE_GPR_24 0x10000000
1011 /* A user-defined instruction. */
1012 #define INSN_UDI 0x20000000
1013 /* Instruction is actually a macro. It should be ignored by the
1014 disassembler, and requires special treatment by the assembler. */
1015 #define INSN_MACRO 0xffffffff
1017 /* These are the bits which may be set in the pinfo2 field of an
1020 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
1021 #define INSN2_ALIAS 0x00000001
1022 /* Instruction reads MDMX accumulator. */
1023 #define INSN2_READ_MDMX_ACC 0x00000002
1024 /* Instruction writes MDMX accumulator. */
1025 #define INSN2_WRITE_MDMX_ACC 0x00000004
1026 /* Macro uses single-precision floating-point instructions. This should
1027 only be set for macros. For instructions, FP_S in pinfo carries the
1028 same information. */
1029 #define INSN2_M_FP_S 0x00000008
1030 /* Macro uses double-precision floating-point instructions. This should
1031 only be set for macros. For instructions, FP_D in pinfo carries the
1032 same information. */
1033 #define INSN2_M_FP_D 0x00000010
1034 /* Instruction has a branch delay slot that requires a 16-bit instruction. */
1035 #define INSN2_BRANCH_DELAY_16BIT 0x00000020
1036 /* Instruction has a branch delay slot that requires a 32-bit instruction. */
1037 #define INSN2_BRANCH_DELAY_32BIT 0x00000040
1038 /* Writes to the stack pointer ($29). */
1039 #define INSN2_WRITE_SP 0x00000080
1040 /* Reads from the stack pointer ($29). */
1041 #define INSN2_READ_SP 0x00000100
1042 /* Reads the RA ($31) register. */
1043 #define INSN2_READ_GPR_31 0x00000200
1044 /* Reads the program counter ($pc). */
1045 #define INSN2_READ_PC 0x00000400
1046 /* Is an unconditional branch insn. */
1047 #define INSN2_UNCOND_BRANCH 0x00000800
1048 /* Is a conditional branch insn. */
1049 #define INSN2_COND_BRANCH 0x00001000
1050 /* Reads from $16. This is true of the MIPS16 0x6500 nop. */
1051 #define INSN2_READ_GPR_16 0x00002000
1052 /* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */
1053 #define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
1055 /* Masks used to mark instructions to indicate which MIPS ISA level
1056 they were introduced in. INSN_ISA_MASK masks an enumeration that
1057 specifies the base ISA level(s). The remainder of a 32-bit
1058 word constructed using these macros is a bitmask of the remaining
1059 INSN_* values below. */
1061 #define INSN_ISA_MASK 0x0000001ful
1063 /* We cannot start at zero due to ISA_UNKNOWN below. */
1069 #define INSN_ISA32 6
1070 #define INSN_ISA32R2 7
1071 #define INSN_ISA32R3 8
1072 #define INSN_ISA32R5 9
1073 #define INSN_ISA64 11
1074 #define INSN_ISA64R2 12
1075 #define INSN_ISA64R3 13
1076 #define INSN_ISA64R5 14
1077 /* Below this point the INSN_* values correspond to combinations of ISAs.
1078 They are only for use in the opcodes table to indicate membership of
1079 a combination of ISAs that cannot be expressed using the usual inclusion
1080 ordering on the above INSN_* values. */
1081 #define INSN_ISA3_32 16
1082 #define INSN_ISA3_32R2 17
1083 #define INSN_ISA4_32 18
1084 #define INSN_ISA4_32R2 19
1085 #define INSN_ISA5_32R2 20
1087 /* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */
1088 #define ISAF(X) (1 << (INSN_ISA##X - 1))
1089 #define INSN_UPTO1 ISAF(1)
1090 #define INSN_UPTO2 INSN_UPTO1 | ISAF(2)
1091 #define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2)
1092 #define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2)
1093 #define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2)
1094 #define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32)
1095 #define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \
1096 | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2)
1097 #define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3)
1098 #define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5)
1099 #define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32)
1100 #define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2)
1101 #define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3)
1102 #define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5)
1104 /* The same information in table form: bit INSN_ISA<X> - 1 of index
1105 INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */
1106 static const unsigned int mips_isa_table[] = {
1124 /* Masks used for Chip specific instructions. */
1125 #define INSN_CHIP_MASK 0xc3ff0f20
1127 /* Cavium Networks Octeon instructions. */
1128 #define INSN_OCTEON 0x00000800
1129 #define INSN_OCTEONP 0x00000200
1130 #define INSN_OCTEON2 0x00000100
1132 /* MIPS R5900 instruction */
1133 #define INSN_5900 0x00004000
1135 /* MIPS R4650 instruction. */
1136 #define INSN_4650 0x00010000
1137 /* LSI R4010 instruction. */
1138 #define INSN_4010 0x00020000
1139 /* NEC VR4100 instruction. */
1140 #define INSN_4100 0x00040000
1141 /* Toshiba R3900 instruction. */
1142 #define INSN_3900 0x00080000
1143 /* MIPS R10000 instruction. */
1144 #define INSN_10000 0x00100000
1145 /* Broadcom SB-1 instruction. */
1146 #define INSN_SB1 0x00200000
1147 /* NEC VR4111/VR4181 instruction. */
1148 #define INSN_4111 0x00400000
1149 /* NEC VR4120 instruction. */
1150 #define INSN_4120 0x00800000
1151 /* NEC VR5400 instruction. */
1152 #define INSN_5400 0x01000000
1153 /* NEC VR5500 instruction. */
1154 #define INSN_5500 0x02000000
1156 /* ST Microelectronics Loongson 2E. */
1157 #define INSN_LOONGSON_2E 0x40000000
1158 /* ST Microelectronics Loongson 2F. */
1159 #define INSN_LOONGSON_2F 0x80000000
1161 #define INSN_LOONGSON_3A 0x00000400
1162 /* RMI Xlr instruction */
1163 #define INSN_XLR 0x00000020
1166 #define ASE_DSP 0x00000001
1167 #define ASE_DSP64 0x00000002
1169 #define ASE_DSPR2 0x00000004
1170 /* Enhanced VA Scheme */
1171 #define ASE_EVA 0x00000008
1172 /* MCU (MicroController) ASE */
1173 #define ASE_MCU 0x00000010
1175 #define ASE_MDMX 0x00000020
1177 #define ASE_MIPS3D 0x00000040
1179 #define ASE_MT 0x00000080
1181 #define ASE_SMARTMIPS 0x00000100
1182 /* Virtualization ASE */
1183 #define ASE_VIRT 0x00000200
1184 #define ASE_VIRT64 0x00000400
1186 #define ASE_MSA 0x00000800
1187 #define ASE_MSA64 0x00001000
1188 /* eXtended Physical Address (XPA) Extension. */
1189 #define ASE_XPA 0x00002000
1191 /* MIPS ISA defines, use instead of hardcoding ISA level. */
1193 #define ISA_UNKNOWN 0 /* Gas internal use. */
1194 #define ISA_MIPS1 INSN_ISA1
1195 #define ISA_MIPS2 INSN_ISA2
1196 #define ISA_MIPS3 INSN_ISA3
1197 #define ISA_MIPS4 INSN_ISA4
1198 #define ISA_MIPS5 INSN_ISA5
1200 #define ISA_MIPS32 INSN_ISA32
1201 #define ISA_MIPS64 INSN_ISA64
1203 #define ISA_MIPS32R2 INSN_ISA32R2
1204 #define ISA_MIPS32R3 INSN_ISA32R3
1205 #define ISA_MIPS32R5 INSN_ISA32R5
1206 #define ISA_MIPS64R2 INSN_ISA64R2
1207 #define ISA_MIPS64R3 INSN_ISA64R3
1208 #define ISA_MIPS64R5 INSN_ISA64R5
1211 /* CPU defines, use instead of hardcoding processor number. Keep this
1212 in sync with bfd/archures.c in order for machine selection to work. */
1213 #define CPU_UNKNOWN 0 /* Gas internal use. */
1214 #define CPU_R3000 3000
1215 #define CPU_R3900 3900
1216 #define CPU_R4000 4000
1217 #define CPU_R4010 4010
1218 #define CPU_VR4100 4100
1219 #define CPU_R4111 4111
1220 #define CPU_VR4120 4120
1221 #define CPU_R4300 4300
1222 #define CPU_R4400 4400
1223 #define CPU_R4600 4600
1224 #define CPU_R4650 4650
1225 #define CPU_R5000 5000
1226 #define CPU_VR5400 5400
1227 #define CPU_VR5500 5500
1228 #define CPU_R5900 5900
1229 #define CPU_R6000 6000
1230 #define CPU_RM7000 7000
1231 #define CPU_R8000 8000
1232 #define CPU_RM9000 9000
1233 #define CPU_R10000 10000
1234 #define CPU_R12000 12000
1235 #define CPU_R14000 14000
1236 #define CPU_R16000 16000
1237 #define CPU_MIPS16 16
1238 #define CPU_MIPS32 32
1239 #define CPU_MIPS32R2 33
1240 #define CPU_MIPS32R3 34
1241 #define CPU_MIPS32R5 36
1243 #define CPU_MIPS64 64
1244 #define CPU_MIPS64R2 65
1245 #define CPU_MIPS64R3 66
1246 #define CPU_MIPS64R5 68
1247 #define CPU_SB1 12310201 /* octal 'SB', 01. */
1248 #define CPU_LOONGSON_2E 3001
1249 #define CPU_LOONGSON_2F 3002
1250 #define CPU_LOONGSON_3A 3003
1251 #define CPU_OCTEON 6501
1252 #define CPU_OCTEONP 6601
1253 #define CPU_OCTEON2 6502
1254 #define CPU_XLR 887682 /* decimal 'XLR' */
1256 /* Return true if the given CPU is included in INSN_* mask MASK. */
1258 static inline bfd_boolean
1259 cpu_is_member (int cpu, unsigned int mask)
1266 return (mask & INSN_4650) != 0;
1269 return (mask & INSN_4010) != 0;
1272 return (mask & INSN_4100) != 0;
1275 return (mask & INSN_3900) != 0;
1281 return (mask & INSN_10000) != 0;
1284 return (mask & INSN_SB1) != 0;
1287 return (mask & INSN_4111) != 0;
1290 return (mask & INSN_4120) != 0;
1293 return (mask & INSN_5400) != 0;
1296 return (mask & INSN_5500) != 0;
1299 return (mask & INSN_5900) != 0;
1301 case CPU_LOONGSON_2E:
1302 return (mask & INSN_LOONGSON_2E) != 0;
1304 case CPU_LOONGSON_2F:
1305 return (mask & INSN_LOONGSON_2F) != 0;
1307 case CPU_LOONGSON_3A:
1308 return (mask & INSN_LOONGSON_3A) != 0;
1311 return (mask & INSN_OCTEON) != 0;
1314 return (mask & INSN_OCTEONP) != 0;
1317 return (mask & INSN_OCTEON2) != 0;
1320 return (mask & INSN_XLR) != 0;
1327 /* Test for membership in an ISA including chip specific ISAs. INSN
1328 is pointer to an element of the opcode table; ISA is the specified
1329 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
1330 test, or zero if no CPU specific ISA test is desired. Return true
1331 if instruction INSN is available to the given ISA and CPU. */
1333 static inline bfd_boolean
1334 opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
1336 if (!cpu_is_member (cpu, insn->exclusions))
1338 /* Test for ISA level compatibility. */
1339 if ((isa & INSN_ISA_MASK) != 0
1340 && (insn->membership & INSN_ISA_MASK) != 0
1341 && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
1342 >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
1345 /* Test for ASE compatibility. */
1346 if ((ase & insn->ase) != 0)
1349 /* Test for processor-specific extensions. */
1350 if (cpu_is_member (cpu, insn->membership))
1356 /* This is a list of macro expanded instructions.
1358 _I appended means immediate
1359 _A appended means target address of a jump
1360 _AB appended means address with (possibly zero) base register
1361 _D appended means 64 bit floating point constant
1362 _S appended means 32 bit floating point constant. */
1615 /* The order of overloaded instructions matters. Label arguments and
1616 register arguments look the same. Instructions that can have either
1617 for arguments must apear in the correct order in this table for the
1618 assembler to pick the right one. In other words, entries with
1619 immediate operands must apear after the same instruction with
1622 Many instructions are short hand for other instructions (i.e., The
1623 jal <register> instruction is short for jalr <register>). */
1625 extern const struct mips_operand mips_vu0_channel_mask;
1626 extern const struct mips_operand *decode_mips_operand (const char *);
1627 extern const struct mips_opcode mips_builtin_opcodes[];
1628 extern const int bfd_mips_num_builtin_opcodes;
1629 extern struct mips_opcode *mips_opcodes;
1630 extern int bfd_mips_num_opcodes;
1631 #define NUMOPCODES bfd_mips_num_opcodes
1634 /* The rest of this file adds definitions for the mips16 TinyRISC
1637 /* These are the bitmasks and shift counts used for the different
1638 fields in the instruction formats. Other than OP, no masks are
1639 provided for the fixed portions of an instruction, since they are
1642 The I format uses IMM11.
1644 The RI format uses RX and IMM8.
1646 The RR format uses RX, and RY.
1648 The RRI format uses RX, RY, and IMM5.
1650 The RRR format uses RX, RY, and RZ.
1652 The RRI_A format uses RX, RY, and IMM4.
1654 The SHIFT format uses RX, RY, and SHAMT.
1656 The I8 format uses IMM8.
1658 The I8_MOVR32 format uses RY and REGR32.
1660 The IR_MOV32R format uses REG32R and MOV32Z.
1662 The I64 format uses IMM8.
1664 The RI64 format uses RY and IMM5.
1667 #define MIPS16OP_MASK_OP 0x1f
1668 #define MIPS16OP_SH_OP 11
1669 #define MIPS16OP_MASK_IMM11 0x7ff
1670 #define MIPS16OP_SH_IMM11 0
1671 #define MIPS16OP_MASK_RX 0x7
1672 #define MIPS16OP_SH_RX 8
1673 #define MIPS16OP_MASK_IMM8 0xff
1674 #define MIPS16OP_SH_IMM8 0
1675 #define MIPS16OP_MASK_RY 0x7
1676 #define MIPS16OP_SH_RY 5
1677 #define MIPS16OP_MASK_IMM5 0x1f
1678 #define MIPS16OP_SH_IMM5 0
1679 #define MIPS16OP_MASK_RZ 0x7
1680 #define MIPS16OP_SH_RZ 2
1681 #define MIPS16OP_MASK_IMM4 0xf
1682 #define MIPS16OP_SH_IMM4 0
1683 #define MIPS16OP_MASK_REGR32 0x1f
1684 #define MIPS16OP_SH_REGR32 0
1685 #define MIPS16OP_MASK_REG32R 0x1f
1686 #define MIPS16OP_SH_REG32R 3
1687 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1688 #define MIPS16OP_MASK_MOVE32Z 0x7
1689 #define MIPS16OP_SH_MOVE32Z 0
1690 #define MIPS16OP_MASK_IMM6 0x3f
1691 #define MIPS16OP_SH_IMM6 5
1693 /* These are the characters which may appears in the args field of a MIPS16
1694 instruction. They appear in the order in which the fields appear when the
1695 instruction is used. Commas and parentheses in the args string are ignored
1696 when assembling, and written into the output when disassembling.
1698 "y" 3 bit register (MIPS16OP_*_RY)
1699 "x" 3 bit register (MIPS16OP_*_RX)
1700 "z" 3 bit register (MIPS16OP_*_RZ)
1701 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1702 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1703 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1704 "0" zero register ($0)
1705 "S" stack pointer ($sp or $29)
1707 "R" return address register ($ra or $31)
1708 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1709 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1710 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1711 "a" 26 bit jump address
1712 "i" likewise, but flips bit 0
1713 "e" 11 bit extension value
1714 "l" register list for entry instruction
1715 "L" register list for exit instruction
1717 "I" an immediate value used for macros
1719 The remaining codes may be extended. Except as otherwise noted,
1720 the full extended operand is a 16 bit signed value.
1721 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1722 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1723 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1724 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1725 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1726 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1727 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1728 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1729 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1730 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1731 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1732 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1733 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1734 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1735 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1736 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1737 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1738 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1739 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1740 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1741 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1742 "m" 7 bit register list for save instruction (18 bit extended)
1743 "M" 7 bit register list for restore instruction (18 bit extended)
1746 /* Save/restore encoding for the args field when all 4 registers are
1747 either saved as arguments or saved/restored as statics. */
1748 #define MIPS16_ALL_ARGS 0xe
1749 #define MIPS16_ALL_STATICS 0xb
1751 /* The following flags have the same value for the mips16 opcode
1756 INSN_UNCOND_BRANCH_DELAY
1757 INSN_COND_BRANCH_DELAY
1758 INSN_COND_BRANCH_LIKELY (never used)
1767 extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean);
1768 extern const struct mips_opcode mips16_opcodes[];
1769 extern const int bfd_mips16_num_opcodes;
1771 /* These are the bit masks and shift counts used for the different fields
1772 in the microMIPS instruction formats. No masks are provided for the
1773 fixed portions of an instruction, since they are not needed. */
1775 #define MICROMIPSOP_MASK_IMMEDIATE 0xffff
1776 #define MICROMIPSOP_SH_IMMEDIATE 0
1777 #define MICROMIPSOP_MASK_DELTA 0xffff
1778 #define MICROMIPSOP_SH_DELTA 0
1779 #define MICROMIPSOP_MASK_CODE10 0x3ff
1780 #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
1781 #define MICROMIPSOP_MASK_TRAP 0xf
1782 #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
1783 #define MICROMIPSOP_MASK_SHAMT 0x1f
1784 #define MICROMIPSOP_SH_SHAMT 11
1785 #define MICROMIPSOP_MASK_TARGET 0x3ffffff
1786 #define MICROMIPSOP_SH_TARGET 0
1787 #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
1788 #define MICROMIPSOP_SH_EXTLSB 6
1789 #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
1790 #define MICROMIPSOP_SH_EXTMSBD 11
1791 #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
1792 #define MICROMIPSOP_SH_INSMSB 11
1793 #define MICROMIPSOP_MASK_CODE 0x3ff
1794 #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
1795 #define MICROMIPSOP_MASK_CODE2 0x3ff
1796 #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
1797 #define MICROMIPSOP_MASK_CACHE 0x1f
1798 #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
1799 #define MICROMIPSOP_MASK_SEL 0x7
1800 #define MICROMIPSOP_SH_SEL 11
1801 #define MICROMIPSOP_MASK_OFFSET12 0xfff
1802 #define MICROMIPSOP_SH_OFFSET12 0
1803 #define MICROMIPSOP_MASK_3BITPOS 0x7
1804 #define MICROMIPSOP_SH_3BITPOS 21
1805 #define MICROMIPSOP_MASK_STYPE 0x1f
1806 #define MICROMIPSOP_SH_STYPE 16
1807 #define MICROMIPSOP_MASK_OFFSET10 0x3ff
1808 #define MICROMIPSOP_SH_OFFSET10 6
1809 #define MICROMIPSOP_MASK_RS 0x1f
1810 #define MICROMIPSOP_SH_RS 16
1811 #define MICROMIPSOP_MASK_RT 0x1f
1812 #define MICROMIPSOP_SH_RT 21
1813 #define MICROMIPSOP_MASK_RD 0x1f
1814 #define MICROMIPSOP_SH_RD 11
1815 #define MICROMIPSOP_MASK_FS 0x1f
1816 #define MICROMIPSOP_SH_FS 16
1817 #define MICROMIPSOP_MASK_FT 0x1f
1818 #define MICROMIPSOP_SH_FT 21
1819 #define MICROMIPSOP_MASK_FD 0x1f
1820 #define MICROMIPSOP_SH_FD 11
1821 #define MICROMIPSOP_MASK_FR 0x1f
1822 #define MICROMIPSOP_SH_FR 6
1823 #define MICROMIPSOP_MASK_RS3 0x1f
1824 #define MICROMIPSOP_SH_RS3 6
1825 #define MICROMIPSOP_MASK_PREFX 0x1f
1826 #define MICROMIPSOP_SH_PREFX 11
1827 #define MICROMIPSOP_MASK_BCC 0x7
1828 #define MICROMIPSOP_SH_BCC 18
1829 #define MICROMIPSOP_MASK_CCC 0x7
1830 #define MICROMIPSOP_SH_CCC 13
1831 #define MICROMIPSOP_MASK_COPZ 0x7fffff
1832 #define MICROMIPSOP_SH_COPZ 3
1834 #define MICROMIPSOP_MASK_MB 0x7
1835 #define MICROMIPSOP_SH_MB 23
1836 #define MICROMIPSOP_MASK_MC 0x7
1837 #define MICROMIPSOP_SH_MC 4
1838 #define MICROMIPSOP_MASK_MD 0x7
1839 #define MICROMIPSOP_SH_MD 7
1840 #define MICROMIPSOP_MASK_ME 0x7
1841 #define MICROMIPSOP_SH_ME 1
1842 #define MICROMIPSOP_MASK_MF 0x7
1843 #define MICROMIPSOP_SH_MF 3
1844 #define MICROMIPSOP_MASK_MG 0x7
1845 #define MICROMIPSOP_SH_MG 0
1846 #define MICROMIPSOP_MASK_MH 0x7
1847 #define MICROMIPSOP_SH_MH 7
1848 #define MICROMIPSOP_MASK_MJ 0x1f
1849 #define MICROMIPSOP_SH_MJ 0
1850 #define MICROMIPSOP_MASK_ML 0x7
1851 #define MICROMIPSOP_SH_ML 4
1852 #define MICROMIPSOP_MASK_MM 0x7
1853 #define MICROMIPSOP_SH_MM 1
1854 #define MICROMIPSOP_MASK_MN 0x7
1855 #define MICROMIPSOP_SH_MN 4
1856 #define MICROMIPSOP_MASK_MP 0x1f
1857 #define MICROMIPSOP_SH_MP 5
1858 #define MICROMIPSOP_MASK_MQ 0x7
1859 #define MICROMIPSOP_SH_MQ 7
1861 #define MICROMIPSOP_MASK_IMMA 0x7f
1862 #define MICROMIPSOP_SH_IMMA 0
1863 #define MICROMIPSOP_MASK_IMMB 0x7
1864 #define MICROMIPSOP_SH_IMMB 1
1865 #define MICROMIPSOP_MASK_IMMC 0xf
1866 #define MICROMIPSOP_SH_IMMC 0
1867 #define MICROMIPSOP_MASK_IMMD 0x3ff
1868 #define MICROMIPSOP_SH_IMMD 0
1869 #define MICROMIPSOP_MASK_IMME 0x7f
1870 #define MICROMIPSOP_SH_IMME 0
1871 #define MICROMIPSOP_MASK_IMMF 0xf
1872 #define MICROMIPSOP_SH_IMMF 0
1873 #define MICROMIPSOP_MASK_IMMG 0xf
1874 #define MICROMIPSOP_SH_IMMG 0
1875 #define MICROMIPSOP_MASK_IMMH 0xf
1876 #define MICROMIPSOP_SH_IMMH 0
1877 #define MICROMIPSOP_MASK_IMMI 0x7f
1878 #define MICROMIPSOP_SH_IMMI 0
1879 #define MICROMIPSOP_MASK_IMMJ 0xf
1880 #define MICROMIPSOP_SH_IMMJ 0
1881 #define MICROMIPSOP_MASK_IMML 0xf
1882 #define MICROMIPSOP_SH_IMML 0
1883 #define MICROMIPSOP_MASK_IMMM 0x7
1884 #define MICROMIPSOP_SH_IMMM 1
1885 #define MICROMIPSOP_MASK_IMMN 0x3
1886 #define MICROMIPSOP_SH_IMMN 4
1887 #define MICROMIPSOP_MASK_IMMO 0xf
1888 #define MICROMIPSOP_SH_IMMO 0
1889 #define MICROMIPSOP_MASK_IMMP 0x1f
1890 #define MICROMIPSOP_SH_IMMP 0
1891 #define MICROMIPSOP_MASK_IMMQ 0x7fffff
1892 #define MICROMIPSOP_SH_IMMQ 0
1893 #define MICROMIPSOP_MASK_IMMU 0x1f
1894 #define MICROMIPSOP_SH_IMMU 0
1895 #define MICROMIPSOP_MASK_IMMW 0x3f
1896 #define MICROMIPSOP_SH_IMMW 1
1897 #define MICROMIPSOP_MASK_IMMX 0xf
1898 #define MICROMIPSOP_SH_IMMX 1
1899 #define MICROMIPSOP_MASK_IMMY 0x1ff
1900 #define MICROMIPSOP_SH_IMMY 1
1903 #define MICROMIPSOP_MASK_DSPACC 0x3
1904 #define MICROMIPSOP_SH_DSPACC 14
1905 #define MICROMIPSOP_MASK_DSPSFT 0x3f
1906 #define MICROMIPSOP_SH_DSPSFT 16
1907 #define MICROMIPSOP_MASK_SA3 0x7
1908 #define MICROMIPSOP_SH_SA3 13
1909 #define MICROMIPSOP_MASK_SA4 0xf
1910 #define MICROMIPSOP_SH_SA4 12
1911 #define MICROMIPSOP_MASK_IMM8 0xff
1912 #define MICROMIPSOP_SH_IMM8 13
1913 #define MICROMIPSOP_MASK_IMM10 0x3ff
1914 #define MICROMIPSOP_SH_IMM10 16
1915 #define MICROMIPSOP_MASK_WRDSP 0x3f
1916 #define MICROMIPSOP_SH_WRDSP 14
1917 #define MICROMIPSOP_MASK_BP 0x3
1918 #define MICROMIPSOP_SH_BP 14
1920 /* Placeholders for fields that only exist in the traditional 32-bit
1921 instruction encoding; see the comment above for details. */
1922 #define MICROMIPSOP_MASK_CODE20 0
1923 #define MICROMIPSOP_SH_CODE20 0
1924 #define MICROMIPSOP_MASK_PERFREG 0
1925 #define MICROMIPSOP_SH_PERFREG 0
1926 #define MICROMIPSOP_MASK_CODE19 0
1927 #define MICROMIPSOP_SH_CODE19 0
1928 #define MICROMIPSOP_MASK_ALN 0
1929 #define MICROMIPSOP_SH_ALN 0
1930 #define MICROMIPSOP_MASK_VECBYTE 0
1931 #define MICROMIPSOP_SH_VECBYTE 0
1932 #define MICROMIPSOP_MASK_VECALIGN 0
1933 #define MICROMIPSOP_SH_VECALIGN 0
1934 #define MICROMIPSOP_MASK_DSPACC_S 0
1935 #define MICROMIPSOP_SH_DSPACC_S 0
1936 #define MICROMIPSOP_MASK_DSPSFT_7 0
1937 #define MICROMIPSOP_SH_DSPSFT_7 0
1938 #define MICROMIPSOP_MASK_RDDSP 0
1939 #define MICROMIPSOP_SH_RDDSP 0
1940 #define MICROMIPSOP_MASK_MT_U 0
1941 #define MICROMIPSOP_SH_MT_U 0
1942 #define MICROMIPSOP_MASK_MT_H 0
1943 #define MICROMIPSOP_SH_MT_H 0
1944 #define MICROMIPSOP_MASK_MTACC_T 0
1945 #define MICROMIPSOP_SH_MTACC_T 0
1946 #define MICROMIPSOP_MASK_MTACC_D 0
1947 #define MICROMIPSOP_SH_MTACC_D 0
1948 #define MICROMIPSOP_MASK_BBITIND 0
1949 #define MICROMIPSOP_SH_BBITIND 0
1950 #define MICROMIPSOP_MASK_CINSPOS 0
1951 #define MICROMIPSOP_SH_CINSPOS 0
1952 #define MICROMIPSOP_MASK_CINSLM1 0
1953 #define MICROMIPSOP_SH_CINSLM1 0
1954 #define MICROMIPSOP_MASK_SEQI 0
1955 #define MICROMIPSOP_SH_SEQI 0
1956 #define MICROMIPSOP_SH_OFFSET_A 0
1957 #define MICROMIPSOP_MASK_OFFSET_A 0
1958 #define MICROMIPSOP_SH_OFFSET_B 0
1959 #define MICROMIPSOP_MASK_OFFSET_B 0
1960 #define MICROMIPSOP_SH_OFFSET_C 0
1961 #define MICROMIPSOP_MASK_OFFSET_C 0
1962 #define MICROMIPSOP_SH_RZ 0
1963 #define MICROMIPSOP_MASK_RZ 0
1964 #define MICROMIPSOP_SH_FZ 0
1965 #define MICROMIPSOP_MASK_FZ 0
1967 /* microMIPS Enhanced VA Scheme */
1968 #define MICROMIPSOP_SH_EVAOFFSET 0
1969 #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff
1971 /* These are the characters which may appears in the args field of a microMIPS
1972 instruction. They appear in the order in which the fields appear
1973 when the instruction is used. Commas and parentheses in the args
1974 string are ignored when assembling, and written into the output
1977 The followings are for 16-bit microMIPS instructions.
1980 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1981 The same register used as both source and target.
1982 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1983 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1984 The same register used as both source and target.
1985 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1986 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1987 "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7
1988 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1989 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1990 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1991 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1992 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1993 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1994 "mr" must be program counter
1996 "mt" must be the same as the previous register
1997 "mx" must be the same as the destination register
2001 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
2002 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
2003 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
2004 32768, 65535) (MICROMIPSOP_*_IMMC)
2005 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
2006 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
2007 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
2008 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
2009 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
2010 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
2011 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
2012 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
2013 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
2014 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
2015 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
2016 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
2017 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
2018 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
2019 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
2020 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
2023 In most cases 32-bit microMIPS instructions use the same characters
2024 as MIPS (with ADDIUPC being a notable exception, but there are some
2027 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
2028 "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
2029 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
2030 ">" shift amount between 32 and 63, stored after subtracting 32
2031 (MICROMIPSOP_*_SHAMT)
2032 "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
2033 "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
2034 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
2035 "a" 26-bit target address (MICROMIPSOP_*_TARGET)
2036 "+i" likewise, but flips bit 0
2037 "b" 5-bit base register (MICROMIPSOP_*_RS)
2038 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
2039 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
2040 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
2041 "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
2042 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
2043 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
2044 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
2045 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
2046 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
2047 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
2048 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
2049 "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
2050 "t" 5-bit target register (MICROMIPSOP_*_RT)
2051 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
2052 "v" 5-bit same register used as both source and destination
2054 "w" 5-bit same register used as both target and destination
2056 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
2057 "z" must be zero register
2058 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
2059 "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
2060 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
2062 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
2063 LSB (MICROMIPSOP_*_EXTLSB).
2064 Enforces: 0 <= pos < 32.
2065 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
2066 Requires that "+A" or "+E" occur first to set position.
2067 Enforces: 0 < (pos+size) <= 32.
2068 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
2069 Requires that "+A" or "+E" occur first to set position.
2070 Enforces: 0 < (pos+size) <= 32.
2071 (Also used by DEXT w/ different limits, but limits for
2072 that are checked by the M_DEXT macro.)
2073 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
2074 Enforces: 32 <= pos < 64.
2075 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
2076 Requires that "+A" or "+E" occur first to set position.
2077 Enforces: 32 < (pos+size) <= 64.
2078 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
2079 Requires that "+A" or "+E" occur first to set position.
2080 Enforces: 32 < (pos+size) <= 64.
2081 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
2082 Requires that "+A" or "+E" occur first to set position.
2083 Enforces: 32 < (pos+size) <= 64.
2085 PC-relative addition (ADDIUPC) instruction:
2086 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
2087 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
2089 Floating point instructions:
2090 "D" 5-bit destination register (MICROMIPSOP_*_FD)
2091 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
2092 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
2093 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
2094 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
2095 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
2096 "V" 5-bit same register used as floating source and destination or target
2099 Coprocessor instructions:
2100 "E" 5-bit target register (MICROMIPSOP_*_RT)
2101 "G" 5-bit source register (MICROMIPSOP_*_RS)
2102 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
2105 "A" general 32 bit expression
2106 "I" 32-bit immediate (value placed in imm_expr).
2107 "F" 64-bit floating point constant in .rdata
2108 "L" 64-bit floating point constant in .lit8
2109 "f" 32-bit floating point constant
2110 "l" 32-bit floating point constant in .lit4
2113 "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
2114 "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
2115 "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
2116 "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
2117 "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
2118 "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
2119 "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
2120 "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
2121 "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
2122 "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
2124 microMIPS Enhanced VA Scheme:
2125 "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
2128 "+d" 5-bit MSA register (FD)
2129 "+e" 5-bit MSA register (FS)
2130 "+h" 5-bit MSA register (FT)
2131 "+k" 5-bit GPR at bit 6
2132 "+l" 5-bit MSA control register at bit 6
2133 "+n" 5-bit MSA control register at bit 11
2134 "+o" 4-bit vector element index at bit 16
2135 "+u" 3-bit vector element index at bit 16
2136 "+v" 2-bit vector element index at bit 16
2137 "+w" 1-bit vector element index at bit 16
2138 "+x" 5-bit shift amount at bit 16
2139 "+T" (-512 .. 511) << 0 at bit 16
2140 "+U" (-512 .. 511) << 1 at bit 16
2141 "+V" (-512 .. 511) << 2 at bit 16
2142 "+W" (-512 .. 511) << 3 at bit 16
2143 "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
2144 "+!" 3 bit unsigned bit position at bit 16
2145 "+@" 4 bit unsigned bit position at bit 16
2146 "+#" 6 bit unsigned bit position at bit 16
2147 "+$" 5 bit unsigned immediate at bit 16
2148 "+%" 5 bit signed immediate at bit 16
2149 "+^" 10 bit signed immediate at bit 11
2150 "+&" 0 vector element index
2151 "+*" 5-bit register vector element index at bit 16
2152 "+|" 8-bit mask at bit 16
2155 "()" parens surrounding optional value
2156 "," separates operands
2157 "+" start of extension sequence
2158 "m" start of microMIPS extension sequence
2160 Characters used so far, for quick reference when adding more:
2163 "ABCDEFGHI KLMN RST V "
2164 "abcd f hijklmnopqrstuvw yz"
2166 Extension character sequences used so far ("+" followed by the
2167 following), for quick reference when adding more:
2173 Extension character sequences used so far ("m" followed by the
2174 following), for quick reference when adding more:
2177 " BCDEFGHIJ LMNOPQ U WXYZ"
2178 " bcdefghij lmn pq st xyz"
2181 extern const struct mips_operand *decode_micromips_operand (const char *);
2182 extern const struct mips_opcode micromips_opcodes[];
2183 extern const int bfd_micromips_num_opcodes;
2185 /* A NOP insn impemented as "or at,at,zero".
2186 Used to implement -mfix-loongson2f. */
2187 #define LOONGSON2F_NOP_INSN 0x00200825
2189 #endif /* _MIPS_H_ */
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