1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005, 2008, 2009, 2010, 2013
4 Free Software Foundation, Inc.
5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
8 This file is part of GDB, GAS, and the GNU binutils.
10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version 3,
13 or (at your option) any later version.
15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING3. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
23 MA 02110-1301, USA. */
30 /* These are bit masks and shift counts to use to access the various
31 fields of an instruction. To retrieve the X field of an
32 instruction, use the expression
33 (i >> OP_SH_X) & OP_MASK_X
34 To set the same field (to j), use
35 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
37 Make sure you use fields that are appropriate for the instruction,
40 The 'i' format uses OP, RS, RT and IMMEDIATE.
42 The 'j' format uses OP and TARGET.
44 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
46 The 'b' format uses OP, RS, RT and DELTA.
48 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
50 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
52 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
53 breakpoint instruction are not defined; Kane says the breakpoint
54 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
55 only use ten bits). An optional two-operand form of break/sdbbp
56 allows the lower ten bits to be set too, and MIPS32 and later
57 architectures allow 20 bits to be set with a signal operand
60 The syscall instruction uses CODE20.
62 The general coprocessor instructions use COPZ. */
64 #define OP_MASK_OP 0x3f
66 #define OP_MASK_RS 0x1f
68 #define OP_MASK_FR 0x1f
70 #define OP_MASK_FMT 0x1f
72 #define OP_MASK_BCC 0x7
74 #define OP_MASK_CODE 0x3ff
76 #define OP_MASK_CODE2 0x3ff
78 #define OP_MASK_RT 0x1f
80 #define OP_MASK_FT 0x1f
82 #define OP_MASK_CACHE 0x1f
83 #define OP_SH_CACHE 16
84 #define OP_MASK_RD 0x1f
86 #define OP_MASK_FS 0x1f
88 #define OP_MASK_PREFX 0x1f
89 #define OP_SH_PREFX 11
90 #define OP_MASK_CCC 0x7
92 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
93 #define OP_SH_CODE20 6
94 #define OP_MASK_SHAMT 0x1f
96 #define OP_MASK_EXTLSB OP_MASK_SHAMT
97 #define OP_SH_EXTLSB OP_SH_SHAMT
98 #define OP_MASK_STYPE OP_MASK_SHAMT
99 #define OP_SH_STYPE OP_SH_SHAMT
100 #define OP_MASK_FD 0x1f
102 #define OP_MASK_TARGET 0x3ffffff
103 #define OP_SH_TARGET 0
104 #define OP_MASK_COPZ 0x1ffffff
106 #define OP_MASK_IMMEDIATE 0xffff
107 #define OP_SH_IMMEDIATE 0
108 #define OP_MASK_DELTA 0xffff
109 #define OP_SH_DELTA 0
110 #define OP_MASK_FUNCT 0x3f
111 #define OP_SH_FUNCT 0
112 #define OP_MASK_SPEC 0x3f
114 #define OP_SH_LOCC 8 /* FP condition code. */
115 #define OP_SH_HICC 18 /* FP condition code. */
116 #define OP_MASK_CC 0x7
117 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
118 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
119 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
120 #define OP_MASK_COP1SPEC 0xf
121 #define OP_MASK_COP1SCLR 0x4
122 #define OP_MASK_COP1CMP 0x3
123 #define OP_SH_COP1CMP 4
124 #define OP_SH_FORMAT 21 /* FP short format field. */
125 #define OP_MASK_FORMAT 0x7
126 #define OP_SH_TRUE 16
127 #define OP_MASK_TRUE 0x1
129 #define OP_MASK_GE 0x01
130 #define OP_SH_UNSIGNED 16
131 #define OP_MASK_UNSIGNED 0x1
132 #define OP_SH_HINT 16
133 #define OP_MASK_HINT 0x1f
134 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
135 #define OP_MASK_MMI 0x3f
136 #define OP_SH_MMISUB 6
137 #define OP_MASK_MMISUB 0x1f
138 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
139 #define OP_SH_PERFREG 1
140 #define OP_SH_SEL 0 /* Coprocessor select field. */
141 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
142 #define OP_SH_CODE19 6 /* 19 bit wait code. */
143 #define OP_MASK_CODE19 0x7ffff
145 #define OP_MASK_ALN 0x7
146 #define OP_SH_VSEL 21
147 #define OP_MASK_VSEL 0x1f
148 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
149 but 0x8-0xf don't select bytes. */
150 #define OP_SH_VECBYTE 22
151 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
152 #define OP_SH_VECALIGN 21
153 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
154 #define OP_SH_INSMSB 11
155 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
156 #define OP_SH_EXTMSBD 11
159 #define OP_SH_DSPACC 11
160 #define OP_MASK_DSPACC 0x3
161 #define OP_SH_DSPACC_S 21
162 #define OP_MASK_DSPACC_S 0x3
163 #define OP_SH_DSPSFT 20
164 #define OP_MASK_DSPSFT 0x3f
165 #define OP_SH_DSPSFT_7 19
166 #define OP_MASK_DSPSFT_7 0x7f
168 #define OP_MASK_SA3 0x7
170 #define OP_MASK_SA4 0xf
171 #define OP_SH_IMM8 16
172 #define OP_MASK_IMM8 0xff
173 #define OP_SH_IMM10 16
174 #define OP_MASK_IMM10 0x3ff
175 #define OP_SH_WRDSP 11
176 #define OP_MASK_WRDSP 0x3f
177 #define OP_SH_RDDSP 16
178 #define OP_MASK_RDDSP 0x3f
180 #define OP_MASK_BP 0x3
184 #define OP_MASK_MT_U 0x1
186 #define OP_MASK_MT_H 0x1
187 #define OP_SH_MTACC_T 18
188 #define OP_MASK_MTACC_T 0x3
189 #define OP_SH_MTACC_D 13
190 #define OP_MASK_MTACC_D 0x3
193 #define OP_MASK_3BITPOS 0x7
194 #define OP_SH_3BITPOS 12
195 #define OP_MASK_OFFSET12 0xfff
196 #define OP_SH_OFFSET12 0
198 #define OP_OP_COP0 0x10
199 #define OP_OP_COP1 0x11
200 #define OP_OP_COP2 0x12
201 #define OP_OP_COP3 0x13
202 #define OP_OP_LWC1 0x31
203 #define OP_OP_LWC2 0x32
204 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
205 #define OP_OP_LDC1 0x35
206 #define OP_OP_LDC2 0x36
207 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
208 #define OP_OP_SWC1 0x39
209 #define OP_OP_SWC2 0x3a
210 #define OP_OP_SWC3 0x3b
211 #define OP_OP_SDC1 0x3d
212 #define OP_OP_SDC2 0x3e
213 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
216 #define OP_MASK_CODE10 0x3ff
217 #define OP_SH_CODE10 11
219 /* Values in the 'VSEL' field. */
220 #define MDMX_FMTSEL_IMM_QH 0x1d
221 #define MDMX_FMTSEL_IMM_OB 0x1e
222 #define MDMX_FMTSEL_VEC_QH 0x15
223 #define MDMX_FMTSEL_VEC_OB 0x16
227 #define OP_MASK_UDI1 0x1f
229 #define OP_MASK_UDI2 0x3ff
231 #define OP_MASK_UDI3 0x7fff
233 #define OP_MASK_UDI4 0xfffff
236 #define OP_SH_BBITIND 16
237 #define OP_MASK_BBITIND 0x1f
238 #define OP_SH_CINSPOS 6
239 #define OP_MASK_CINSPOS 0x1f
240 #define OP_SH_CINSLM1 11
241 #define OP_MASK_CINSLM1 0x1f
243 #define OP_MASK_SEQI 0x3ff
246 #define OP_SH_OFFSET_A 6
247 #define OP_MASK_OFFSET_A 0xff
248 #define OP_SH_OFFSET_B 3
249 #define OP_MASK_OFFSET_B 0xff
250 #define OP_SH_OFFSET_C 6
251 #define OP_MASK_OFFSET_C 0x1ff
253 #define OP_MASK_RZ 0x1f
255 #define OP_MASK_FZ 0x1f
257 /* Every MICROMIPSOP_X definition requires a corresponding OP_X
258 definition, and vice versa. This simplifies various parts
259 of the operand handling in GAS. The fields below only exist
260 in the microMIPS encoding, so define each one to have an empty
262 #define OP_MASK_TRAP 0
264 #define OP_MASK_OFFSET10 0
265 #define OP_SH_OFFSET10 0
266 #define OP_MASK_RS3 0
294 #define OP_MASK_IMMA 0
296 #define OP_MASK_IMMB 0
298 #define OP_MASK_IMMC 0
300 #define OP_MASK_IMMF 0
302 #define OP_MASK_IMMG 0
304 #define OP_MASK_IMMH 0
306 #define OP_MASK_IMMI 0
308 #define OP_MASK_IMMJ 0
310 #define OP_MASK_IMML 0
312 #define OP_MASK_IMMM 0
314 #define OP_MASK_IMMN 0
316 #define OP_MASK_IMMO 0
318 #define OP_MASK_IMMP 0
320 #define OP_MASK_IMMQ 0
322 #define OP_MASK_IMMU 0
324 #define OP_MASK_IMMW 0
326 #define OP_MASK_IMMX 0
328 #define OP_MASK_IMMY 0
331 /* Enhanced VA Scheme */
332 #define OP_SH_EVAOFFSET 7
333 #define OP_MASK_EVAOFFSET 0x1ff
335 /* Enumerates the various types of MIPS operand. */
336 enum mips_operand_type {
337 /* Described by mips_int_operand. */
340 /* Described by mips_mapped_int_operand. */
343 /* Described by mips_msb_operand. */
346 /* Described by mips_reg_operand. */
349 /* Described by mips_reg_pair_operand. */
352 /* Described by mips_pcrel_operand. */
355 /* A performance register. The field is 5 bits in size, but the supported
356 values are much more restricted. */
359 /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts
360 as a normal 9-bit signed offset that is multiplied by four, but there
361 are four special cases:
369 /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two
370 5-bit register fields, both of which must be set to the destination
374 /* A register list for a microMIPS LWM or SWM instruction. The operand
375 size determines whether the 16-bit or 32-bit encoding is required. */
378 /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */
381 /* The register list and frame size for a MIPS16 SAVE or RESTORE
383 OP_SAVE_RESTORE_LIST,
385 /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:
389 0EEE0 8 copies of $vN[E], OB format
390 0EE01 4 copies of $vN[E], QH format
391 10110 all 8 elements of $vN, OB format
392 10101 all 4 elements of $vN, QH format
393 11110 8 copies of immediate N, OB format
394 11101 4 copies of immediate N, QH format. */
397 /* A register operand that must match the destination register. */
400 /* A register operand that must match the previous register. */
403 /* $pc, which has no encoding in the architectural instruction. */
407 /* Enumerates the types of MIPS register. */
408 enum mips_reg_operand_type {
409 /* General registers $0-$31. Software names like $at can also be used. */
412 /* Floating-point registers $f0-$f31. */
415 /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes
416 can also be written $fcc0-$fcc7. */
419 /* FPRs used in a vector capacity. They can be written $f0-$f31
420 or $v0-$v31, although the latter form is not used for the VR5400
421 vector instructions. */
424 /* DSP accumulator registers $ac0-$ac3. */
427 /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can
428 also be used in some contexts. */
431 /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
432 also be used in some contexts. */
436 /* Base class for all operands. */
439 /* The type of the operand. */
440 enum mips_operand_type type;
442 /* The operand occupies SIZE bits of the instruction, starting at LSB. */
447 /* Describes an integer operand with a regular encoding pattern. */
448 struct mips_int_operand
450 struct mips_operand root;
452 /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.
453 The cyclically previous field value encodes 1 << SHIFT less than that,
456 - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,
459 - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is
460 shifted left two places.
462 - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except
465 - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */
466 unsigned int max_val;
470 /* True if the operand should be printed as hex rather than decimal. */
471 bfd_boolean print_hex;
474 /* Uses a lookup table to describe a small integer operand. */
475 struct mips_mapped_int_operand
477 struct mips_operand root;
479 /* Maps each encoding value to the integer that it represents. */
482 /* True if the operand should be printed as hex rather than decimal. */
483 bfd_boolean print_hex;
486 /* An operand that encodes the most significant bit position of a bitfield.
487 Given a bitfield that spans bits [MSB, LSB], some operands of this type
488 encode MSB directly while others encode MSB - LSB. Each operand of this
489 type is preceded by an integer operand that specifies LSB.
491 The assembly form varies between instructions. For some instructions,
492 such as EXT, the operand is written as the bitfield size. For others,
493 such as EXTS, it is written in raw MSB - LSB form. */
494 struct mips_msb_operand
496 struct mips_operand root;
498 /* The assembly-level operand encoded by a field value of 0. */
501 /* True if the operand encodes MSB directly, false if it encodes
505 /* The maximum value of MSB + 1. */
509 /* Describes a single register operand. */
510 struct mips_reg_operand
512 struct mips_operand root;
514 /* The type of register. */
515 enum mips_reg_operand_type reg_type;
517 /* If nonnull, REG_MAP[N] gives the register associated with encoding N,
518 otherwise the encoding is the same as the register number. */
519 const unsigned char *reg_map;
522 /* Describes an operand that encodes a pair of registers. */
523 struct mips_reg_pair_operand
525 struct mips_operand root;
527 /* The type of register. */
528 enum mips_reg_operand_type reg_type;
530 /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */
531 unsigned char *reg1_map;
532 unsigned char *reg2_map;
535 /* Describes an operand that is calculated relative to a base PC.
536 The base PC is usually the address of the following instruction,
537 but the rules for MIPS16 instructions like ADDIUPC are more complicated. */
538 struct mips_pcrel_operand
540 struct mips_operand root;
542 /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC'. */
543 unsigned int align_log2 : 8;
545 /* The operand is shifted left SHIFT places and added to PC'.
546 The operand is signed if IS_SIGNED. */
547 unsigned int shift : 8;
548 unsigned int is_signed : 1;
550 /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
551 reinstated. This is true for jumps and branches and false for
552 PC-relative data instructions. */
553 unsigned int include_isa_bit : 1;
555 /* If FLIP_ISA_BIT, the ISA bit of the result is inverted.
556 This is true for JALX and false otherwise. */
557 unsigned int flip_isa_bit : 1;
560 /* Return a version of INSN in which the field specified by OPERAND
563 static inline unsigned int
564 mips_insert_operand (const struct mips_operand *operand, unsigned int insn,
569 mask = (1 << operand->size) - 1;
570 insn &= ~(mask << operand->lsb);
571 insn |= (uval & mask) << operand->lsb;
575 /* Extract OPERAND from instruction INSN. */
577 static inline unsigned int
578 mips_extract_operand (const struct mips_operand *operand, unsigned int insn)
580 return (insn >> operand->lsb) & ((1 << operand->size) - 1);
583 /* UVAL is the value encoded by OPERAND. Return it in signed form. */
586 mips_signed_operand (const struct mips_operand *operand, unsigned int uval)
588 unsigned int sign_bit, mask;
590 mask = (1 << operand->size) - 1;
591 sign_bit = 1 << (operand->size - 1);
592 return ((uval + sign_bit) & mask) - sign_bit;
595 /* Return the integer that OPERAND encodes as UVAL. */
598 mips_decode_int_operand (const struct mips_int_operand *operand,
601 uval |= (operand->max_val - uval) & -(1 << operand->root.size);
602 uval += operand->bias;
603 uval <<= operand->shift;
607 /* Return the register that OPERAND encodes as UVAL. */
610 mips_decode_reg_operand (const struct mips_reg_operand *operand,
613 if (operand->reg_map)
614 uval = operand->reg_map[uval];
618 /* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
619 Return the address that it encodes. */
621 static inline bfd_vma
622 mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand,
623 bfd_vma base_pc, unsigned int uval)
627 addr = base_pc & -(1 << operand->align_log2);
628 if (operand->is_signed)
629 addr += mips_signed_operand (&operand->root, uval) * (1 << operand->shift);
631 addr += uval << operand->shift;
632 if (operand->include_isa_bit)
634 if (operand->flip_isa_bit)
639 /* This structure holds information for a particular instruction. */
643 /* The name of the instruction. */
645 /* A string describing the arguments for this instruction. */
647 /* The basic opcode for the instruction. When assembling, this
648 opcode is modified by the arguments to produce the actual opcode
649 that is used. If pinfo is INSN_MACRO, then this is 0. */
651 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
652 relevant portions of the opcode when disassembling. If the
653 actual opcode anded with the match field equals the opcode field,
654 then we have found the correct instruction. If pinfo is
655 INSN_MACRO, then this field is the macro identifier. */
657 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
658 of bits describing the instruction, notably any relevant hazard
661 /* A collection of additional bits describing the instruction. */
662 unsigned long pinfo2;
663 /* A collection of bits describing the instruction sets of which this
664 instruction or macro is a member. */
665 unsigned long membership;
666 /* A collection of bits describing the ASE of which this instruction
667 or macro is a member. */
669 /* A collection of bits describing the instruction sets of which this
670 instruction or macro is not a member. */
671 unsigned long exclusions;
674 /* These are the characters which may appear in the args field of an
675 instruction. They appear in the order in which the fields appear
676 when the instruction is used. Commas and parentheses in the args
677 string are ignored when assembling, and written into the output
680 Each of these characters corresponds to a mask field defined above.
682 "1" 5 bit sync type (OP_*_STYPE)
683 "<" 5 bit shift amount (OP_*_SHAMT)
684 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
685 "a" 26 bit target address (OP_*_TARGET)
686 "+i" likewise, but flips bit 0
687 "b" 5 bit base register (OP_*_RS)
688 "c" 10 bit breakpoint code (OP_*_CODE)
689 "d" 5 bit destination register specifier (OP_*_RD)
690 "h" 5 bit prefx hint (OP_*_PREFX)
691 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
692 "j" 16 bit signed immediate (OP_*_DELTA)
693 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
694 "o" 16 bit signed offset (OP_*_DELTA)
695 "p" 16 bit PC relative branch target address (OP_*_DELTA)
696 "q" 10 bit extra breakpoint code (OP_*_CODE2)
697 "r" 5 bit same register used as both source and target (OP_*_RS)
698 "s" 5 bit source register specifier (OP_*_RS)
699 "t" 5 bit target register (OP_*_RT)
700 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
701 "v" 5 bit same register used as both source and destination (OP_*_RS)
702 "w" 5 bit same register used as both target and destination (OP_*_RT)
703 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
704 (used by clo and clz)
705 "C" 25 bit coprocessor function code (OP_*_COPZ)
706 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
707 "J" 19 bit wait function code (OP_*_CODE19)
708 "x" accept and ignore register name
709 "z" must be zero register
710 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
711 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
712 LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for
713 microMIPS compatibility).
714 Enforces: 0 <= pos < 32.
715 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
716 Requires that "+A" or "+E" occur first to set position.
717 Enforces: 0 < (pos+size) <= 32.
718 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
719 Requires that "+A" or "+E" occur first to set position.
720 Enforces: 0 < (pos+size) <= 32.
721 (Also used by "dext" w/ different limits, but limits for
722 that are checked by the M_DEXT macro.)
723 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
724 Enforces: 32 <= pos < 64.
725 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
726 Requires that "+A" or "+E" occur first to set position.
727 Enforces: 32 < (pos+size) <= 64.
728 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
729 Requires that "+A" or "+E" occur first to set position.
730 Enforces: 32 < (pos+size) <= 64.
731 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
732 Requires that "+A" or "+E" occur first to set position.
733 Enforces: 32 < (pos+size) <= 64.
735 Floating point instructions:
736 "D" 5 bit destination register (OP_*_FD)
737 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
738 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
739 "S" 5 bit fs source 1 register (OP_*_FS)
740 "T" 5 bit ft source 2 register (OP_*_FT)
741 "R" 5 bit fr source 3 register (OP_*_FR)
742 "V" 5 bit same register used as floating source and destination (OP_*_FS)
743 "W" 5 bit same register used as floating target and destination (OP_*_FT)
745 Coprocessor instructions:
746 "E" 5 bit target register (OP_*_RT)
747 "G" 5 bit destination register (OP_*_RD)
748 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
749 "P" 5 bit performance-monitor register (OP_*_PERFREG)
750 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
751 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
754 "A" General 32 bit expression
755 "I" 32 bit immediate (value placed in imm_expr).
756 "+I" 32 bit immediate (value placed in imm2_expr).
757 "F" 64 bit floating point constant in .rdata
758 "L" 64 bit floating point constant in .lit8
759 "f" 32 bit floating point constant
760 "l" 32 bit floating point constant in .lit4
762 MDMX and VR5400 instruction operands (note that while these use the
763 FP register fields, the MDMX instructions accept both $fN and $vN names
765 "O" alignment offset (OP_*_ALN)
766 "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
767 "X" destination register (OP_*_FD)
768 "Y" source register (OP_*_FS)
769 "Z" source register (OP_*_FT)
772 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
773 "3" 3 bit unsigned immediate (OP_*_SA3)
774 "4" 4 bit unsigned immediate (OP_*_SA4)
775 "5" 8 bit unsigned immediate (OP_*_IMM8)
776 "6" 5 bit unsigned immediate (OP_*_RS)
777 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
778 "8" 6 bit unsigned immediate (OP_*_WRDSP)
779 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
780 "0" 6 bit signed immediate (OP_*_DSPSFT)
781 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
782 "'" 6 bit unsigned immediate (OP_*_RDDSP)
783 "@" 10 bit signed immediate (OP_*_IMM10)
786 "!" 1 bit usermode flag (OP_*_MT_U)
787 "$" 1 bit load high flag (OP_*_MT_H)
788 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
789 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
790 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
791 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
794 "~" 12 bit offset (OP_*_OFFSET12)
795 "\" 3 bit position for aset and aclr (OP_*_3BITPOS)
798 "+J" 10-bit hypcall code (OP_*CODE10)
801 "+1" UDI immediate bits 6-10
802 "+2" UDI immediate bits 6-15
803 "+3" UDI immediate bits 6-20
804 "+4" UDI immediate bits 6-25
807 "+x" Bit index field of bbit. Enforces: 0 <= index < 32.
808 "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64,
809 otherwise skips to next candidate.
810 "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32.
811 "+P" Position field of cins/exts aliasing cins32/exts32. Matches if
812 32 <= pos < 64, otherwise skips to next candidate.
813 "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
814 "+s" Length-minus-one field of cins32/exts32. Requires msb position
815 of the field to be <= 31.
816 "+S" Length-minus-one field of cins/exts. Requires msb position
817 of the field to be <= 63.
820 "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
821 "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
822 "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
823 "+z" 5-bit rz register (OP_*_RZ)
824 "+Z" 5-bit fz register (OP_*_FZ)
827 "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
830 "()" parens surrounding optional value
831 "," separates operands
832 "+" Start of extension sequence.
834 Characters used so far, for quick reference when adding more:
837 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
838 "abcdefghijklopqrstuvwxz"
840 Extension character sequences used so far ("+" followed by the
841 following), for quick reference when adding more:
847 /* These are the bits which may be set in the pinfo field of an
848 instructions, if it is not equal to INSN_MACRO. */
850 /* Writes to operand number N. */
851 #define INSN_WRITE_SHIFT 0
852 #define INSN_WRITE_1 0x00000001
853 #define INSN_WRITE_2 0x00000002
854 #define INSN_WRITE_ALL 0x00000003
855 /* Reads from operand number N. */
856 #define INSN_READ_SHIFT 2
857 #define INSN_READ_1 0x00000004
858 #define INSN_READ_2 0x00000008
859 #define INSN_READ_3 0x00000010
860 #define INSN_READ_4 0x00000020
861 #define INSN_READ_ALL 0x0000003c
862 /* Modifies general purpose register 31. */
863 #define INSN_WRITE_GPR_31 0x00000040
864 /* Modifies coprocessor condition code. */
865 #define INSN_WRITE_COND_CODE 0x00000080
866 /* Reads coprocessor condition code. */
867 #define INSN_READ_COND_CODE 0x00000100
869 #define INSN_TLB 0x00000200
870 /* Reads coprocessor register other than floating point register. */
871 #define INSN_COP 0x00000400
872 /* Instruction loads value from memory, requiring delay. */
873 #define INSN_LOAD_MEMORY_DELAY 0x00000800
874 /* Instruction loads value from coprocessor, requiring delay. */
875 #define INSN_LOAD_COPROC_DELAY 0x00001000
876 /* Instruction has unconditional branch delay slot. */
877 #define INSN_UNCOND_BRANCH_DELAY 0x00002000
878 /* Instruction has conditional branch delay slot. */
879 #define INSN_COND_BRANCH_DELAY 0x00004000
880 /* Conditional branch likely: if branch not taken, insn nullified. */
881 #define INSN_COND_BRANCH_LIKELY 0x00008000
882 /* Moves to coprocessor register, requiring delay. */
883 #define INSN_COPROC_MOVE_DELAY 0x00010000
884 /* Loads coprocessor register from memory, requiring delay. */
885 #define INSN_COPROC_MEMORY_DELAY 0x00020000
886 /* Reads the HI register. */
887 #define INSN_READ_HI 0x00040000
888 /* Reads the LO register. */
889 #define INSN_READ_LO 0x00080000
890 /* Modifies the HI register. */
891 #define INSN_WRITE_HI 0x00100000
892 /* Modifies the LO register. */
893 #define INSN_WRITE_LO 0x00200000
894 /* Not to be placed in a branch delay slot, either architecturally
895 or for ease of handling (such as with instructions that take a trap). */
896 #define INSN_NO_DELAY_SLOT 0x00400000
897 /* Instruction stores value into memory. */
898 #define INSN_STORE_MEMORY 0x00800000
899 /* Instruction uses single precision floating point. */
900 #define FP_S 0x01000000
901 /* Instruction uses double precision floating point. */
902 #define FP_D 0x02000000
903 /* Instruction is part of the tx39's integer multiply family. */
904 #define INSN_MULT 0x04000000
905 /* Reads general purpose register 24. */
906 #define INSN_READ_GPR_24 0x08000000
907 /* Writes to general purpose register 24. */
908 #define INSN_WRITE_GPR_24 0x10000000
909 /* A user-defined instruction. */
910 #define INSN_UDI 0x20000000
911 /* Instruction is actually a macro. It should be ignored by the
912 disassembler, and requires special treatment by the assembler. */
913 #define INSN_MACRO 0xffffffff
915 /* These are the bits which may be set in the pinfo2 field of an
918 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
919 #define INSN2_ALIAS 0x00000001
920 /* Instruction reads MDMX accumulator. */
921 #define INSN2_READ_MDMX_ACC 0x00000002
922 /* Instruction writes MDMX accumulator. */
923 #define INSN2_WRITE_MDMX_ACC 0x00000004
924 /* Macro uses single-precision floating-point instructions. This should
925 only be set for macros. For instructions, FP_S in pinfo carries the
927 #define INSN2_M_FP_S 0x00000008
928 /* Macro uses double-precision floating-point instructions. This should
929 only be set for macros. For instructions, FP_D in pinfo carries the
931 #define INSN2_M_FP_D 0x00000010
932 /* Instruction has a branch delay slot that requires a 16-bit instruction. */
933 #define INSN2_BRANCH_DELAY_16BIT 0x00000020
934 /* Instruction has a branch delay slot that requires a 32-bit instruction. */
935 #define INSN2_BRANCH_DELAY_32BIT 0x00000040
936 /* Writes to the stack pointer ($29). */
937 #define INSN2_WRITE_SP 0x00000080
938 /* Reads from the stack pointer ($29). */
939 #define INSN2_READ_SP 0x00000100
940 /* Reads the RA ($31) register. */
941 #define INSN2_READ_GPR_31 0x00000200
942 /* Reads the program counter ($pc). */
943 #define INSN2_READ_PC 0x00000400
944 /* Is an unconditional branch insn. */
945 #define INSN2_UNCOND_BRANCH 0x00000800
946 /* Is a conditional branch insn. */
947 #define INSN2_COND_BRANCH 0x00001000
948 /* Reads from $16. This is true of the MIPS16 0x6500 nop. */
949 #define INSN2_READ_GPR_16 0x00002000
951 /* Masks used to mark instructions to indicate which MIPS ISA level
952 they were introduced in. INSN_ISA_MASK masks an enumeration that
953 specifies the base ISA level(s). The remainder of a 32-bit
954 word constructed using these macros is a bitmask of the remaining
955 INSN_* values below. */
957 #define INSN_ISA_MASK 0x0000000ful
959 /* We cannot start at zero due to ISA_UNKNOWN below. */
966 #define INSN_ISA32R2 7
968 #define INSN_ISA64R2 9
969 /* Below this point the INSN_* values correspond to combinations of ISAs.
970 They are only for use in the opcodes table to indicate membership of
971 a combination of ISAs that cannot be expressed using the usual inclusion
972 ordering on the above INSN_* values. */
973 #define INSN_ISA3_32 10
974 #define INSN_ISA3_32R2 11
975 #define INSN_ISA4_32 12
976 #define INSN_ISA4_32R2 13
977 #define INSN_ISA5_32R2 14
979 /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
980 INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
981 this table describes whether at least one of the ISAs described by X
982 is/are implemented by ISA Y. (Think of Y as the ISA level supported by
983 a particular core and X as the ISA level(s) at which a certain instruction
984 is defined.) The ISA(s) described by X is/are implemented by Y iff
985 (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
987 static const unsigned int mips_isa_table[] =
988 { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
990 /* Masks used for Chip specific instructions. */
991 #define INSN_CHIP_MASK 0xc3ff0f20
993 /* Cavium Networks Octeon instructions. */
994 #define INSN_OCTEON 0x00000800
995 #define INSN_OCTEONP 0x00000200
996 #define INSN_OCTEON2 0x00000100
998 /* MIPS R5900 instruction */
999 #define INSN_5900 0x00004000
1001 /* MIPS R4650 instruction. */
1002 #define INSN_4650 0x00010000
1003 /* LSI R4010 instruction. */
1004 #define INSN_4010 0x00020000
1005 /* NEC VR4100 instruction. */
1006 #define INSN_4100 0x00040000
1007 /* Toshiba R3900 instruction. */
1008 #define INSN_3900 0x00080000
1009 /* MIPS R10000 instruction. */
1010 #define INSN_10000 0x00100000
1011 /* Broadcom SB-1 instruction. */
1012 #define INSN_SB1 0x00200000
1013 /* NEC VR4111/VR4181 instruction. */
1014 #define INSN_4111 0x00400000
1015 /* NEC VR4120 instruction. */
1016 #define INSN_4120 0x00800000
1017 /* NEC VR5400 instruction. */
1018 #define INSN_5400 0x01000000
1019 /* NEC VR5500 instruction. */
1020 #define INSN_5500 0x02000000
1022 /* ST Microelectronics Loongson 2E. */
1023 #define INSN_LOONGSON_2E 0x40000000
1024 /* ST Microelectronics Loongson 2F. */
1025 #define INSN_LOONGSON_2F 0x80000000
1027 #define INSN_LOONGSON_3A 0x00000400
1028 /* RMI Xlr instruction */
1029 #define INSN_XLR 0x00000020
1032 #define ASE_DSP 0x00000001
1033 #define ASE_DSP64 0x00000002
1035 #define ASE_DSPR2 0x00000004
1036 /* Enhanced VA Scheme */
1037 #define ASE_EVA 0x00000008
1038 /* MCU (MicroController) ASE */
1039 #define ASE_MCU 0x00000010
1041 #define ASE_MDMX 0x00000020
1043 #define ASE_MIPS3D 0x00000040
1045 #define ASE_MT 0x00000080
1047 #define ASE_SMARTMIPS 0x00000100
1048 /* Virtualization ASE */
1049 #define ASE_VIRT 0x00000200
1050 #define ASE_VIRT64 0x00000400
1052 /* MIPS ISA defines, use instead of hardcoding ISA level. */
1054 #define ISA_UNKNOWN 0 /* Gas internal use. */
1055 #define ISA_MIPS1 INSN_ISA1
1056 #define ISA_MIPS2 INSN_ISA2
1057 #define ISA_MIPS3 INSN_ISA3
1058 #define ISA_MIPS4 INSN_ISA4
1059 #define ISA_MIPS5 INSN_ISA5
1061 #define ISA_MIPS32 INSN_ISA32
1062 #define ISA_MIPS64 INSN_ISA64
1064 #define ISA_MIPS32R2 INSN_ISA32R2
1065 #define ISA_MIPS64R2 INSN_ISA64R2
1068 /* CPU defines, use instead of hardcoding processor number. Keep this
1069 in sync with bfd/archures.c in order for machine selection to work. */
1070 #define CPU_UNKNOWN 0 /* Gas internal use. */
1071 #define CPU_R3000 3000
1072 #define CPU_R3900 3900
1073 #define CPU_R4000 4000
1074 #define CPU_R4010 4010
1075 #define CPU_VR4100 4100
1076 #define CPU_R4111 4111
1077 #define CPU_VR4120 4120
1078 #define CPU_R4300 4300
1079 #define CPU_R4400 4400
1080 #define CPU_R4600 4600
1081 #define CPU_R4650 4650
1082 #define CPU_R5000 5000
1083 #define CPU_VR5400 5400
1084 #define CPU_VR5500 5500
1085 #define CPU_R5900 5900
1086 #define CPU_R6000 6000
1087 #define CPU_RM7000 7000
1088 #define CPU_R8000 8000
1089 #define CPU_RM9000 9000
1090 #define CPU_R10000 10000
1091 #define CPU_R12000 12000
1092 #define CPU_R14000 14000
1093 #define CPU_R16000 16000
1094 #define CPU_MIPS16 16
1095 #define CPU_MIPS32 32
1096 #define CPU_MIPS32R2 33
1098 #define CPU_MIPS64 64
1099 #define CPU_MIPS64R2 65
1100 #define CPU_SB1 12310201 /* octal 'SB', 01. */
1101 #define CPU_LOONGSON_2E 3001
1102 #define CPU_LOONGSON_2F 3002
1103 #define CPU_LOONGSON_3A 3003
1104 #define CPU_OCTEON 6501
1105 #define CPU_OCTEONP 6601
1106 #define CPU_OCTEON2 6502
1107 #define CPU_XLR 887682 /* decimal 'XLR' */
1109 /* Return true if the given CPU is included in INSN_* mask MASK. */
1111 static inline bfd_boolean
1112 cpu_is_member (int cpu, unsigned int mask)
1119 return (mask & INSN_4650) != 0;
1122 return (mask & INSN_4010) != 0;
1125 return (mask & INSN_4100) != 0;
1128 return (mask & INSN_3900) != 0;
1134 return (mask & INSN_10000) != 0;
1137 return (mask & INSN_SB1) != 0;
1140 return (mask & INSN_4111) != 0;
1143 return (mask & INSN_4120) != 0;
1146 return (mask & INSN_5400) != 0;
1149 return (mask & INSN_5500) != 0;
1152 return (mask & INSN_5900) != 0;
1154 case CPU_LOONGSON_2E:
1155 return (mask & INSN_LOONGSON_2E) != 0;
1157 case CPU_LOONGSON_2F:
1158 return (mask & INSN_LOONGSON_2F) != 0;
1160 case CPU_LOONGSON_3A:
1161 return (mask & INSN_LOONGSON_3A) != 0;
1164 return (mask & INSN_OCTEON) != 0;
1167 return (mask & INSN_OCTEONP) != 0;
1170 return (mask & INSN_OCTEON2) != 0;
1173 return (mask & INSN_XLR) != 0;
1180 /* Test for membership in an ISA including chip specific ISAs. INSN
1181 is pointer to an element of the opcode table; ISA is the specified
1182 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
1183 test, or zero if no CPU specific ISA test is desired. Return true
1184 if instruction INSN is available to the given ISA and CPU. */
1186 static inline bfd_boolean
1187 opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
1189 if (!cpu_is_member (cpu, insn->exclusions))
1191 /* Test for ISA level compatibility. */
1192 if ((isa & INSN_ISA_MASK) != 0
1193 && (insn->membership & INSN_ISA_MASK) != 0
1194 && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1]
1195 >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0)
1198 /* Test for ASE compatibility. */
1199 if ((ase & insn->ase) != 0)
1202 /* Test for processor-specific extensions. */
1203 if (cpu_is_member (cpu, insn->membership))
1209 /* This is a list of macro expanded instructions.
1211 _I appended means immediate
1212 _A appended means target address of a jump
1213 _AB appended means address with (possibly zero) base register
1214 _D appended means 64 bit floating point constant
1215 _S appended means 32 bit floating point constant. */
1470 /* The order of overloaded instructions matters. Label arguments and
1471 register arguments look the same. Instructions that can have either
1472 for arguments must apear in the correct order in this table for the
1473 assembler to pick the right one. In other words, entries with
1474 immediate operands must apear after the same instruction with
1477 Many instructions are short hand for other instructions (i.e., The
1478 jal <register> instruction is short for jalr <register>). */
1480 extern const struct mips_operand *decode_mips_operand (const char *);
1481 extern const struct mips_opcode mips_builtin_opcodes[];
1482 extern const int bfd_mips_num_builtin_opcodes;
1483 extern struct mips_opcode *mips_opcodes;
1484 extern int bfd_mips_num_opcodes;
1485 #define NUMOPCODES bfd_mips_num_opcodes
1488 /* The rest of this file adds definitions for the mips16 TinyRISC
1491 /* These are the bitmasks and shift counts used for the different
1492 fields in the instruction formats. Other than OP, no masks are
1493 provided for the fixed portions of an instruction, since they are
1496 The I format uses IMM11.
1498 The RI format uses RX and IMM8.
1500 The RR format uses RX, and RY.
1502 The RRI format uses RX, RY, and IMM5.
1504 The RRR format uses RX, RY, and RZ.
1506 The RRI_A format uses RX, RY, and IMM4.
1508 The SHIFT format uses RX, RY, and SHAMT.
1510 The I8 format uses IMM8.
1512 The I8_MOVR32 format uses RY and REGR32.
1514 The IR_MOV32R format uses REG32R and MOV32Z.
1516 The I64 format uses IMM8.
1518 The RI64 format uses RY and IMM5.
1521 #define MIPS16OP_MASK_OP 0x1f
1522 #define MIPS16OP_SH_OP 11
1523 #define MIPS16OP_MASK_IMM11 0x7ff
1524 #define MIPS16OP_SH_IMM11 0
1525 #define MIPS16OP_MASK_RX 0x7
1526 #define MIPS16OP_SH_RX 8
1527 #define MIPS16OP_MASK_IMM8 0xff
1528 #define MIPS16OP_SH_IMM8 0
1529 #define MIPS16OP_MASK_RY 0x7
1530 #define MIPS16OP_SH_RY 5
1531 #define MIPS16OP_MASK_IMM5 0x1f
1532 #define MIPS16OP_SH_IMM5 0
1533 #define MIPS16OP_MASK_RZ 0x7
1534 #define MIPS16OP_SH_RZ 2
1535 #define MIPS16OP_MASK_IMM4 0xf
1536 #define MIPS16OP_SH_IMM4 0
1537 #define MIPS16OP_MASK_REGR32 0x1f
1538 #define MIPS16OP_SH_REGR32 0
1539 #define MIPS16OP_MASK_REG32R 0x1f
1540 #define MIPS16OP_SH_REG32R 3
1541 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
1542 #define MIPS16OP_MASK_MOVE32Z 0x7
1543 #define MIPS16OP_SH_MOVE32Z 0
1544 #define MIPS16OP_MASK_IMM6 0x3f
1545 #define MIPS16OP_SH_IMM6 5
1547 /* These are the characters which may appears in the args field of a MIPS16
1548 instruction. They appear in the order in which the fields appear when the
1549 instruction is used. Commas and parentheses in the args string are ignored
1550 when assembling, and written into the output when disassembling.
1552 "y" 3 bit register (MIPS16OP_*_RY)
1553 "x" 3 bit register (MIPS16OP_*_RX)
1554 "z" 3 bit register (MIPS16OP_*_RZ)
1555 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1556 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1557 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1558 "0" zero register ($0)
1559 "S" stack pointer ($sp or $29)
1561 "R" return address register ($ra or $31)
1562 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1563 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1564 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1565 "a" 26 bit jump address
1566 "i" likewise, but flips bit 0
1567 "e" 11 bit extension value
1568 "l" register list for entry instruction
1569 "L" register list for exit instruction
1571 "I" an immediate value used for macros
1573 The remaining codes may be extended. Except as otherwise noted,
1574 the full extended operand is a 16 bit signed value.
1575 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1576 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1577 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1578 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1579 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1580 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1581 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1582 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1583 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1584 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1585 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1586 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1587 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1588 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1589 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1590 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1591 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1592 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1593 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1594 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1595 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1596 "m" 7 bit register list for save instruction (18 bit extended)
1597 "M" 7 bit register list for restore instruction (18 bit extended)
1600 /* Save/restore encoding for the args field when all 4 registers are
1601 either saved as arguments or saved/restored as statics. */
1602 #define MIPS16_ALL_ARGS 0xe
1603 #define MIPS16_ALL_STATICS 0xb
1605 /* The following flags have the same value for the mips16 opcode
1610 INSN_UNCOND_BRANCH_DELAY
1611 INSN_COND_BRANCH_DELAY
1612 INSN_COND_BRANCH_LIKELY (never used)
1621 extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean);
1622 extern const struct mips_opcode mips16_opcodes[];
1623 extern const int bfd_mips16_num_opcodes;
1625 /* These are the bit masks and shift counts used for the different fields
1626 in the microMIPS instruction formats. No masks are provided for the
1627 fixed portions of an instruction, since they are not needed. */
1629 #define MICROMIPSOP_MASK_IMMEDIATE 0xffff
1630 #define MICROMIPSOP_SH_IMMEDIATE 0
1631 #define MICROMIPSOP_MASK_DELTA 0xffff
1632 #define MICROMIPSOP_SH_DELTA 0
1633 #define MICROMIPSOP_MASK_CODE10 0x3ff
1634 #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */
1635 #define MICROMIPSOP_MASK_TRAP 0xf
1636 #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */
1637 #define MICROMIPSOP_MASK_SHAMT 0x1f
1638 #define MICROMIPSOP_SH_SHAMT 11
1639 #define MICROMIPSOP_MASK_TARGET 0x3ffffff
1640 #define MICROMIPSOP_SH_TARGET 0
1641 #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */
1642 #define MICROMIPSOP_SH_EXTLSB 6
1643 #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
1644 #define MICROMIPSOP_SH_EXTMSBD 11
1645 #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */
1646 #define MICROMIPSOP_SH_INSMSB 11
1647 #define MICROMIPSOP_MASK_CODE 0x3ff
1648 #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */
1649 #define MICROMIPSOP_MASK_CODE2 0x3ff
1650 #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */
1651 #define MICROMIPSOP_MASK_CACHE 0x1f
1652 #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */
1653 #define MICROMIPSOP_MASK_SEL 0x7
1654 #define MICROMIPSOP_SH_SEL 11
1655 #define MICROMIPSOP_MASK_OFFSET12 0xfff
1656 #define MICROMIPSOP_SH_OFFSET12 0
1657 #define MICROMIPSOP_MASK_3BITPOS 0x7
1658 #define MICROMIPSOP_SH_3BITPOS 21
1659 #define MICROMIPSOP_MASK_STYPE 0x1f
1660 #define MICROMIPSOP_SH_STYPE 16
1661 #define MICROMIPSOP_MASK_OFFSET10 0x3ff
1662 #define MICROMIPSOP_SH_OFFSET10 6
1663 #define MICROMIPSOP_MASK_RS 0x1f
1664 #define MICROMIPSOP_SH_RS 16
1665 #define MICROMIPSOP_MASK_RT 0x1f
1666 #define MICROMIPSOP_SH_RT 21
1667 #define MICROMIPSOP_MASK_RD 0x1f
1668 #define MICROMIPSOP_SH_RD 11
1669 #define MICROMIPSOP_MASK_FS 0x1f
1670 #define MICROMIPSOP_SH_FS 16
1671 #define MICROMIPSOP_MASK_FT 0x1f
1672 #define MICROMIPSOP_SH_FT 21
1673 #define MICROMIPSOP_MASK_FD 0x1f
1674 #define MICROMIPSOP_SH_FD 11
1675 #define MICROMIPSOP_MASK_FR 0x1f
1676 #define MICROMIPSOP_SH_FR 6
1677 #define MICROMIPSOP_MASK_RS3 0x1f
1678 #define MICROMIPSOP_SH_RS3 6
1679 #define MICROMIPSOP_MASK_PREFX 0x1f
1680 #define MICROMIPSOP_SH_PREFX 11
1681 #define MICROMIPSOP_MASK_BCC 0x7
1682 #define MICROMIPSOP_SH_BCC 18
1683 #define MICROMIPSOP_MASK_CCC 0x7
1684 #define MICROMIPSOP_SH_CCC 13
1685 #define MICROMIPSOP_MASK_COPZ 0x7fffff
1686 #define MICROMIPSOP_SH_COPZ 3
1688 #define MICROMIPSOP_MASK_MB 0x7
1689 #define MICROMIPSOP_SH_MB 23
1690 #define MICROMIPSOP_MASK_MC 0x7
1691 #define MICROMIPSOP_SH_MC 4
1692 #define MICROMIPSOP_MASK_MD 0x7
1693 #define MICROMIPSOP_SH_MD 7
1694 #define MICROMIPSOP_MASK_ME 0x7
1695 #define MICROMIPSOP_SH_ME 1
1696 #define MICROMIPSOP_MASK_MF 0x7
1697 #define MICROMIPSOP_SH_MF 3
1698 #define MICROMIPSOP_MASK_MG 0x7
1699 #define MICROMIPSOP_SH_MG 0
1700 #define MICROMIPSOP_MASK_MH 0x7
1701 #define MICROMIPSOP_SH_MH 7
1702 #define MICROMIPSOP_MASK_MJ 0x1f
1703 #define MICROMIPSOP_SH_MJ 0
1704 #define MICROMIPSOP_MASK_ML 0x7
1705 #define MICROMIPSOP_SH_ML 4
1706 #define MICROMIPSOP_MASK_MM 0x7
1707 #define MICROMIPSOP_SH_MM 1
1708 #define MICROMIPSOP_MASK_MN 0x7
1709 #define MICROMIPSOP_SH_MN 4
1710 #define MICROMIPSOP_MASK_MP 0x1f
1711 #define MICROMIPSOP_SH_MP 5
1712 #define MICROMIPSOP_MASK_MQ 0x7
1713 #define MICROMIPSOP_SH_MQ 7
1715 #define MICROMIPSOP_MASK_IMMA 0x7f
1716 #define MICROMIPSOP_SH_IMMA 0
1717 #define MICROMIPSOP_MASK_IMMB 0x7
1718 #define MICROMIPSOP_SH_IMMB 1
1719 #define MICROMIPSOP_MASK_IMMC 0xf
1720 #define MICROMIPSOP_SH_IMMC 0
1721 #define MICROMIPSOP_MASK_IMMD 0x3ff
1722 #define MICROMIPSOP_SH_IMMD 0
1723 #define MICROMIPSOP_MASK_IMME 0x7f
1724 #define MICROMIPSOP_SH_IMME 0
1725 #define MICROMIPSOP_MASK_IMMF 0xf
1726 #define MICROMIPSOP_SH_IMMF 0
1727 #define MICROMIPSOP_MASK_IMMG 0xf
1728 #define MICROMIPSOP_SH_IMMG 0
1729 #define MICROMIPSOP_MASK_IMMH 0xf
1730 #define MICROMIPSOP_SH_IMMH 0
1731 #define MICROMIPSOP_MASK_IMMI 0x7f
1732 #define MICROMIPSOP_SH_IMMI 0
1733 #define MICROMIPSOP_MASK_IMMJ 0xf
1734 #define MICROMIPSOP_SH_IMMJ 0
1735 #define MICROMIPSOP_MASK_IMML 0xf
1736 #define MICROMIPSOP_SH_IMML 0
1737 #define MICROMIPSOP_MASK_IMMM 0x7
1738 #define MICROMIPSOP_SH_IMMM 1
1739 #define MICROMIPSOP_MASK_IMMN 0x3
1740 #define MICROMIPSOP_SH_IMMN 4
1741 #define MICROMIPSOP_MASK_IMMO 0xf
1742 #define MICROMIPSOP_SH_IMMO 0
1743 #define MICROMIPSOP_MASK_IMMP 0x1f
1744 #define MICROMIPSOP_SH_IMMP 0
1745 #define MICROMIPSOP_MASK_IMMQ 0x7fffff
1746 #define MICROMIPSOP_SH_IMMQ 0
1747 #define MICROMIPSOP_MASK_IMMU 0x1f
1748 #define MICROMIPSOP_SH_IMMU 0
1749 #define MICROMIPSOP_MASK_IMMW 0x3f
1750 #define MICROMIPSOP_SH_IMMW 1
1751 #define MICROMIPSOP_MASK_IMMX 0xf
1752 #define MICROMIPSOP_SH_IMMX 1
1753 #define MICROMIPSOP_MASK_IMMY 0x1ff
1754 #define MICROMIPSOP_SH_IMMY 1
1757 #define MICROMIPSOP_MASK_DSPACC 0x3
1758 #define MICROMIPSOP_SH_DSPACC 14
1759 #define MICROMIPSOP_MASK_DSPSFT 0x3f
1760 #define MICROMIPSOP_SH_DSPSFT 16
1761 #define MICROMIPSOP_MASK_SA3 0x7
1762 #define MICROMIPSOP_SH_SA3 13
1763 #define MICROMIPSOP_MASK_SA4 0xf
1764 #define MICROMIPSOP_SH_SA4 12
1765 #define MICROMIPSOP_MASK_IMM8 0xff
1766 #define MICROMIPSOP_SH_IMM8 13
1767 #define MICROMIPSOP_MASK_IMM10 0x3ff
1768 #define MICROMIPSOP_SH_IMM10 16
1769 #define MICROMIPSOP_MASK_WRDSP 0x3f
1770 #define MICROMIPSOP_SH_WRDSP 14
1771 #define MICROMIPSOP_MASK_BP 0x3
1772 #define MICROMIPSOP_SH_BP 14
1774 /* Placeholders for fields that only exist in the traditional 32-bit
1775 instruction encoding; see the comment above for details. */
1776 #define MICROMIPSOP_MASK_CODE20 0
1777 #define MICROMIPSOP_SH_CODE20 0
1778 #define MICROMIPSOP_MASK_PERFREG 0
1779 #define MICROMIPSOP_SH_PERFREG 0
1780 #define MICROMIPSOP_MASK_CODE19 0
1781 #define MICROMIPSOP_SH_CODE19 0
1782 #define MICROMIPSOP_MASK_ALN 0
1783 #define MICROMIPSOP_SH_ALN 0
1784 #define MICROMIPSOP_MASK_VECBYTE 0
1785 #define MICROMIPSOP_SH_VECBYTE 0
1786 #define MICROMIPSOP_MASK_VECALIGN 0
1787 #define MICROMIPSOP_SH_VECALIGN 0
1788 #define MICROMIPSOP_MASK_DSPACC_S 0
1789 #define MICROMIPSOP_SH_DSPACC_S 0
1790 #define MICROMIPSOP_MASK_DSPSFT_7 0
1791 #define MICROMIPSOP_SH_DSPSFT_7 0
1792 #define MICROMIPSOP_MASK_RDDSP 0
1793 #define MICROMIPSOP_SH_RDDSP 0
1794 #define MICROMIPSOP_MASK_MT_U 0
1795 #define MICROMIPSOP_SH_MT_U 0
1796 #define MICROMIPSOP_MASK_MT_H 0
1797 #define MICROMIPSOP_SH_MT_H 0
1798 #define MICROMIPSOP_MASK_MTACC_T 0
1799 #define MICROMIPSOP_SH_MTACC_T 0
1800 #define MICROMIPSOP_MASK_MTACC_D 0
1801 #define MICROMIPSOP_SH_MTACC_D 0
1802 #define MICROMIPSOP_MASK_BBITIND 0
1803 #define MICROMIPSOP_SH_BBITIND 0
1804 #define MICROMIPSOP_MASK_CINSPOS 0
1805 #define MICROMIPSOP_SH_CINSPOS 0
1806 #define MICROMIPSOP_MASK_CINSLM1 0
1807 #define MICROMIPSOP_SH_CINSLM1 0
1808 #define MICROMIPSOP_MASK_SEQI 0
1809 #define MICROMIPSOP_SH_SEQI 0
1810 #define MICROMIPSOP_SH_OFFSET_A 0
1811 #define MICROMIPSOP_MASK_OFFSET_A 0
1812 #define MICROMIPSOP_SH_OFFSET_B 0
1813 #define MICROMIPSOP_MASK_OFFSET_B 0
1814 #define MICROMIPSOP_SH_OFFSET_C 0
1815 #define MICROMIPSOP_MASK_OFFSET_C 0
1816 #define MICROMIPSOP_SH_RZ 0
1817 #define MICROMIPSOP_MASK_RZ 0
1818 #define MICROMIPSOP_SH_FZ 0
1819 #define MICROMIPSOP_MASK_FZ 0
1821 /* microMIPS Enhanced VA Scheme */
1822 #define MICROMIPSOP_SH_EVAOFFSET 0
1823 #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff
1825 /* These are the characters which may appears in the args field of a microMIPS
1826 instruction. They appear in the order in which the fields appear
1827 when the instruction is used. Commas and parentheses in the args
1828 string are ignored when assembling, and written into the output
1831 The followings are for 16-bit microMIPS instructions.
1834 "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4
1835 The same register used as both source and target.
1836 "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7
1837 "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1
1838 The same register used as both source and target.
1839 "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
1840 "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
1841 "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7
1842 "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
1843 "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
1844 "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
1845 "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4
1846 "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5
1847 "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7
1848 "mr" must be program counter
1850 "mt" must be the same as the previous register
1851 "mx" must be the same as the destination register
1855 "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA)
1856 "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB)
1857 "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255,
1858 32768, 65535) (MICROMIPSOP_*_IMMC)
1859 "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD)
1860 "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME)
1861 "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF)
1862 "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG)
1863 "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH)
1864 "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI)
1865 "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ)
1866 "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1867 "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM)
1868 "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN)
1869 "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML)
1870 "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP)
1871 "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU)
1872 "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW)
1873 "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX)
1874 "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY)
1877 In most cases 32-bit microMIPS instructions use the same characters
1878 as MIPS (with ADDIUPC being a notable exception, but there are some
1881 "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
1882 "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
1883 "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
1884 ">" shift amount between 32 and 63, stored after subtracting 32
1885 (MICROMIPSOP_*_SHAMT)
1886 "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS)
1887 "|" 4-bit trap code (MICROMIPSOP_*_TRAP)
1888 "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
1889 "a" 26-bit target address (MICROMIPSOP_*_TARGET)
1890 "+i" likewise, but flips bit 0
1891 "b" 5-bit base register (MICROMIPSOP_*_RS)
1892 "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
1893 "d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
1894 "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX)
1895 "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE)
1896 "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA)
1897 "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE)
1898 "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT)
1899 "o" 16-bit signed offset (MICROMIPSOP_*_DELTA)
1900 "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA)
1901 "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2)
1902 "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS)
1903 "s" 5-bit source register specifier (MICROMIPSOP_*_RS)
1904 "t" 5-bit target register (MICROMIPSOP_*_RT)
1905 "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE)
1906 "v" 5-bit same register used as both source and destination
1908 "w" 5-bit same register used as both target and destination
1910 "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
1911 "z" must be zero register
1912 "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
1913 "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
1914 "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
1916 "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
1917 LSB (MICROMIPSOP_*_EXTLSB).
1918 Enforces: 0 <= pos < 32.
1919 "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB).
1920 Requires that "+A" or "+E" occur first to set position.
1921 Enforces: 0 < (pos+size) <= 32.
1922 "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1923 Requires that "+A" or "+E" occur first to set position.
1924 Enforces: 0 < (pos+size) <= 32.
1925 (Also used by DEXT w/ different limits, but limits for
1926 that are checked by the M_DEXT macro.)
1927 "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB).
1928 Enforces: 32 <= pos < 64.
1929 "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB).
1930 Requires that "+A" or "+E" occur first to set position.
1931 Enforces: 32 < (pos+size) <= 64.
1932 "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD).
1933 Requires that "+A" or "+E" occur first to set position.
1934 Enforces: 32 < (pos+size) <= 64.
1935 "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
1936 Requires that "+A" or "+E" occur first to set position.
1937 Enforces: 32 < (pos+size) <= 64.
1939 PC-relative addition (ADDIUPC) instruction:
1940 "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
1941 "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23
1943 Floating point instructions:
1944 "D" 5-bit destination register (MICROMIPSOP_*_FD)
1945 "M" 3-bit compare condition code (MICROMIPSOP_*_CCC)
1946 "N" 3-bit branch condition code (MICROMIPSOP_*_BCC)
1947 "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR)
1948 "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS)
1949 "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT)
1950 "V" 5-bit same register used as floating source and destination or target
1953 Coprocessor instructions:
1954 "E" 5-bit target register (MICROMIPSOP_*_RT)
1955 "G" 5-bit source register (MICROMIPSOP_*_RS)
1956 "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
1959 "A" general 32 bit expression
1960 "I" 32-bit immediate (value placed in imm_expr).
1961 "+I" 32-bit immediate (value placed in imm2_expr).
1962 "F" 64-bit floating point constant in .rdata
1963 "L" 64-bit floating point constant in .lit8
1964 "f" 32-bit floating point constant
1965 "l" 32-bit floating point constant in .lit4
1968 "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
1969 "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
1970 "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
1971 "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
1972 "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
1973 "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
1974 "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
1975 "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
1976 "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
1977 "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
1979 microMIPS Enhanced VA Scheme:
1980 "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
1983 "()" parens surrounding optional value
1984 "," separates operands
1985 "+" start of extension sequence
1986 "m" start of microMIPS extension sequence
1988 Characters used so far, for quick reference when adding more:
1991 "ABCDEFGHI KLMN RST V "
1992 "abcd f hijklmnopqrstuvw yz"
1994 Extension character sequences used so far ("+" followed by the
1995 following), for quick reference when adding more:
2001 Extension character sequences used so far ("m" followed by the
2002 following), for quick reference when adding more:
2005 " BCDEFGHIJ LMNOPQ U WXYZ"
2006 " bcdefghij lmn pq st xyz"
2009 extern const struct mips_operand *decode_micromips_operand (const char *);
2010 extern const struct mips_opcode micromips_opcodes[];
2011 extern const int bfd_micromips_num_opcodes;
2013 /* A NOP insn impemented as "or at,at,zero".
2014 Used to implement -mfix-loongson2f. */
2015 #define LOONGSON2F_NOP_INSN 0x00200825
2017 #endif /* _MIPS_H_ */
projects / external / binutils.git / blob