1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc.
3 Contributed by Ralph Campbell and OSF
4 Commented and modified by Ian Lance Taylor, Cygnus Support
6 This file is part of GDB, GAS, and the GNU binutils.
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 1, or (at your option) any later version.
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
25 /* These are bit masks and shift counts to use to access the various
26 fields of an instruction. To retrieve the X field of an
27 instruction, use the expression
28 (i >> OP_SH_X) & OP_MASK_X
29 To set the same field (to j), use
30 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
32 Make sure you use fields that are appropriate for the instruction,
35 The 'i' format uses OP, RS, RT and IMMEDIATE.
37 The 'j' format uses OP and TARGET.
39 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
41 The 'b' format uses OP, RS, RT and DELTA.
43 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
45 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
47 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
48 breakpoint instruction are not defined; Kane says the breakpoint
49 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
50 only use ten bits). An optional two-operand form of break/sdbbp
51 allows the lower ten bits to be set too.
53 The syscall instruction uses SYSCALL.
55 The general coprocessor instructions use COPZ. */
57 #define OP_MASK_OP 0x3f
59 #define OP_MASK_RS 0x1f
61 #define OP_MASK_FR 0x1f
63 #define OP_MASK_FMT 0x1f
65 #define OP_MASK_BCC 0x7
67 #define OP_MASK_CODE 0x3ff
69 #define OP_MASK_CODE2 0x3ff
71 #define OP_MASK_RT 0x1f
73 #define OP_MASK_FT 0x1f
75 #define OP_MASK_CACHE 0x1f
76 #define OP_SH_CACHE 16
77 #define OP_MASK_RD 0x1f
79 #define OP_MASK_FS 0x1f
81 #define OP_MASK_PREFX 0x1f
82 #define OP_SH_PREFX 11
83 #define OP_MASK_CCC 0x7
85 #define OP_MASK_SYSCALL 0xfffff
86 #define OP_SH_SYSCALL 6
87 #define OP_MASK_SHAMT 0x1f
89 #define OP_MASK_FD 0x1f
91 #define OP_MASK_TARGET 0x3ffffff
92 #define OP_SH_TARGET 0
93 #define OP_MASK_COPZ 0x1ffffff
95 #define OP_MASK_IMMEDIATE 0xffff
96 #define OP_SH_IMMEDIATE 0
97 #define OP_MASK_DELTA 0xffff
99 #define OP_MASK_FUNCT 0x3f
100 #define OP_SH_FUNCT 0
101 #define OP_MASK_SPEC 0x3f
103 #define OP_SH_LOCC 8 /* FP condition code */
104 #define OP_SH_HICC 18 /* FP condition code */
105 #define OP_MASK_CC 0x7
106 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding */
107 #define OP_MASK_COP1NORM 0x1 /* a single bit */
108 #define OP_SH_COP1SPEC 21 /* COP1 encodings */
109 #define OP_MASK_COP1SPEC 0xf
110 #define OP_MASK_COP1SCLR 0x4
111 #define OP_MASK_COP1CMP 0x3
112 #define OP_SH_COP1CMP 4
113 #define OP_SH_FORMAT 21 /* FP short format field */
114 #define OP_MASK_FORMAT 0x7
115 #define OP_SH_TRUE 16
116 #define OP_MASK_TRUE 0x1
118 #define OP_MASK_GE 0x01
119 #define OP_SH_UNSIGNED 16
120 #define OP_MASK_UNSIGNED 0x1
121 #define OP_SH_HINT 16
122 #define OP_MASK_HINT 0x1f
123 #define OP_SH_MMI 0 /* Multimedia (parallel) op */
124 #define OP_MASK_MMI 0x3f
125 #define OP_SH_MMISUB 6
126 #define OP_MASK_MMISUB 0x1f
127 #define OP_MASK_PERFREG 0x1f /* Performance monitoring */
128 #define OP_SH_PERFREG 1
130 /* This structure holds information for a particular instruction. */
134 /* The name of the instruction. */
136 /* A string describing the arguments for this instruction. */
138 /* The basic opcode for the instruction. When assembling, this
139 opcode is modified by the arguments to produce the actual opcode
140 that is used. If pinfo is INSN_MACRO, then this is 0. */
142 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
143 relevant portions of the opcode when disassembling. If the
144 actual opcode anded with the match field equals the opcode field,
145 then we have found the correct instruction. If pinfo is
146 INSN_MACRO, then this field is the macro identifier. */
148 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
149 of bits describing the instruction, notably any relevant hazard
152 /* A collection of bits describing the instruction sets of which this
153 instruction or macro is a member. */
154 unsigned long membership;
157 /* These are the characters which may appears in the args field of an
158 instruction. They appear in the order in which the fields appear
159 when the instruction is used. Commas and parentheses in the args
160 string are ignored when assembling, and written into the output
163 Each of these characters corresponds to a mask field defined above.
165 "<" 5 bit shift amount (OP_*_SHAMT)
166 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
167 "a" 26 bit target address (OP_*_TARGET)
168 "b" 5 bit base register (OP_*_RS)
169 "c" 10 bit breakpoint code (OP_*_CODE)
170 "d" 5 bit destination register specifier (OP_*_RD)
171 "h" 5 bit prefx hint (OP_*_PREFX)
172 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
173 "j" 16 bit signed immediate (OP_*_DELTA)
174 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
175 "o" 16 bit signed offset (OP_*_DELTA)
176 "p" 16 bit PC relative branch target address (OP_*_DELTA)
177 "q" 10 bit extra breakpoint code (OP_*_CODE2)
178 "r" 5 bit same register used as both source and target (OP_*_RS)
179 "s" 5 bit source register specifier (OP_*_RS)
180 "t" 5 bit target register (OP_*_RT)
181 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
182 "v" 5 bit same register used as both source and destination (OP_*_RS)
183 "w" 5 bit same register used as both target and destination (OP_*_RT)
184 "C" 25 bit coprocessor function code (OP_*_COPZ)
185 "B" 20 bit syscall function code (OP_*_SYSCALL)
186 "x" accept and ignore register name
187 "z" must be zero register
189 Floating point instructions:
190 "D" 5 bit destination register (OP_*_FD)
191 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
192 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
193 "S" 5 bit fs source 1 register (OP_*_FS)
194 "T" 5 bit ft source 2 register (OP_*_FT)
195 "R" 5 bit fr source 3 register (OP_*_FR)
196 "V" 5 bit same register used as floating source and destination (OP_*_FS)
197 "W" 5 bit same register used as floating target and destination (OP_*_FT)
199 Coprocessor instructions:
200 "E" 5 bit target register (OP_*_RT)
201 "G" 5 bit destination register (OP_*_RD)
202 "P" 5 bit performance-monitor register (OP_*_PERFREG)
205 "A" General 32 bit expression
207 "F" 64 bit floating point constant in .rdata
208 "L" 64 bit floating point constant in .lit8
209 "f" 32 bit floating point constant
210 "l" 32 bit floating point constant in .lit4
213 "()" parens surrounding optional value
214 "," separates operands
216 Characters used so far, for quick reference when adding more:
219 "abcdfhijklopqrstuvwxz"
222 /* These are the bits which may be set in the pinfo field of an
223 instructions, if it is not equal to INSN_MACRO. */
225 /* Modifies the general purpose register in OP_*_RD. */
226 #define INSN_WRITE_GPR_D 0x00000001
227 /* Modifies the general purpose register in OP_*_RT. */
228 #define INSN_WRITE_GPR_T 0x00000002
229 /* Modifies general purpose register 31. */
230 #define INSN_WRITE_GPR_31 0x00000004
231 /* Modifies the floating point register in OP_*_FD. */
232 #define INSN_WRITE_FPR_D 0x00000008
233 /* Modifies the floating point register in OP_*_FS. */
234 #define INSN_WRITE_FPR_S 0x00000010
235 /* Modifies the floating point register in OP_*_FT. */
236 #define INSN_WRITE_FPR_T 0x00000020
237 /* Reads the general purpose register in OP_*_RS. */
238 #define INSN_READ_GPR_S 0x00000040
239 /* Reads the general purpose register in OP_*_RT. */
240 #define INSN_READ_GPR_T 0x00000080
241 /* Reads the floating point register in OP_*_FS. */
242 #define INSN_READ_FPR_S 0x00000100
243 /* Reads the floating point register in OP_*_FT. */
244 #define INSN_READ_FPR_T 0x00000200
245 /* Reads the floating point register in OP_*_FR. */
246 #define INSN_READ_FPR_R 0x00000400
247 /* Modifies coprocessor condition code. */
248 #define INSN_WRITE_COND_CODE 0x00000800
249 /* Reads coprocessor condition code. */
250 #define INSN_READ_COND_CODE 0x00001000
252 #define INSN_TLB 0x00002000
253 /* Reads coprocessor register other than floating point register. */
254 #define INSN_COP 0x00004000
255 /* Instruction loads value from memory, requiring delay. */
256 #define INSN_LOAD_MEMORY_DELAY 0x00008000
257 /* Instruction loads value from coprocessor, requiring delay. */
258 #define INSN_LOAD_COPROC_DELAY 0x00010000
259 /* Instruction has unconditional branch delay slot. */
260 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
261 /* Instruction has conditional branch delay slot. */
262 #define INSN_COND_BRANCH_DELAY 0x00040000
263 /* Conditional branch likely: if branch not taken, insn nullified. */
264 #define INSN_COND_BRANCH_LIKELY 0x00080000
265 /* Moves to coprocessor register, requiring delay. */
266 #define INSN_COPROC_MOVE_DELAY 0x00100000
267 /* Loads coprocessor register from memory, requiring delay. */
268 #define INSN_COPROC_MEMORY_DELAY 0x00200000
269 /* Reads the HI register. */
270 #define INSN_READ_HI 0x00400000
271 /* Reads the LO register. */
272 #define INSN_READ_LO 0x00800000
273 /* Modifies the HI register. */
274 #define INSN_WRITE_HI 0x01000000
275 /* Modifies the LO register. */
276 #define INSN_WRITE_LO 0x02000000
277 /* Takes a trap (easier to keep out of delay slot). */
278 #define INSN_TRAP 0x04000000
279 /* Instruction stores value into memory. */
280 #define INSN_STORE_MEMORY 0x08000000
281 /* Instruction uses single precision floating point. */
282 #define FP_S 0x10000000
283 /* Instruction uses double precision floating point. */
284 #define FP_D 0x20000000
285 /* Instruction is part of the tx39's integer multiply family. */
286 #define INSN_MULT 0x40000000
287 /* Instruction synchronize shared memory. */
288 #define INSN_SYNC 0x80000000
290 /* Instruction is actually a macro. It should be ignored by the
291 disassembler, and requires special treatment by the assembler. */
292 #define INSN_MACRO 0xffffffff
298 /* MIPS ISA field--CPU level at which insn is supported. */
299 #define INSN_ISA 0x0000000F
300 /* An instruction which is not part of any basic MIPS ISA.
301 (ie it is a chip specific instruction) */
302 #define INSN_NO_ISA 0x00000000
303 /* MIPS ISA 1 instruction. */
304 #define INSN_ISA1 0x00000001
305 /* MIPS ISA 2 instruction (R6000 or R4000). */
306 #define INSN_ISA2 0x00000002
307 /* MIPS ISA 3 instruction (R4000). */
308 #define INSN_ISA3 0x00000003
309 /* MIPS ISA 4 instruction (R8000). */
310 #define INSN_ISA4 0x00000004
311 #define INSN_ISA5 0x00000005
313 /* Chip specific instructions. These are bitmasks. */
314 /* MIPS R4650 instruction. */
315 #define INSN_4650 0x00000010
316 /* LSI R4010 instruction. */
317 #define INSN_4010 0x00000020
318 /* NEC VR4100 instruction. */
319 #define INSN_4100 0x00000040
320 /* Toshiba R3900 instruction. */
321 #define INSN_3900 0x00000080
323 /* 32-bit code running on a ISA3+ CPU. */
324 #define INSN_GP32 0x00001000
326 /* Test for membership in an ISA including chip specific ISAs.
327 INSN is pointer to an element of the opcode table; ISA is the
328 specified ISA to test against; and CPU is the CPU specific ISA
329 to test, or zero if no CPU specific ISA test is desired.
330 The gp32 arg is set when you need to force 32-bit register usage on
331 a machine with 64-bit registers; see the documentation under -mgp32
332 in the MIPS gas docs. */
334 #define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \
335 ((((insn)->membership & INSN_ISA) != 0 \
336 && ((insn)->membership & INSN_ISA) <= isa \
337 && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \
339 && ((insn)->membership & INSN_4650) != 0) \
341 && ((insn)->membership & INSN_4010) != 0) \
345 && ((insn)->membership & INSN_4100) != 0) \
347 && ((insn)->membership & INSN_3900) != 0))
349 /* This is a list of macro expanded instructions.
351 * _I appended means immediate
352 * _A appended means address
353 * _AB appended means address with base register
354 * _D appended means 64 bit floating point constant
355 * _S appended means 32 bit floating point constant
572 /* The order of overloaded instructions matters. Label arguments and
573 register arguments look the same. Instructions that can have either
574 for arguments must apear in the correct order in this table for the
575 assembler to pick the right one. In other words, entries with
576 immediate operands must apear after the same instruction with
579 Many instructions are short hand for other instructions (i.e., The
580 jal <register> instruction is short for jalr <register>). */
582 extern const struct mips_opcode mips_builtin_opcodes[];
583 extern const int bfd_mips_num_builtin_opcodes;
584 extern struct mips_opcode *mips_opcodes;
585 extern int bfd_mips_num_opcodes;
586 #define NUMOPCODES bfd_mips_num_opcodes
589 /* The rest of this file adds definitions for the mips16 TinyRISC
592 /* These are the bitmasks and shift counts used for the different
593 fields in the instruction formats. Other than OP, no masks are
594 provided for the fixed portions of an instruction, since they are
597 The I format uses IMM11.
599 The RI format uses RX and IMM8.
601 The RR format uses RX, and RY.
603 The RRI format uses RX, RY, and IMM5.
605 The RRR format uses RX, RY, and RZ.
607 The RRI_A format uses RX, RY, and IMM4.
609 The SHIFT format uses RX, RY, and SHAMT.
611 The I8 format uses IMM8.
613 The I8_MOVR32 format uses RY and REGR32.
615 The IR_MOV32R format uses REG32R and MOV32Z.
617 The I64 format uses IMM8.
619 The RI64 format uses RY and IMM5.
622 #define MIPS16OP_MASK_OP 0x1f
623 #define MIPS16OP_SH_OP 11
624 #define MIPS16OP_MASK_IMM11 0x7ff
625 #define MIPS16OP_SH_IMM11 0
626 #define MIPS16OP_MASK_RX 0x7
627 #define MIPS16OP_SH_RX 8
628 #define MIPS16OP_MASK_IMM8 0xff
629 #define MIPS16OP_SH_IMM8 0
630 #define MIPS16OP_MASK_RY 0x7
631 #define MIPS16OP_SH_RY 5
632 #define MIPS16OP_MASK_IMM5 0x1f
633 #define MIPS16OP_SH_IMM5 0
634 #define MIPS16OP_MASK_RZ 0x7
635 #define MIPS16OP_SH_RZ 2
636 #define MIPS16OP_MASK_IMM4 0xf
637 #define MIPS16OP_SH_IMM4 0
638 #define MIPS16OP_MASK_REGR32 0x1f
639 #define MIPS16OP_SH_REGR32 0
640 #define MIPS16OP_MASK_REG32R 0x1f
641 #define MIPS16OP_SH_REG32R 3
642 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
643 #define MIPS16OP_MASK_MOVE32Z 0x7
644 #define MIPS16OP_SH_MOVE32Z 0
645 #define MIPS16OP_MASK_IMM6 0x3f
646 #define MIPS16OP_SH_IMM6 5
648 /* These are the characters which may appears in the args field of an
649 instruction. They appear in the order in which the fields appear
650 when the instruction is used. Commas and parentheses in the args
651 string are ignored when assembling, and written into the output
654 "y" 3 bit register (MIPS16OP_*_RY)
655 "x" 3 bit register (MIPS16OP_*_RX)
656 "z" 3 bit register (MIPS16OP_*_RZ)
657 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
658 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
659 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
660 "0" zero register ($0)
661 "S" stack pointer ($sp or $29)
663 "R" return address register ($ra or $31)
664 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
665 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
666 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
667 "a" 26 bit jump address
668 "e" 11 bit extension value
669 "l" register list for entry instruction
670 "L" register list for exit instruction
672 The remaining codes may be extended. Except as otherwise noted,
673 the full extended operand is a 16 bit signed value.
674 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
675 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
676 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
677 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
678 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
679 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
680 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
681 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
682 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
683 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
684 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
685 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
686 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
687 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
688 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
689 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
690 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
691 "q" 11 bit branch address (MIPS16OP_*_IMM11)
692 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
693 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
694 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
697 /* For the mips16, we use the same opcode table format and a few of
698 the same flags. However, most of the flags are different. */
700 /* Modifies the register in MIPS16OP_*_RX. */
701 #define MIPS16_INSN_WRITE_X 0x00000001
702 /* Modifies the register in MIPS16OP_*_RY. */
703 #define MIPS16_INSN_WRITE_Y 0x00000002
704 /* Modifies the register in MIPS16OP_*_RZ. */
705 #define MIPS16_INSN_WRITE_Z 0x00000004
706 /* Modifies the T ($24) register. */
707 #define MIPS16_INSN_WRITE_T 0x00000008
708 /* Modifies the SP ($29) register. */
709 #define MIPS16_INSN_WRITE_SP 0x00000010
710 /* Modifies the RA ($31) register. */
711 #define MIPS16_INSN_WRITE_31 0x00000020
712 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
713 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
714 /* Reads the register in MIPS16OP_*_RX. */
715 #define MIPS16_INSN_READ_X 0x00000080
716 /* Reads the register in MIPS16OP_*_RY. */
717 #define MIPS16_INSN_READ_Y 0x00000100
718 /* Reads the register in MIPS16OP_*_MOVE32Z. */
719 #define MIPS16_INSN_READ_Z 0x00000200
720 /* Reads the T ($24) register. */
721 #define MIPS16_INSN_READ_T 0x00000400
722 /* Reads the SP ($29) register. */
723 #define MIPS16_INSN_READ_SP 0x00000800
724 /* Reads the RA ($31) register. */
725 #define MIPS16_INSN_READ_31 0x00001000
726 /* Reads the program counter. */
727 #define MIPS16_INSN_READ_PC 0x00002000
728 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
729 #define MIPS16_INSN_READ_GPR_X 0x00004000
730 /* Is a branch insn. */
731 #define MIPS16_INSN_BRANCH 0x00010000
733 /* The following flags have the same value for the mips16 opcode
735 INSN_UNCOND_BRANCH_DELAY
736 INSN_COND_BRANCH_DELAY
737 INSN_COND_BRANCH_LIKELY (never used)
746 extern const struct mips_opcode mips16_opcodes[];
747 extern const int bfd_mips16_num_opcodes;
749 #endif /* _MIPS_H_ */