1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 Free Software Foundation, Inc.
5 Contributed by Ralph Campbell and OSF
6 Commented and modified by Ian Lance Taylor, Cygnus Support
8 This file is part of GDB, GAS, and the GNU binutils.
10 GDB, GAS, and the GNU binutils are free software; you can redistribute
11 them and/or modify them under the terms of the GNU General Public
12 License as published by the Free Software Foundation; either version
13 1, or (at your option) any later version.
15 GDB, GAS, and the GNU binutils are distributed in the hope that they
16 will be useful, but WITHOUT ANY WARRANTY; without even the implied
17 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
18 the GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this file; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
27 /* These are bit masks and shift counts to use to access the various
28 fields of an instruction. To retrieve the X field of an
29 instruction, use the expression
30 (i >> OP_SH_X) & OP_MASK_X
31 To set the same field (to j), use
32 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
34 Make sure you use fields that are appropriate for the instruction,
37 The 'i' format uses OP, RS, RT and IMMEDIATE.
39 The 'j' format uses OP and TARGET.
41 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
43 The 'b' format uses OP, RS, RT and DELTA.
45 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
47 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
49 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
50 breakpoint instruction are not defined; Kane says the breakpoint
51 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
52 only use ten bits). An optional two-operand form of break/sdbbp
53 allows the lower ten bits to be set too, and MIPS32 and later
54 architectures allow 20 bits to be set with a signal operand
57 The syscall instruction uses CODE20.
59 The general coprocessor instructions use COPZ. */
61 #define OP_MASK_OP 0x3f
63 #define OP_MASK_RS 0x1f
65 #define OP_MASK_FR 0x1f
67 #define OP_MASK_FMT 0x1f
69 #define OP_MASK_BCC 0x7
71 #define OP_MASK_CODE 0x3ff
73 #define OP_MASK_CODE2 0x3ff
75 #define OP_MASK_RT 0x1f
77 #define OP_MASK_FT 0x1f
79 #define OP_MASK_CACHE 0x1f
80 #define OP_SH_CACHE 16
81 #define OP_MASK_RD 0x1f
83 #define OP_MASK_FS 0x1f
85 #define OP_MASK_PREFX 0x1f
86 #define OP_SH_PREFX 11
87 #define OP_MASK_CCC 0x7
89 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
90 #define OP_SH_CODE20 6
91 #define OP_MASK_SHAMT 0x1f
93 #define OP_MASK_FD 0x1f
95 #define OP_MASK_TARGET 0x3ffffff
96 #define OP_SH_TARGET 0
97 #define OP_MASK_COPZ 0x1ffffff
99 #define OP_MASK_IMMEDIATE 0xffff
100 #define OP_SH_IMMEDIATE 0
101 #define OP_MASK_DELTA 0xffff
102 #define OP_SH_DELTA 0
103 #define OP_MASK_FUNCT 0x3f
104 #define OP_SH_FUNCT 0
105 #define OP_MASK_SPEC 0x3f
107 #define OP_SH_LOCC 8 /* FP condition code. */
108 #define OP_SH_HICC 18 /* FP condition code. */
109 #define OP_MASK_CC 0x7
110 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
111 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
112 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
113 #define OP_MASK_COP1SPEC 0xf
114 #define OP_MASK_COP1SCLR 0x4
115 #define OP_MASK_COP1CMP 0x3
116 #define OP_SH_COP1CMP 4
117 #define OP_SH_FORMAT 21 /* FP short format field. */
118 #define OP_MASK_FORMAT 0x7
119 #define OP_SH_TRUE 16
120 #define OP_MASK_TRUE 0x1
122 #define OP_MASK_GE 0x01
123 #define OP_SH_UNSIGNED 16
124 #define OP_MASK_UNSIGNED 0x1
125 #define OP_SH_HINT 16
126 #define OP_MASK_HINT 0x1f
127 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
128 #define OP_MASK_MMI 0x3f
129 #define OP_SH_MMISUB 6
130 #define OP_MASK_MMISUB 0x1f
131 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
132 #define OP_SH_PERFREG 1
133 #define OP_SH_SEL 0 /* Coprocessor select field. */
134 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
135 #define OP_SH_CODE19 6 /* 19 bit wait code. */
136 #define OP_MASK_CODE19 0x7ffff
138 #define OP_MASK_ALN 0x7
139 #define OP_SH_VSEL 21
140 #define OP_MASK_VSEL 0x1f
141 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
142 but 0x8-0xf don't select bytes. */
143 #define OP_SH_VECBYTE 22
144 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
145 #define OP_SH_VECALIGN 21
146 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
147 #define OP_SH_INSMSB 11
148 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
149 #define OP_SH_EXTMSBD 11
152 #define OP_SH_DSPACC 11
153 #define OP_MASK_DSPACC 0x3
154 #define OP_SH_DSPACC_S 21
155 #define OP_MASK_DSPACC_S 0x3
156 #define OP_SH_DSPSFT 20
157 #define OP_MASK_DSPSFT 0x3f
158 #define OP_SH_DSPSFT_7 19
159 #define OP_MASK_DSPSFT_7 0x7f
161 #define OP_MASK_SA3 0x7
163 #define OP_MASK_SA4 0xf
164 #define OP_SH_IMM8 16
165 #define OP_MASK_IMM8 0xff
166 #define OP_SH_IMM10 16
167 #define OP_MASK_IMM10 0x3ff
168 #define OP_SH_WRDSP 11
169 #define OP_MASK_WRDSP 0x3f
170 #define OP_SH_RDDSP 16
171 #define OP_MASK_RDDSP 0x3f
175 #define OP_MASK_MT_U 0x1
177 #define OP_MASK_MT_H 0x1
178 #define OP_SH_MTACC_T 18
179 #define OP_MASK_MTACC_T 0x3
180 #define OP_SH_MTACC_D 13
181 #define OP_MASK_MTACC_D 0x3
183 #define OP_OP_COP0 0x10
184 #define OP_OP_COP1 0x11
185 #define OP_OP_COP2 0x12
186 #define OP_OP_COP3 0x13
187 #define OP_OP_LWC1 0x31
188 #define OP_OP_LWC2 0x32
189 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
190 #define OP_OP_LDC1 0x35
191 #define OP_OP_LDC2 0x36
192 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
193 #define OP_OP_SWC1 0x39
194 #define OP_OP_SWC2 0x3a
195 #define OP_OP_SWC3 0x3b
196 #define OP_OP_SDC1 0x3d
197 #define OP_OP_SDC2 0x3e
198 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
200 /* Values in the 'VSEL' field. */
201 #define MDMX_FMTSEL_IMM_QH 0x1d
202 #define MDMX_FMTSEL_IMM_OB 0x1e
203 #define MDMX_FMTSEL_VEC_QH 0x15
204 #define MDMX_FMTSEL_VEC_OB 0x16
206 /* This structure holds information for a particular instruction. */
210 /* The name of the instruction. */
212 /* A string describing the arguments for this instruction. */
214 /* The basic opcode for the instruction. When assembling, this
215 opcode is modified by the arguments to produce the actual opcode
216 that is used. If pinfo is INSN_MACRO, then this is 0. */
218 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
219 relevant portions of the opcode when disassembling. If the
220 actual opcode anded with the match field equals the opcode field,
221 then we have found the correct instruction. If pinfo is
222 INSN_MACRO, then this field is the macro identifier. */
224 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
225 of bits describing the instruction, notably any relevant hazard
228 /* A collection of additional bits describing the instruction. */
229 unsigned long pinfo2;
230 /* A collection of bits describing the instruction sets of which this
231 instruction or macro is a member. */
232 unsigned long membership;
235 /* These are the characters which may appear in the args field of an
236 instruction. They appear in the order in which the fields appear
237 when the instruction is used. Commas and parentheses in the args
238 string are ignored when assembling, and written into the output
241 Each of these characters corresponds to a mask field defined above.
243 "<" 5 bit shift amount (OP_*_SHAMT)
244 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
245 "a" 26 bit target address (OP_*_TARGET)
246 "b" 5 bit base register (OP_*_RS)
247 "c" 10 bit breakpoint code (OP_*_CODE)
248 "d" 5 bit destination register specifier (OP_*_RD)
249 "h" 5 bit prefx hint (OP_*_PREFX)
250 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
251 "j" 16 bit signed immediate (OP_*_DELTA)
252 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
253 Also used for immediate operands in vr5400 vector insns.
254 "o" 16 bit signed offset (OP_*_DELTA)
255 "p" 16 bit PC relative branch target address (OP_*_DELTA)
256 "q" 10 bit extra breakpoint code (OP_*_CODE2)
257 "r" 5 bit same register used as both source and target (OP_*_RS)
258 "s" 5 bit source register specifier (OP_*_RS)
259 "t" 5 bit target register (OP_*_RT)
260 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
261 "v" 5 bit same register used as both source and destination (OP_*_RS)
262 "w" 5 bit same register used as both target and destination (OP_*_RT)
263 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
264 (used by clo and clz)
265 "C" 25 bit coprocessor function code (OP_*_COPZ)
266 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
267 "J" 19 bit wait function code (OP_*_CODE19)
268 "x" accept and ignore register name
269 "z" must be zero register
270 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
271 "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT).
272 Enforces: 0 <= pos < 32.
273 "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB).
274 Requires that "+A" or "+E" occur first to set position.
275 Enforces: 0 < (pos+size) <= 32.
276 "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD).
277 Requires that "+A" or "+E" occur first to set position.
278 Enforces: 0 < (pos+size) <= 32.
279 (Also used by "dext" w/ different limits, but limits for
280 that are checked by the M_DEXT macro.)
281 "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT).
282 Enforces: 32 <= pos < 64.
283 "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB).
284 Requires that "+A" or "+E" occur first to set position.
285 Enforces: 32 < (pos+size) <= 64.
286 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
287 Requires that "+A" or "+E" occur first to set position.
288 Enforces: 32 < (pos+size) <= 64.
289 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
290 Requires that "+A" or "+E" occur first to set position.
291 Enforces: 32 < (pos+size) <= 64.
293 Floating point instructions:
294 "D" 5 bit destination register (OP_*_FD)
295 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
296 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
297 "S" 5 bit fs source 1 register (OP_*_FS)
298 "T" 5 bit ft source 2 register (OP_*_FT)
299 "R" 5 bit fr source 3 register (OP_*_FR)
300 "V" 5 bit same register used as floating source and destination (OP_*_FS)
301 "W" 5 bit same register used as floating target and destination (OP_*_FT)
303 Coprocessor instructions:
304 "E" 5 bit target register (OP_*_RT)
305 "G" 5 bit destination register (OP_*_RD)
306 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
307 "P" 5 bit performance-monitor register (OP_*_PERFREG)
308 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
309 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
311 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
312 for pretty-printing in disassembly only.
315 "A" General 32 bit expression
316 "I" 32 bit immediate (value placed in imm_expr).
317 "+I" 32 bit immediate (value placed in imm2_expr).
318 "F" 64 bit floating point constant in .rdata
319 "L" 64 bit floating point constant in .lit8
320 "f" 32 bit floating point constant
321 "l" 32 bit floating point constant in .lit4
323 MDMX instruction operands (note that while these use the FP register
324 fields, they accept both $fN and $vN names for the registers):
325 "O" MDMX alignment offset (OP_*_ALN)
326 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
327 "X" MDMX destination register (OP_*_FD)
328 "Y" MDMX source register (OP_*_FS)
329 "Z" MDMX source register (OP_*_FT)
332 "3" 3 bit unsigned immediate (OP_*_SA3)
333 "4" 4 bit unsigned immediate (OP_*_SA4)
334 "5" 8 bit unsigned immediate (OP_*_IMM8)
335 "6" 5 bit unsigned immediate (OP_*_RS)
336 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
337 "8" 6 bit unsigned immediate (OP_*_WRDSP)
338 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
339 "0" 6 bit signed immediate (OP_*_DSPSFT)
340 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
341 "'" 6 bit unsigned immediate (OP_*_RDDSP)
342 "@" 10 bit signed immediate (OP_*_IMM10)
345 "!" 1 bit immediate at bit 5
346 "$" 1 bit immediate at bit 4
347 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
348 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
349 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
350 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
351 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
354 "()" parens surrounding optional value
355 "," separates operands
356 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
357 "+" Start of extension sequence.
359 Characters used so far, for quick reference when adding more:
362 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
363 "abcdefghijklopqrstuvwxz"
365 Extension character sequences used so far ("+" followed by the
366 following), for quick reference when adding more:
371 /* These are the bits which may be set in the pinfo field of an
372 instructions, if it is not equal to INSN_MACRO. */
374 /* Modifies the general purpose register in OP_*_RD. */
375 #define INSN_WRITE_GPR_D 0x00000001
376 /* Modifies the general purpose register in OP_*_RT. */
377 #define INSN_WRITE_GPR_T 0x00000002
378 /* Modifies general purpose register 31. */
379 #define INSN_WRITE_GPR_31 0x00000004
380 /* Modifies the floating point register in OP_*_FD. */
381 #define INSN_WRITE_FPR_D 0x00000008
382 /* Modifies the floating point register in OP_*_FS. */
383 #define INSN_WRITE_FPR_S 0x00000010
384 /* Modifies the floating point register in OP_*_FT. */
385 #define INSN_WRITE_FPR_T 0x00000020
386 /* Reads the general purpose register in OP_*_RS. */
387 #define INSN_READ_GPR_S 0x00000040
388 /* Reads the general purpose register in OP_*_RT. */
389 #define INSN_READ_GPR_T 0x00000080
390 /* Reads the floating point register in OP_*_FS. */
391 #define INSN_READ_FPR_S 0x00000100
392 /* Reads the floating point register in OP_*_FT. */
393 #define INSN_READ_FPR_T 0x00000200
394 /* Reads the floating point register in OP_*_FR. */
395 #define INSN_READ_FPR_R 0x00000400
396 /* Modifies coprocessor condition code. */
397 #define INSN_WRITE_COND_CODE 0x00000800
398 /* Reads coprocessor condition code. */
399 #define INSN_READ_COND_CODE 0x00001000
401 #define INSN_TLB 0x00002000
402 /* Reads coprocessor register other than floating point register. */
403 #define INSN_COP 0x00004000
404 /* Instruction loads value from memory, requiring delay. */
405 #define INSN_LOAD_MEMORY_DELAY 0x00008000
406 /* Instruction loads value from coprocessor, requiring delay. */
407 #define INSN_LOAD_COPROC_DELAY 0x00010000
408 /* Instruction has unconditional branch delay slot. */
409 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
410 /* Instruction has conditional branch delay slot. */
411 #define INSN_COND_BRANCH_DELAY 0x00040000
412 /* Conditional branch likely: if branch not taken, insn nullified. */
413 #define INSN_COND_BRANCH_LIKELY 0x00080000
414 /* Moves to coprocessor register, requiring delay. */
415 #define INSN_COPROC_MOVE_DELAY 0x00100000
416 /* Loads coprocessor register from memory, requiring delay. */
417 #define INSN_COPROC_MEMORY_DELAY 0x00200000
418 /* Reads the HI register. */
419 #define INSN_READ_HI 0x00400000
420 /* Reads the LO register. */
421 #define INSN_READ_LO 0x00800000
422 /* Modifies the HI register. */
423 #define INSN_WRITE_HI 0x01000000
424 /* Modifies the LO register. */
425 #define INSN_WRITE_LO 0x02000000
426 /* Takes a trap (easier to keep out of delay slot). */
427 #define INSN_TRAP 0x04000000
428 /* Instruction stores value into memory. */
429 #define INSN_STORE_MEMORY 0x08000000
430 /* Instruction uses single precision floating point. */
431 #define FP_S 0x10000000
432 /* Instruction uses double precision floating point. */
433 #define FP_D 0x20000000
434 /* Instruction is part of the tx39's integer multiply family. */
435 #define INSN_MULT 0x40000000
436 /* Instruction synchronize shared memory. */
437 #define INSN_SYNC 0x80000000
439 /* These are the bits which may be set in the pinfo2 field of an
442 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
443 #define INSN2_ALIAS 0x00000001
444 /* Instruction reads MDMX accumulator. */
445 #define INSN2_READ_MDMX_ACC 0x00000002
446 /* Instruction writes MDMX accumulator. */
447 #define INSN2_WRITE_MDMX_ACC 0x00000004
449 /* Instruction is actually a macro. It should be ignored by the
450 disassembler, and requires special treatment by the assembler. */
451 #define INSN_MACRO 0xffffffff
453 /* Masks used to mark instructions to indicate which MIPS ISA level
454 they were introduced in. ISAs, as defined below, are logical
455 ORs of these bits, indicating that they support the instructions
456 defined at the given level. */
458 #define INSN_ISA_MASK 0x00000fff
459 #define INSN_ISA1 0x00000001
460 #define INSN_ISA2 0x00000002
461 #define INSN_ISA3 0x00000004
462 #define INSN_ISA4 0x00000008
463 #define INSN_ISA5 0x00000010
464 #define INSN_ISA32 0x00000020
465 #define INSN_ISA64 0x00000040
466 #define INSN_ISA32R2 0x00000080
467 #define INSN_ISA64R2 0x00000100
469 /* Masks used for MIPS-defined ASEs. */
470 #define INSN_ASE_MASK 0x0400f000
473 #define INSN_DSP 0x00001000
475 #define INSN_MIPS16 0x00002000
477 #define INSN_MIPS3D 0x00004000
479 #define INSN_MDMX 0x00008000
481 /* Chip specific instructions. These are bitmasks. */
483 /* MIPS R4650 instruction. */
484 #define INSN_4650 0x00010000
485 /* LSI R4010 instruction. */
486 #define INSN_4010 0x00020000
487 /* NEC VR4100 instruction. */
488 #define INSN_4100 0x00040000
489 /* Toshiba R3900 instruction. */
490 #define INSN_3900 0x00080000
491 /* MIPS R10000 instruction. */
492 #define INSN_10000 0x00100000
493 /* Broadcom SB-1 instruction. */
494 #define INSN_SB1 0x00200000
495 /* NEC VR4111/VR4181 instruction. */
496 #define INSN_4111 0x00400000
497 /* NEC VR4120 instruction. */
498 #define INSN_4120 0x00800000
499 /* NEC VR5400 instruction. */
500 #define INSN_5400 0x01000000
501 /* NEC VR5500 instruction. */
502 #define INSN_5500 0x02000000
504 #define INSN_MT 0x04000000
506 /* MIPS ISA defines, use instead of hardcoding ISA level. */
508 #define ISA_UNKNOWN 0 /* Gas internal use. */
509 #define ISA_MIPS1 (INSN_ISA1)
510 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
511 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
512 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
513 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
515 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
516 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
518 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
519 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
522 /* CPU defines, use instead of hardcoding processor number. Keep this
523 in sync with bfd/archures.c in order for machine selection to work. */
524 #define CPU_UNKNOWN 0 /* Gas internal use. */
525 #define CPU_R3000 3000
526 #define CPU_R3900 3900
527 #define CPU_R4000 4000
528 #define CPU_R4010 4010
529 #define CPU_VR4100 4100
530 #define CPU_R4111 4111
531 #define CPU_VR4120 4120
532 #define CPU_R4300 4300
533 #define CPU_R4400 4400
534 #define CPU_R4600 4600
535 #define CPU_R4650 4650
536 #define CPU_R5000 5000
537 #define CPU_VR5400 5400
538 #define CPU_VR5500 5500
539 #define CPU_R6000 6000
540 #define CPU_RM7000 7000
541 #define CPU_R8000 8000
542 #define CPU_RM9000 9000
543 #define CPU_R10000 10000
544 #define CPU_R12000 12000
545 #define CPU_MIPS16 16
546 #define CPU_MIPS32 32
547 #define CPU_MIPS32R2 33
549 #define CPU_MIPS64 64
550 #define CPU_MIPS64R2 65
551 #define CPU_SB1 12310201 /* octal 'SB', 01. */
553 /* Test for membership in an ISA including chip specific ISAs. INSN
554 is pointer to an element of the opcode table; ISA is the specified
555 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
556 test, or zero if no CPU specific ISA test is desired. */
558 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
559 (((insn)->membership & isa) != 0 \
560 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
561 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
562 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
563 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
564 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
565 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
566 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
567 && ((insn)->membership & INSN_10000) != 0) \
568 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
569 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
570 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
571 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
572 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
573 || 0) /* Please keep this term for easier source merging. */
575 /* This is a list of macro expanded instructions.
577 _I appended means immediate
578 _A appended means address
579 _AB appended means address with base register
580 _D appended means 64 bit floating point constant
581 _S appended means 32 bit floating point constant. */
808 /* The order of overloaded instructions matters. Label arguments and
809 register arguments look the same. Instructions that can have either
810 for arguments must apear in the correct order in this table for the
811 assembler to pick the right one. In other words, entries with
812 immediate operands must apear after the same instruction with
815 Many instructions are short hand for other instructions (i.e., The
816 jal <register> instruction is short for jalr <register>). */
818 extern const struct mips_opcode mips_builtin_opcodes[];
819 extern const int bfd_mips_num_builtin_opcodes;
820 extern struct mips_opcode *mips_opcodes;
821 extern int bfd_mips_num_opcodes;
822 #define NUMOPCODES bfd_mips_num_opcodes
825 /* The rest of this file adds definitions for the mips16 TinyRISC
828 /* These are the bitmasks and shift counts used for the different
829 fields in the instruction formats. Other than OP, no masks are
830 provided for the fixed portions of an instruction, since they are
833 The I format uses IMM11.
835 The RI format uses RX and IMM8.
837 The RR format uses RX, and RY.
839 The RRI format uses RX, RY, and IMM5.
841 The RRR format uses RX, RY, and RZ.
843 The RRI_A format uses RX, RY, and IMM4.
845 The SHIFT format uses RX, RY, and SHAMT.
847 The I8 format uses IMM8.
849 The I8_MOVR32 format uses RY and REGR32.
851 The IR_MOV32R format uses REG32R and MOV32Z.
853 The I64 format uses IMM8.
855 The RI64 format uses RY and IMM5.
858 #define MIPS16OP_MASK_OP 0x1f
859 #define MIPS16OP_SH_OP 11
860 #define MIPS16OP_MASK_IMM11 0x7ff
861 #define MIPS16OP_SH_IMM11 0
862 #define MIPS16OP_MASK_RX 0x7
863 #define MIPS16OP_SH_RX 8
864 #define MIPS16OP_MASK_IMM8 0xff
865 #define MIPS16OP_SH_IMM8 0
866 #define MIPS16OP_MASK_RY 0x7
867 #define MIPS16OP_SH_RY 5
868 #define MIPS16OP_MASK_IMM5 0x1f
869 #define MIPS16OP_SH_IMM5 0
870 #define MIPS16OP_MASK_RZ 0x7
871 #define MIPS16OP_SH_RZ 2
872 #define MIPS16OP_MASK_IMM4 0xf
873 #define MIPS16OP_SH_IMM4 0
874 #define MIPS16OP_MASK_REGR32 0x1f
875 #define MIPS16OP_SH_REGR32 0
876 #define MIPS16OP_MASK_REG32R 0x1f
877 #define MIPS16OP_SH_REG32R 3
878 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
879 #define MIPS16OP_MASK_MOVE32Z 0x7
880 #define MIPS16OP_SH_MOVE32Z 0
881 #define MIPS16OP_MASK_IMM6 0x3f
882 #define MIPS16OP_SH_IMM6 5
884 /* These are the characters which may appears in the args field of an
885 instruction. They appear in the order in which the fields appear
886 when the instruction is used. Commas and parentheses in the args
887 string are ignored when assembling, and written into the output
890 "y" 3 bit register (MIPS16OP_*_RY)
891 "x" 3 bit register (MIPS16OP_*_RX)
892 "z" 3 bit register (MIPS16OP_*_RZ)
893 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
894 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
895 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
896 "0" zero register ($0)
897 "S" stack pointer ($sp or $29)
899 "R" return address register ($ra or $31)
900 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
901 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
902 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
903 "a" 26 bit jump address
904 "e" 11 bit extension value
905 "l" register list for entry instruction
906 "L" register list for exit instruction
908 The remaining codes may be extended. Except as otherwise noted,
909 the full extended operand is a 16 bit signed value.
910 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
911 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
912 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
913 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
914 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
915 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
916 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
917 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
918 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
919 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
920 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
921 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
922 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
923 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
924 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
925 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
926 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
927 "q" 11 bit branch address (MIPS16OP_*_IMM11)
928 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
929 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
930 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
931 "m" 7 bit register list for save instruction (18 bit extended)
932 "M" 7 bit register list for restore instruction (18 bit extended)
935 /* Save/restore encoding for the args field when all 4 registers are
936 either saved as arguments or saved/restored as statics. */
937 #define MIPS16_ALL_ARGS 0xe
938 #define MIPS16_ALL_STATICS 0xb
940 /* For the mips16, we use the same opcode table format and a few of
941 the same flags. However, most of the flags are different. */
943 /* Modifies the register in MIPS16OP_*_RX. */
944 #define MIPS16_INSN_WRITE_X 0x00000001
945 /* Modifies the register in MIPS16OP_*_RY. */
946 #define MIPS16_INSN_WRITE_Y 0x00000002
947 /* Modifies the register in MIPS16OP_*_RZ. */
948 #define MIPS16_INSN_WRITE_Z 0x00000004
949 /* Modifies the T ($24) register. */
950 #define MIPS16_INSN_WRITE_T 0x00000008
951 /* Modifies the SP ($29) register. */
952 #define MIPS16_INSN_WRITE_SP 0x00000010
953 /* Modifies the RA ($31) register. */
954 #define MIPS16_INSN_WRITE_31 0x00000020
955 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
956 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
957 /* Reads the register in MIPS16OP_*_RX. */
958 #define MIPS16_INSN_READ_X 0x00000080
959 /* Reads the register in MIPS16OP_*_RY. */
960 #define MIPS16_INSN_READ_Y 0x00000100
961 /* Reads the register in MIPS16OP_*_MOVE32Z. */
962 #define MIPS16_INSN_READ_Z 0x00000200
963 /* Reads the T ($24) register. */
964 #define MIPS16_INSN_READ_T 0x00000400
965 /* Reads the SP ($29) register. */
966 #define MIPS16_INSN_READ_SP 0x00000800
967 /* Reads the RA ($31) register. */
968 #define MIPS16_INSN_READ_31 0x00001000
969 /* Reads the program counter. */
970 #define MIPS16_INSN_READ_PC 0x00002000
971 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
972 #define MIPS16_INSN_READ_GPR_X 0x00004000
973 /* Is a branch insn. */
974 #define MIPS16_INSN_BRANCH 0x00010000
976 /* The following flags have the same value for the mips16 opcode
978 INSN_UNCOND_BRANCH_DELAY
979 INSN_COND_BRANCH_DELAY
980 INSN_COND_BRANCH_LIKELY (never used)
989 extern const struct mips_opcode mips16_opcodes[];
990 extern const int bfd_mips16_num_opcodes;
992 #endif /* _MIPS_H_ */