1 /* Table of opcodes for the PA-RISC.
2 Copyright (C) 1990, 1991, 1993, 1995, 1999 Free Software Foundation, Inc.
4 Contributed by the Center for Software Science at the
5 University of Utah (pa-gdb-bugs@cs.utah.edu).
7 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 1, or (at your option)
14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS or GDB; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
23 #if !defined(__STDC__) && !defined(const)
28 * Structure of an opcode table entry.
31 /* There are two kinds of delay slot nullification: normal which is
32 * controled by the nullification bit, and conditional, which depends
33 * on the direction of the branch and its success or failure.
35 * NONE is unfortunately #defined in the hiux system include files.
42 unsigned long int match; /* Bits that must be set... */
43 unsigned long int mask; /* ... in these bits. */
50 All hppa opcodes are 32 bits.
52 The match component is a mask saying which bits must match a
53 particular opcode in order for an instruction to be an instance
56 The args component is a string containing one character
57 for each operand of the instruction.
59 Bit positions in this description follow HP usage of lsb = 31,
62 In the args field, the following characters must match exactly:
66 In the args field, the following characters are unused:
72 Here are all the characters:
74 ' !"#$%&'()*+-,./0123456789:;<=>?@'
75 'ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
76 'abcdefghijklmnopqrstuvwxyz{|}~'
79 x integer register field at 15.
80 b integer register field at 10.
81 t integer register field at 31.
82 y floating point register field at 31
83 5 5 bit immediate at 15.
84 s 2 bit space specifier at 17.
85 S 3 bit space specifier at 18.
86 c indexed load completer.
87 C short load and store completer.
88 Y Store Bytes Short completer
89 < non-negated compare/subtract conditions.
90 a compare/subtract conditions
91 d non-negated add conditions
92 & logical instruction conditions
93 U unit instruction conditions
94 > shift/extract/deposit conditions.
96 V 5 bit immediate value at 31
97 i 11 bit immediate value at 31
98 j 14 bit immediate value at 31
99 k 21 bit immediate value at 31
100 n nullification for branch instructions
101 N nullification for spop and copr instructions
102 w 12 bit branch displacement
103 W 17 bit branch displacement (PC relative)
104 z 17 bit branch displacement (just a number, not an address)
108 p 5 bit shift count at 26 (to support the SHD instruction) encoded as
110 P 5 bit bit position at 26
111 T 5 bit field length at 31 (encoded as 32-T)
112 A 13 bit immediate at 18 (to support the BREAK instruction)
113 ^ like b, but describes a control register
114 Z System Control Completer (to support LPA, LHA, etc.)
115 D 26 bit immediate at 31 (to support the DIAG instruction)
117 f 3 bit Special Function Unit identifier at 25
118 O 20 bit Special Function Unit operation split between 15 bits at 20
120 o 15 bit Special Function Unit operation at 20
121 2 22 bit Special Function Unit operation split between 17 bits at 20
123 1 15 bit Special Function Unit operation split between 10 bits at 20
125 0 10 bit Special Function Unit operation split between 5 bits at 20
127 u 3 bit coprocessor unit identifier at 25
128 F Source Floating Point Operand Format Completer encoded 2 bits at 20
129 I Source Floating Point Operand Format Completer encoded 1 bits at 20
130 (for 0xe format FP instructions)
131 G Destination Floating Point Operand Format Completer encoded 2 bits at 18
132 M Floating-Point Compare Conditions (encoded as 5 bits at 31)
133 ? non-negated/negated compare/subtract conditions.
134 @ non-negated/negated add conditions.
135 ! non-negated add conditions.
137 s 2 bit space specifier at 17.
138 b register field at 10.
139 r 5 bit immediate value at 31 (for the break instruction)
140 (very similar to V above, except the value is unsigned instead of
142 R 5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
143 (same as r above, except the value is in a different location)
144 Q 5 bit immediate value at 10 (a bit position specified in
145 the bb instruction. It's the same as r above, except the
146 value is in a different location)
147 | shift/extract/deposit conditions when used in a conditional branch
149 And these (PJH) for PA-89 F.P. registers and instructions:
151 v a 't' operand type extended to handle L/R register halves.
152 E a 'b' operand type extended to handle L/R register halves.
153 X an 'x' operand type extended to handle L/R register halves.
154 J a 'b' operand type further extended to handle extra 1.1 registers
155 K a 'x' operand type further extended to handle extra 1.1 registers
156 4 a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub'
157 6 a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub'
158 7 a variation of the 't' operand type for 'fmpyadd' and 'fmpysub'
159 8 5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub')
160 9 5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub')
161 H Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
162 (very similar to 'F')
166 /* List of characters not to put a space after. Note that
167 "," is included, as the "spopN" operations use literal
168 commas in their completer sections. */
169 static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
171 /* The order of the opcodes in this table is significant:
173 * The assembler requires that all instances of the same mnemonic must be
174 consecutive. If they aren't, the assembler will bomb at runtime.
176 * The disassembler should not care about the order of the opcodes. */
178 static const struct pa_opcode pa_opcodes[] =
182 /* pseudo-instructions */
184 { "b", 0xe8000000, 0xffe0e000, "nW", pa10}, /* bl foo,r0 */
185 { "ldi", 0x34000000, 0xffe0c000, "j,x", pa10}, /* ldo val(r0),r */
186 { "comib", 0x84000000, 0xfc000000, "?n5,b,w", pa10}, /* comib{tf}*/
187 /* This entry is for the disassembler only. It will never be used by
189 { "comib", 0x8c000000, 0xfc000000, "?n5,b,w", pa10}, /* comib{tf}*/
190 { "comb", 0x80000000, 0xfc000000, "?nx,b,w", pa10}, /* comb{tf} */
191 /* This entry is for the disassembler only. It will never be used by
193 { "comb", 0x88000000, 0xfc000000, "?nx,b,w", pa10}, /* comb{tf} */
194 { "addb", 0xa0000000, 0xfc000000, "@nx,b,w", pa10}, /* addb{tf} */
195 /* This entry is for the disassembler only. It will never be used by
197 { "addb", 0xa8000000, 0xfc000000, "@nx,b,w", pa10},
198 { "addib", 0xa4000000, 0xfc000000, "@n5,b,w", pa10}, /* addib{tf}*/
199 /* This entry is for the disassembler only. It will never be used by
201 { "addib", 0xac000000, 0xfc000000, "@n5,b,w", pa10}, /* addib{tf}*/
202 { "nop", 0x08000240, 0xffffffff, "", pa10}, /* or 0,0,0 */
203 { "copy", 0x08000240, 0xffe0ffe0, "x,t", pa10}, /* or r,0,t */
204 { "mtsar", 0x01601840, 0xffe0ffff, "x", pa10}, /* mtctl r,cr11 */
206 /* Loads and Stores for integer registers. */
207 { "ldw", 0x48000000, 0xfc000000, "j(s,b),x", pa10},
208 { "ldw", 0x48000000, 0xfc000000, "j(b),x", pa10},
209 { "ldh", 0x44000000, 0xfc000000, "j(s,b),x", pa10},
210 { "ldh", 0x44000000, 0xfc000000, "j(b),x", pa10},
211 { "ldb", 0x40000000, 0xfc000000, "j(s,b),x", pa10},
212 { "ldb", 0x40000000, 0xfc000000, "j(b),x", pa10},
213 { "stw", 0x68000000, 0xfc000000, "x,j(s,b)", pa10},
214 { "stw", 0x68000000, 0xfc000000, "x,j(b)", pa10},
215 { "sth", 0x64000000, 0xfc000000, "x,j(s,b)", pa10},
216 { "sth", 0x64000000, 0xfc000000, "x,j(b)", pa10},
217 { "stb", 0x60000000, 0xfc000000, "x,j(s,b)", pa10},
218 { "stb", 0x60000000, 0xfc000000, "x,j(b)", pa10},
219 { "ldwm", 0x4c000000, 0xfc000000, "j(s,b),x", pa10},
220 { "ldwm", 0x4c000000, 0xfc000000, "j(b),x", pa10},
221 { "stwm", 0x6c000000, 0xfc000000, "x,j(s,b)", pa10},
222 { "stwm", 0x6c000000, 0xfc000000, "x,j(b)", pa10},
223 { "ldwx", 0x0c000080, 0xfc001fc0, "cx(s,b),t", pa10},
224 { "ldwx", 0x0c000080, 0xfc001fc0, "cx(b),t", pa10},
225 { "ldhx", 0x0c000040, 0xfc001fc0, "cx(s,b),t", pa10},
226 { "ldhx", 0x0c000040, 0xfc001fc0, "cx(b),t", pa10},
227 { "ldbx", 0x0c000000, 0xfc001fc0, "cx(s,b),t", pa10},
228 { "ldbx", 0x0c000000, 0xfc001fc0, "cx(b),t", pa10},
229 { "ldwax", 0x0c000180, 0xfc00dfc0, "cx(b),t", pa10},
230 { "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(s,b),t", pa10},
231 { "ldcwx", 0x0c0001c0, 0xfc001fc0, "cx(b),t", pa10},
232 { "ldws", 0x0c001080, 0xfc001fc0, "C5(s,b),t", pa10},
233 { "ldws", 0x0c001080, 0xfc001fc0, "C5(b),t", pa10},
234 { "ldhs", 0x0c001040, 0xfc001fc0, "C5(s,b),t", pa10},
235 { "ldhs", 0x0c001040, 0xfc001fc0, "C5(b),t", pa10},
236 { "ldbs", 0x0c001000, 0xfc001fc0, "C5(s,b),t", pa10},
237 { "ldbs", 0x0c001000, 0xfc001fc0, "C5(b),t", pa10},
238 { "ldwas", 0x0c001180, 0xfc00dfc0, "C5(b),t", pa10},
239 { "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(s,b),t", pa10},
240 { "ldcws", 0x0c0011c0, 0xfc001fc0, "C5(b),t", pa10},
241 { "stws", 0x0c001280, 0xfc001fc0, "Cx,V(s,b)", pa10},
242 { "stws", 0x0c001280, 0xfc001fc0, "Cx,V(b)", pa10},
243 { "sths", 0x0c001240, 0xfc001fc0, "Cx,V(s,b)", pa10},
244 { "sths", 0x0c001240, 0xfc001fc0, "Cx,V(b)", pa10},
245 { "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(s,b)", pa10},
246 { "stbs", 0x0c001200, 0xfc001fc0, "Cx,V(b)", pa10},
247 { "stwas", 0x0c001380, 0xfc00dfc0, "Cx,V(b)", pa10},
248 { "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(s,b)", pa10},
249 { "stbys", 0x0c001300, 0xfc001fc0, "Yx,V(b)", pa10},
251 /* Immediate instructions. */
252 { "ldo", 0x34000000, 0xfc00c000, "j(b),x", pa10},
253 { "ldil", 0x20000000, 0xfc000000, "k,b", pa10},
254 { "addil", 0x28000000, 0xfc000000, "k,b", pa10},
256 /* Branching instructions. */
257 { "bl", 0xe8000000, 0xfc00e000, "nW,b", pa10},
258 { "gate", 0xe8002000, 0xfc00e000, "nW,b", pa10},
259 { "blr", 0xe8004000, 0xfc00e001, "nx,b", pa10},
260 { "bv", 0xe800c000, 0xfc00fffd, "nx(b)", pa10},
261 { "bv", 0xe800c000, 0xfc00fffd, "n(b)", pa10},
262 { "be", 0xe0000000, 0xfc000000, "nz(S,b)", pa10},
263 { "ble", 0xe4000000, 0xfc000000, "nz(S,b)", pa10},
264 { "movb", 0xc8000000, 0xfc000000, "|nx,b,w", pa10},
265 { "movib", 0xcc000000, 0xfc000000, "|n5,b,w", pa10},
266 { "combt", 0x80000000, 0xfc000000, "<nx,b,w", pa10},
267 { "combf", 0x88000000, 0xfc000000, "<nx,b,w", pa10},
268 { "comibt", 0x84000000, 0xfc000000, "<n5,b,w", pa10},
269 { "comibf", 0x8c000000, 0xfc000000, "<n5,b,w", pa10},
270 { "addbt", 0xa0000000, 0xfc000000, "!nx,b,w", pa10},
271 { "addbf", 0xa8000000, 0xfc000000, "!nx,b,w", pa10},
272 { "addibt", 0xa4000000, 0xfc000000, "!n5,b,w", pa10},
273 { "addibf", 0xac000000, 0xfc000000, "!n5,b,w", pa10},
274 { "bb", 0xc4004000, 0xfc004000, "~nx,Q,w", pa10},
275 { "bvb", 0xc0004000, 0xffe04000, "~nx,w", pa10},
277 /* Computation Instructions */
279 { "add", 0x08000600, 0xfc000fe0, "dx,b,t", pa10},
280 { "addl", 0x08000a00, 0xfc000fe0, "dx,b,t", pa10},
281 { "addo", 0x08000e00, 0xfc000fe0, "dx,b,t", pa10},
282 { "addc", 0x08000700, 0xfc000fe0, "dx,b,t", pa10},
283 { "addco", 0x08000f00, 0xfc000fe0, "dx,b,t", pa10},
284 { "sh1add", 0x08000640, 0xfc000fe0, "dx,b,t", pa10},
285 { "sh1addl", 0x08000a40, 0xfc000fe0, "dx,b,t", pa10},
286 { "sh1addo", 0x08000e40, 0xfc000fe0, "dx,b,t", pa10},
287 { "sh2add", 0x08000680, 0xfc000fe0, "dx,b,t", pa10},
288 { "sh2addl", 0x08000a80, 0xfc000fe0, "dx,b,t", pa10},
289 { "sh2addo", 0x08000e80, 0xfc000fe0, "dx,b,t", pa10},
290 { "sh3add", 0x080006c0, 0xfc000fe0, "dx,b,t", pa10},
291 { "sh3addl", 0x08000ac0, 0xfc000fe0, "dx,b,t", pa10},
292 { "sh3addo", 0x08000ec0, 0xfc000fe0, "dx,b,t", pa10},
293 { "sub", 0x08000400, 0xfc000fe0, "ax,b,t", pa10},
294 { "subo", 0x08000c00, 0xfc000fe0, "ax,b,t", pa10},
295 { "subb", 0x08000500, 0xfc000fe0, "ax,b,t", pa10},
296 { "subbo", 0x08000d00, 0xfc000fe0, "ax,b,t", pa10},
297 { "subt", 0x080004c0, 0xfc000fe0, "ax,b,t", pa10},
298 { "subto", 0x08000cc0, 0xfc000fe0, "ax,b,t", pa10},
299 { "ds", 0x08000440, 0xfc000fe0, "ax,b,t", pa10},
300 { "comclr", 0x08000880, 0xfc000fe0, "ax,b,t", pa10},
301 { "or", 0x08000240, 0xfc000fe0, "&x,b,t", pa10},
302 { "xor", 0x08000280, 0xfc000fe0, "&x,b,t", pa10},
303 { "and", 0x08000200, 0xfc000fe0, "&x,b,t", pa10},
304 { "andcm", 0x08000000, 0xfc000fe0, "&x,b,t", pa10},
305 { "uxor", 0x08000380, 0xfc000fe0, "Ux,b,t", pa10},
306 { "uaddcm", 0x08000980, 0xfc000fe0, "Ux,b,t", pa10},
307 { "uaddcmt", 0x080009c0, 0xfc000fe0, "Ux,b,t", pa10},
308 { "dcor", 0x08000b80, 0xfc1f0fe0, "Ub,t", pa10},
309 { "idcor", 0x08000bc0, 0xfc1f0fe0, "Ub,t", pa10},
310 { "addi", 0xb4000000, 0xfc000800, "di,b,x", pa10},
311 { "addio", 0xb4000800, 0xfc000800, "di,b,x", pa10},
312 { "addit", 0xb0000000, 0xfc000800, "di,b,x", pa10},
313 { "addito", 0xb0000800, 0xfc000800, "di,b,x", pa10},
314 { "subi", 0x94000000, 0xfc000800, "ai,b,x", pa10},
315 { "subio", 0x94000800, 0xfc000800, "ai,b,x", pa10},
316 { "comiclr", 0x90000000, 0xfc000800, "ai,b,x", pa10},
318 /* Extract and Deposit Instructions */
320 { "vshd", 0xd0000000, 0xfc001fe0, ">x,b,t", pa10},
321 { "shd", 0xd0000800, 0xfc001c00, ">x,b,p,t", pa10},
322 { "vextru", 0xd0001000, 0xfc001fe0, ">b,T,x", pa10},
323 { "vextrs", 0xd0001400, 0xfc001fe0, ">b,T,x", pa10},
324 { "extru", 0xd0001800, 0xfc001c00, ">b,P,T,x", pa10},
325 { "extrs", 0xd0001c00, 0xfc001c00, ">b,P,T,x", pa10},
326 { "zvdep", 0xd4000000, 0xfc001fe0, ">x,T,b", pa10},
327 { "vdep", 0xd4000400, 0xfc001fe0, ">x,T,b", pa10},
328 { "zdep", 0xd4000800, 0xfc001c00, ">x,p,T,b", pa10},
329 { "dep", 0xd4000c00, 0xfc001c00, ">x,p,T,b", pa10},
330 { "zvdepi", 0xd4001000, 0xfc001fe0, ">5,T,b", pa10},
331 { "vdepi", 0xd4001400, 0xfc001fe0, ">5,T,b", pa10},
332 { "zdepi", 0xd4001800, 0xfc001c00, ">5,p,T,b", pa10},
333 { "depi", 0xd4001c00, 0xfc001c00, ">5,p,T,b", pa10},
335 /* System Control Instructions */
337 { "break", 0x00000000, 0xfc001fe0, "r,A", pa10},
338 { "rfi", 0x00000c00, 0xffffffff, "", pa10},
339 { "rfir", 0x00000ca0, 0xffffffff, "", pa11},
340 { "ssm", 0x00000d60, 0xffe0ffe0, "R,t", pa10},
341 { "rsm", 0x00000e60, 0xffe0ffe0, "R,t", pa10},
342 { "mtsm", 0x00001860, 0xffe0ffff, "x", pa10},
343 { "ldsid", 0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10},
344 { "ldsid", 0x000010a0, 0xfc1f3fe0, "(b),t", pa10},
345 { "mtsp", 0x00001820, 0xffe01fff, "x,S", pa10},
346 { "mtctl", 0x00001840, 0xfc00ffff, "x,^", pa10},
347 { "mfsp", 0x000004a0, 0xffff1fe0, "S,t", pa10},
348 { "mfctl", 0x000008a0, 0xfc1fffe0, "^,t", pa10},
349 { "sync", 0x00000400, 0xffffffff, "", pa10},
350 { "syncdma", 0x00100400, 0xffffffff, "", pa10},
351 { "prober", 0x04001180, 0xfc003fe0, "(s,b),x,t", pa10},
352 { "prober", 0x04001180, 0xfc003fe0, "(b),x,t", pa10},
353 { "proberi", 0x04003180, 0xfc003fe0, "(s,b),R,t", pa10},
354 { "proberi", 0x04003180, 0xfc003fe0, "(b),R,t", pa10},
355 { "probew", 0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10},
356 { "probew", 0x040011c0, 0xfc003fe0, "(b),x,t", pa10},
357 { "probewi", 0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10},
358 { "probewi", 0x040031c0, 0xfc003fe0, "(b),R,t", pa10},
359 { "lpa", 0x04001340, 0xfc003fc0, "Zx(s,b),t", pa10},
360 { "lpa", 0x04001340, 0xfc003fc0, "Zx(b),t", pa10},
361 { "lha", 0x04001300, 0xfc003fc0, "Zx(s,b),t", pa10},
362 { "lha", 0x04001300, 0xfc003fc0, "Zx(b),t", pa10},
363 { "lci", 0x04001300, 0xfc003fe0, "x(s,b),t", pa10},
364 { "lci", 0x04001300, 0xfc003fe0, "x(b),t", pa10},
365 { "pdtlb", 0x04001200, 0xfc003fdf, "Zx(s,b)", pa10},
366 { "pdtlb", 0x04001200, 0xfc003fdf, "Zx(b)", pa10},
367 { "pitlb", 0x04000200, 0xfc001fdf, "Zx(S,b)", pa10},
368 { "pitlb", 0x04000200, 0xfc001fdf, "Zx(b)", pa10},
369 { "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(s,b)", pa10},
370 { "pdtlbe", 0x04001240, 0xfc003fdf, "Zx(b)", pa10},
371 { "pitlbe", 0x04000240, 0xfc001fdf, "Zx(S,b)", pa10},
372 { "pitlbe", 0x04000240, 0xfc001fdf, "Zx(b)", pa10},
373 { "idtlba", 0x04001040, 0xfc003fff, "x,(s,b)", pa10},
374 { "idtlba", 0x04001040, 0xfc003fff, "x,(b)", pa10},
375 { "iitlba", 0x04000040, 0xfc001fff, "x,(S,b)", pa10},
376 { "iitlba", 0x04000040, 0xfc001fff, "x,(b)", pa10},
377 { "idtlbp", 0x04001000, 0xfc003fff, "x,(s,b)", pa10},
378 { "idtlbp", 0x04001000, 0xfc003fff, "x,(b)", pa10},
379 { "iitlbp", 0x04000000, 0xfc001fff, "x,(S,b)", pa10},
380 { "iitlbp", 0x04000000, 0xfc001fff, "x,(b)", pa10},
381 { "pdc", 0x04001380, 0xfc003fdf, "Zx(s,b)", pa10},
382 { "pdc", 0x04001380, 0xfc003fdf, "Zx(b)", pa10},
383 { "fdc", 0x04001280, 0xfc003fdf, "Zx(s,b)", pa10},
384 { "fdc", 0x04001280, 0xfc003fdf, "Zx(b)", pa10},
385 { "fic", 0x04000280, 0xfc001fdf, "Zx(S,b)", pa10},
386 { "fic", 0x04000280, 0xfc001fdf, "Zx(b)", pa10},
387 { "fdce", 0x040012c0, 0xfc003fdf, "Zx(s,b)", pa10},
388 { "fdce", 0x040012c0, 0xfc003fdf, "Zx(b)", pa10},
389 { "fice", 0x040002c0, 0xfc001fdf, "Zx(S,b)", pa10},
390 { "fice", 0x040002c0, 0xfc001fdf, "Zx(b)", pa10},
391 { "diag", 0x14000000, 0xfc000000, "D", pa10},
393 /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
394 the Timex FPU or the Mustang ERS (not sure which) manual. */
395 { "gfw", 0x04001680, 0xfc003fdf, "Zx(s,b)", pa11},
396 { "gfw", 0x04001680, 0xfc003fdf, "Zx(b)", pa11},
397 { "gfr", 0x04001a80, 0xfc003fdf, "Zx(s,b)", pa11},
398 { "gfr", 0x04001a80, 0xfc003fdf, "Zx(b)", pa11},
400 /* Floating Point Coprocessor Instructions */
402 { "fldwx", 0x24000000, 0xfc001f80, "cx(s,b),v", pa10},
403 { "fldwx", 0x24000000, 0xfc001f80, "cx(b),v", pa10},
404 { "flddx", 0x2c000000, 0xfc001fc0, "cx(s,b),y", pa10},
405 { "flddx", 0x2c000000, 0xfc001fc0, "cx(b),y", pa10},
406 { "fstwx", 0x24000200, 0xfc001f80, "cv,x(s,b)", pa10},
407 { "fstwx", 0x24000200, 0xfc001f80, "cv,x(b)", pa10},
408 { "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(s,b)", pa10},
409 { "fstdx", 0x2c000200, 0xfc001fc0, "cy,x(b)", pa10},
410 { "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(s,b)", pa10},
411 { "fstqx", 0x3c000200, 0xfc001fc0, "cy,x(b)", pa10},
412 { "fldws", 0x24001000, 0xfc001f80, "C5(s,b),v", pa10},
413 { "fldws", 0x24001000, 0xfc001f80, "C5(b),v", pa10},
414 { "fldds", 0x2c001000, 0xfc001fc0, "C5(s,b),y", pa10},
415 { "fldds", 0x2c001000, 0xfc001fc0, "C5(b),y", pa10},
416 { "fstws", 0x24001200, 0xfc001f80, "Cv,5(s,b)", pa10},
417 { "fstws", 0x24001200, 0xfc001f80, "Cv,5(b)", pa10},
418 { "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(s,b)", pa10},
419 { "fstds", 0x2c001200, 0xfc001fc0, "Cy,5(b)", pa10},
420 { "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(s,b)", pa10},
421 { "fstqs", 0x3c001200, 0xfc001fc0, "Cy,5(b)", pa10},
422 { "fadd", 0x30000600, 0xfc00e7e0, "FE,X,v", pa10},
423 { "fadd", 0x38000600, 0xfc00e720, "IJ,K,v", pa10},
424 { "fsub", 0x30002600, 0xfc00e7e0, "FE,X,v", pa10},
425 { "fsub", 0x38002600, 0xfc00e720, "IJ,K,v", pa10},
426 { "fmpy", 0x30004600, 0xfc00e7e0, "FE,X,v", pa10},
427 { "fmpy", 0x38004600, 0xfc00e720, "IJ,K,v", pa10},
428 { "fdiv", 0x30006600, 0xfc00e7e0, "FE,X,v", pa10},
429 { "fdiv", 0x38006600, 0xfc00e720, "IJ,K,v", pa10},
430 { "fsqrt", 0x30008000, 0xfc1fe7e0, "FE,v", pa10},
431 { "fsqrt", 0x38008000, 0xfc1fe720, "FJ,v", pa10},
432 { "fabs", 0x30006000, 0xfc1fe7e0, "FE,v", pa10},
433 { "fabs", 0x38006000, 0xfc1fe720, "FJ,v", pa10},
434 { "frem", 0x30008600, 0xfc00e7e0, "FE,X,v", pa10},
435 { "frem", 0x38008600, 0xfc00e720, "FJ,K,v", pa10},
436 { "frnd", 0x3000a000, 0xfc1fe7e0, "FE,v", pa10},
437 { "frnd", 0x3800a000, 0xfc1fe720, "FJ,v", pa10},
438 { "fcpy", 0x30004000, 0xfc1fe7e0, "FE,v", pa10},
439 { "fcpy", 0x38004000, 0xfc1fe720, "FJ,v", pa10},
440 { "fcnvff", 0x30000200, 0xfc1f87e0, "FGE,v", pa10},
441 { "fcnvff", 0x38000200, 0xfc1f8720, "FGJ,v", pa10},
442 { "fcnvxf", 0x30008200, 0xfc1f87e0, "FGE,v", pa10},
443 { "fcnvxf", 0x38008200, 0xfc1f8720, "FGJ,v", pa10},
444 { "fcnvfx", 0x30010200, 0xfc1f87e0, "FGE,v", pa10},
445 { "fcnvfx", 0x38010200, 0xfc1f8720, "FGJ,v", pa10},
446 { "fcnvfxt", 0x30018200, 0xfc1f87e0, "FGE,v", pa10},
447 { "fcnvfxt", 0x38018200, 0xfc1f8720, "FGJ,v", pa10},
448 { "fmpyfadd", 0xb8000000, 0xfc000020, "FE,X,3,v", pa20},
449 { "fmpynfadd", 0xb8000020, 0xfc000020, "FE,X,3,v", pa20},
450 { "fneg", 0x3000c000, 0xfc1fe7e0, "FE,v", pa20},
451 { "fneg", 0x3800c000, 0xfc1fe720, "FJ,v", pa20},
452 { "fnegabs", 0x3000e000, 0xfc1fe7e0, "FE,v", pa20},
453 { "fnegabs", 0x3800e000, 0xfc1fe720, "FJ,v", pa20},
454 { "fcmp", 0x30000400, 0xfc00e7e0, "FME,X", pa10},
455 { "fcmp", 0x38000400, 0xfc00e720, "IMJ,K", pa10},
456 { "xmpyu", 0x38004700, 0xfc00e720, "E,X,v", pa11},
457 { "fmpyadd", 0x18000000, 0xfc000000, "H4,6,7,9,8", pa11},
458 { "fmpysub", 0x98000000, 0xfc000000, "H4,6,7,9,8", pa11},
459 { "ftest", 0x30002420, 0xffffffff, "", pa10},
460 { "fid", 0x30000000, 0xffffffff, "", pa11},
463 /* Assist Instructions */
465 { "spop0", 0x10000000, 0xfc000600, "f,ON", pa10},
466 { "spop1", 0x10000200, 0xfc000600, "f,oNt", pa10},
467 { "spop2", 0x10000400, 0xfc000600, "f,1Nb", pa10},
468 { "spop3", 0x10000600, 0xfc000600, "f,0Nx,b", pa10},
469 { "copr", 0x30000000, 0xfc000000, "u,2N", pa10},
470 { "cldwx", 0x24000000, 0xfc001e00, "ucx(s,b),t", pa10},
471 { "cldwx", 0x24000000, 0xfc001e00, "ucx(b),t", pa10},
472 { "clddx", 0x2c000000, 0xfc001e00, "ucx(s,b),t", pa10},
473 { "clddx", 0x2c000000, 0xfc001e00, "ucx(b),t", pa10},
474 { "cstwx", 0x24000200, 0xfc001e00, "uct,x(s,b)", pa10},
475 { "cstwx", 0x24000200, 0xfc001e00, "uct,x(b)", pa10},
476 { "cstdx", 0x2c000200, 0xfc001e00, "uct,x(s,b)", pa10},
477 { "cstdx", 0x2c000200, 0xfc001e00, "uct,x(b)", pa10},
478 { "cldws", 0x24001000, 0xfc001e00, "uC5(s,b),t", pa10},
479 { "cldws", 0x24001000, 0xfc001e00, "uC5(b),t", pa10},
480 { "cldds", 0x2c001000, 0xfc001e00, "uC5(s,b),t", pa10},
481 { "cldds", 0x2c001000, 0xfc001e00, "uC5(b),t", pa10},
482 { "cstws", 0x24001200, 0xfc001e00, "uCt,5(s,b)", pa10},
483 { "cstws", 0x24001200, 0xfc001e00, "uCt,5(b)", pa10},
484 { "cstds", 0x2c001200, 0xfc001e00, "uCt,5(s,b)", pa10},
485 { "cstds", 0x2c001200, 0xfc001e00, "uCt,5(b)", pa10},
488 #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
490 /* SKV 12/18/92. Added some denotations for various operands. */
492 #define PA_IMM11_AT_31 'i'
493 #define PA_IMM14_AT_31 'j'
494 #define PA_IMM21_AT_31 'k'
495 #define PA_DISP12 'w'
496 #define PA_DISP17 'W'
498 #define N_HPPA_OPERAND_FORMATS 5