include/opcode/hppa.h

   1 /* Table of opcodes for the PA-RISC.
   2    Copyright (C) 1990, 1991, 1993 Free Software Foundation, Inc.
   3
   4    Contributed by the Center for Software Science at the
   5    University of Utah (pa-gdb-bugs@cs.utah.edu).
   6
   7 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
   8
   9 GAS/GDB is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 1, or (at your option)
  12 any later version.
  13
  14 GAS/GDB is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with GAS or GDB; see the file COPYING.  If not, write to
  21 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  22
  23 #if !defined(__STDC__) && !defined(const)
  24 #define const
  25 #endif
  26
  27 /*
  28  * Structure of an opcode table entry.
  29  */
  30
  31 /* There are two kinds of delay slot nullification: normal which is
  32  * controled by the nullification bit, and conditional, which depends
  33  * on the direction of the branch and its success or failure.
  34  *
  35  * NONE is unfortunately #defined in the hiux system include files.
  36  * #undef it away.
  37  */
  38 #undef NONE
  39 enum delay_type {NONE, NORMAL, CONDITIONAL};
  40 struct pa_opcode
  41 {
  42     const char *name;
  43     unsigned long int match;    /* Bits that must be set...  */
  44     unsigned long int mask;     /* ... in these bits. */
  45     char *args;
  46     /* Nonzero if this is a delayed branch instruction.  */
  47     /* What uses this field?  Nothing in opcodes or gas that I saw.
  48        If nothing needs it, we could reduce this table by 20% (for
  49        most machines).  KR */
  50     char delayed;
  51 };
  52
  53 /*
  54    All hppa opcodes are 32 bits.
  55
  56    The match component is a mask saying which bits must match a
  57    particular opcode in order for an instruction to be an instance
  58    of that opcode.
  59
  60    The args component is a string containing one character
  61    for each operand of the instruction.
  62
  63    Bit positions in this description follow HP usage of lsb = 31,
  64    "at" is lsb of field.
  65
  66    In the args field, the following characters must match exactly:
  67
  68         '+,() '
  69
  70    In the args field, the following characters are unused:
  71
  72         '  "#$%    *+- ./   3      :; =  @'
  73         ' B         L              [\] _'
  74         '    e gh   lm   qr        { } '
  75
  76    Here are all the characters:
  77
  78         ' !"#$%&'()*+-,./0123456789:;<=>?@'
  79         'ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
  80         'abcdefghijklmnopqrstuvwxyz{|}~'
  81
  82 Kinds of operands:
  83    x    integer register field at 15.
  84    b    integer register field at 10.
  85    t    integer register field at 31.
  86    y    floating point register field at 31
  87    5    5 bit immediate at 15.
  88    s    2 bit space specifier at 17.
  89    S    3 bit space specifier at 18.
  90    c    indexed load completer.
  91    C    short load and store completer.
  92    Y    Store Bytes Short completer
  93    <    non-negated compare/subtract conditions.
  94    a    compare/subtract conditions
  95    d    non-negated add conditions
  96    &    logical instruction conditions
  97    U    unit instruction conditions
  98    >    shift/extract/deposit conditions.
  99    ~    bvb,bb conditions
 100    V    5 bit immediate value at 31
 101    i    11 bit immediate value at 31
 102    j    14 bit immediate value at 31
 103    k    21 bit immediate value at 31
 104    n    nullification for branch instructions
 105    N    nullification for spop and copr instructions
 106    w    12 bit branch displacement
 107    W    17 bit branch displacement (PC relative)
 108    z    17 bit branch displacement (just a number, not an address)
 109
 110 Also these:
 111
 112    p    5 bit shift count at 26 (to support the SHD instruction) encoded as
 113         31-p
 114    P    5 bit bit position at 26
 115    T    5 bit field length at 31 (encoded as 32-T)
 116    A    13 bit immediate at 18 (to support the BREAK instruction)
 117    ^    like b, but describes a control register
 118    Z    System Control Completer (to support LPA, LHA, etc.)
 119    D    26 bit immediate at 31 (to support the DIAG instruction)
 120
 121    f    3 bit Special Function Unit identifier at 25
 122    O    20 bit Special Function Unit operation split between 15 bits at 20
 123         and 5 bits at 31
 124    o    15 bit Special Function Unit operation at 20
 125    2    22 bit Special Function Unit operation split between 17 bits at 20
 126         and 5 bits at 31
 127    1    15 bit Special Function Unit operation split between 10 bits at 20
 128         and 5 bits at 31
 129    0    10 bit Special Function Unit operation split between 5 bits at 20
 130         and 5 bits at 31
 131    u    3 bit coprocessor unit identifier at 25
 132    F    Source Floating Point Operand Format Completer encoded 2 bits at 20
 133    I    Source Floating Point Operand Format Completer encoded 1 bits at 20
 134         (for 0xe format FP instructions)
 135    G    Destination Floating Point Operand Format Completer encoded 2 bits at 18
 136    M    Floating-Point Compare Conditions (encoded as 5 bits at 31)
 137    ?    negated compare/subtract conditions.
 138    !    non-negated add conditions.
 139
 140    s    2 bit space specifier at 17.
 141    b    register field at 10.
 142    r    5 bit immediate value at 31 (for the break instruction)
 143         (very similar to V above, except the value is unsigned instead of
 144         low_sign_ext)
 145    R    5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
 146         (same as r above, except the value is in a different location)
 147    Q    5 bit immediate value at 10 (a bit position specified in
 148         the bb instruction. It's the same as r above, except the
 149         value is in a different location)
 150    |    shift/extract/deposit conditions when used in a conditional branch
 151
 152 And these (PJH) for PA-89 F.P. registers and instructions:
 153
 154    v    a 't' operand type extended to handle L/R register halves.
 155    E    a 'b' operand type extended to handle L/R register halves.
 156    X    an 'x' operand type extended to handle L/R register halves.
 157    J    a 'b' operand type further extended to handle extra 1.1 registers
 158    K    a 'x' operand type further extended to handle extra 1.1 registers
 159    4    a variation of the 'b' operand type for 'fmpyadd' and 'fmpysub'
 160    6    a variation of the 'x' operand type for 'fmpyadd' and 'fmpysub'
 161    7    a variation of the 't' operand type for 'fmpyadd' and 'fmpysub'
 162    8    5 bit register field at 20 (used in 'fmpyadd' and 'fmpysub')
 163    9    5 bit register field at 25 (used in 'fmpyadd' and 'fmpysub')
 164    H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
 165         (very similar to 'F')
 166 */
 167
 168 /* The order of the opcodes in this table is significant:
 169
 170    * The assembler requires that all instances of the same mnemonic must be
 171    consecutive.  If they aren't, the assembler will bomb at runtime.
 172
 173    * The disassembler should not care about the order of the opcodes.  */
 174
 175 static const struct pa_opcode pa_opcodes[] =
 176 {
 177
 178 /* pseudo-instructions */
 179
 180 { "b",          0xe8000000, 0xffe0e000, "nW", NORMAL}, /* bl foo,r0 */
 181 { "ldi",        0x34000000, 0xffe0c000, "j,x"}, /* ldo val(r0),r */
 182 { "comib",      0x84000000, 0xfc000000, "?n5,b,w", CONDITIONAL}, /* comib{tf}*/
 183 { "comb",       0x80000000, 0xfc000000, "?nx,b,w", CONDITIONAL}, /* comb{tf} */
 184 { "addb",       0xa0000000, 0xfc000000, "!nx,b,w", CONDITIONAL}, /* addb{tf} */
 185 { "addib",      0xa4000000, 0xfc000000, "!n5,b,w", CONDITIONAL}, /* addib{tf}*/
 186 { "nop",        0x08000240, 0xffffffff, ""},      /* or 0,0,0 */
 187 { "copy",       0x08000240, 0xffe0ffe0, "x,t"},   /* or r,0,t */
 188 { "mtsar",      0x01601840, 0xffe0ffff, "x"}, /* mtctl r,cr11 */
 189
 190 /* Loads and Stores for integer registers.  */
 191 { "ldw",        0x48000000, 0xfc000000, "j(s,b),x"},
 192 { "ldw",        0x48000000, 0xfc000000, "j(b),x"},
 193 { "ldh",        0x44000000, 0xfc000000, "j(s,b),x"},
 194 { "ldh",        0x44000000, 0xfc000000, "j(b),x"},
 195 { "ldb",        0x40000000, 0xfc000000, "j(s,b),x"},
 196 { "ldb",        0x40000000, 0xfc000000, "j(b),x"},
 197 { "stw",        0x68000000, 0xfc000000, "x,j(s,b)"},
 198 { "stw",        0x68000000, 0xfc000000, "x,j(b)"},
 199 { "sth",        0x64000000, 0xfc000000, "x,j(s,b)"},
 200 { "sth",        0x64000000, 0xfc000000, "x,j(b)"},
 201 { "stb",        0x60000000, 0xfc000000, "x,j(s,b)"},
 202 { "stb",        0x60000000, 0xfc000000, "x,j(b)"},
 203 { "ldwm",       0x4c000000, 0xfc000000, "j(s,b),x"},
 204 { "ldwm",       0x4c000000, 0xfc000000, "j(b),x"},
 205 { "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)"},
 206 { "stwm",       0x6c000000, 0xfc000000, "x,j(b)"},
 207 { "ldwx",       0x0c000080, 0xfc001fc0, "cx(s,b),t"},
 208 { "ldwx",       0x0c000080, 0xfc001fc0, "cx(b),t"},
 209 { "ldhx",       0x0c000040, 0xfc001fc0, "cx(s,b),t"},
 210 { "ldhx",       0x0c000040, 0xfc001fc0, "cx(b),t"},
 211 { "ldbx",       0x0c000000, 0xfc001fc0, "cx(s,b),t"},
 212 { "ldbx",       0x0c000000, 0xfc001fc0, "cx(b),t"},
 213 { "ldwax",      0x0c000180, 0xfc00dfc0, "cx(b),t"},
 214 { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cx(s,b),t"},
 215 { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cx(b),t"},
 216 { "ldws",       0x0c001080, 0xfc001fc0, "C5(s,b),t"},
 217 { "ldws",       0x0c001080, 0xfc001fc0, "C5(b),t"},
 218 { "ldhs",       0x0c001040, 0xfc001fc0, "C5(s,b),t"},
 219 { "ldhs",       0x0c001040, 0xfc001fc0, "C5(b),t"},
 220 { "ldbs",       0x0c001000, 0xfc001fc0, "C5(s,b),t"},
 221 { "ldbs",       0x0c001000, 0xfc001fc0, "C5(b),t"},
 222 { "ldwas",      0x0c001180, 0xfc00dfc0, "C5(b),t"},
 223 { "ldcws",      0x0c0011c0, 0xfc001fc0, "C5(s,b),t"},
 224 { "ldcws",      0x0c0011c0, 0xfc001fc0, "C5(b),t"},
 225 { "stws",       0x0c001280, 0xfc001fc0, "Cx,V(s,b)"},
 226 { "stws",       0x0c001280, 0xfc001fc0, "Cx,V(b)"},
 227 { "sths",       0x0c001240, 0xfc001fc0, "Cx,V(s,b)"},
 228 { "sths",       0x0c001240, 0xfc001fc0, "Cx,V(b)"},
 229 { "stbs",       0x0c001200, 0xfc001fc0, "Cx,V(s,b)"},
 230 { "stbs",       0x0c001200, 0xfc001fc0, "Cx,V(b)"},
 231 { "stwas",      0x0c001380, 0xfc00dfc0, "Cx,V(b)"},
 232 { "stbys",      0x0c001300, 0xfc001fc0, "Yx,V(s,b)"},
 233 { "stbys",      0x0c001300, 0xfc001fc0, "Yx,V(b)"},
 234
 235 /* Immediate instructions.  */
 236 { "ldo",        0x34000000, 0xfc00c000, "j(b),x"},
 237 { "ldil",       0x20000000, 0xfc000000, "k,b"},
 238 { "addil",      0x28000000, 0xfc000000, "k,b"},
 239
 240 /* Branching instructions. */
 241 { "bl",         0xe8000000, 0xfc00e000, "nW,b", NORMAL},
 242 { "gate",       0xe8002000, 0xfc00e000, "nW,b", NORMAL},
 243 { "blr",        0xe8004000, 0xfc00e001, "nx,b", NORMAL},
 244 { "bv",         0xe800c000, 0xfc00e001, "nx(b)", NORMAL},
 245 { "bv",         0xe800c000, 0xfc00e001, "n(b)", NORMAL},
 246 { "be",         0xe0000000, 0xfc000000, "nz(S,b)", NORMAL},
 247 { "ble",        0xe4000000, 0xfc000000, "nz(S,b)", NORMAL},
 248 { "movb",       0xc8000000, 0xfc000000, "|nx,b,w", CONDITIONAL},
 249 { "movib",      0xcc000000, 0xfc000000, "|n5,b,w", CONDITIONAL},
 250 { "combt",      0x80000000, 0xfc000000, "<nx,b,w", CONDITIONAL},
 251 { "combf",      0x88000000, 0xfc000000, "<nx,b,w", CONDITIONAL},
 252 { "comibt",     0x84000000, 0xfc000000, "<n5,b,w", CONDITIONAL},
 253 { "comibf",     0x8c000000, 0xfc000000, "<n5,b,w", CONDITIONAL},
 254 { "addbt",      0xa0000000, 0xfc000000, "!nx,b,w", CONDITIONAL},
 255 { "addbf",      0xa8000000, 0xfc000000, "!nx,b,w", CONDITIONAL},
 256 { "addibt",     0xa4000000, 0xfc000000, "!n5,b,w", CONDITIONAL},
 257 { "addibf",     0xac000000, 0xfc000000, "!n5,b,w", CONDITIONAL},
 258 { "bvb",        0xc0000000, 0xffe00000, "~nx,w", CONDITIONAL},
 259 { "bb",         0xc4000000, 0xfc000000, "~nx,Q,w", CONDITIONAL},
 260
 261 /* Computation Instructions */
 262
 263 { "add",        0x08000600, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 264 { "addl",       0x08000a00, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 265 { "addo",       0x08000e00, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 266 { "addc",       0x08000700, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 267 { "addco",      0x08000f00, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 268 { "sh1add",     0x08000640, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 269 { "sh1addl",    0x08000a40, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 270 { "sh1addo",    0x08000e40, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 271 { "sh2add",     0x08000680, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 272 { "sh2addl",    0x08000a80, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 273 { "sh2addo",    0x08000e80, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 274 { "sh3add",     0x080006c0, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 275 { "sh3addl",    0x08000ac0, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 276 { "sh3addo",    0x08000ec0, 0xfc000fe0, "dx,b,t", CONDITIONAL},
 277 { "sub",        0x08000400, 0xfc000fe0, "ax,b,t", CONDITIONAL},
 278 { "subo",       0x08000c00, 0xfc000fe0, "ax,b,t", CONDITIONAL},
 279 { "subb",       0x08000500, 0xfc000fe0, "ax,b,t", CONDITIONAL},
 280 { "subbo",      0x08000d00, 0xfc000fe0, "ax,b,t", CONDITIONAL},
 281 { "subt",       0x080004c0, 0xfc000fe0, "ax,b,t", CONDITIONAL},
 282 { "subto",      0x08000cc0, 0xfc000fe0, "ax,b,t", CONDITIONAL},
 283 { "ds",         0x08000440, 0xfc000fe0, "ax,b,t", CONDITIONAL},
 284 { "comclr",     0x08000880, 0xfc000fe0, "ax,b,t", CONDITIONAL},
 285 { "or",         0x08000240, 0xfc000fe0, "&x,b,t", CONDITIONAL},
 286 { "xor",        0x08000280, 0xfc000fe0, "&x,b,t", CONDITIONAL},
 287 { "and",        0x08000200, 0xfc000fe0, "&x,b,t", CONDITIONAL},
 288 { "andcm",      0x08000000, 0xfc000fe0, "&x,b,t", CONDITIONAL},
 289 { "uxor",       0x08000380, 0xfc000fe0, "Ux,b,t", CONDITIONAL},
 290 { "uaddcm",     0x08000980, 0xfc000fe0, "Ux,b,t", CONDITIONAL},
 291 { "uaddcmt",    0x080009c0, 0xfc000fe0, "Ux,b,t", CONDITIONAL},
 292 { "dcor",       0x08000b80, 0xfc1f0fe0, "Ub,t",   CONDITIONAL},
 293 { "idcor",      0x08000bc0, 0xfc1f0fe0, "Ub,t",   CONDITIONAL},
 294 { "addi",       0xb4000000, 0xfc000800, "di,b,x", CONDITIONAL},
 295 { "addio",      0xb4000800, 0xfc000800, "di,b,x", CONDITIONAL},
 296 { "addit",      0xb0000000, 0xfc000800, "di,b,x", CONDITIONAL},
 297 { "addito",     0xb0000800, 0xfc000800, "di,b,x", CONDITIONAL},
 298 { "subi",       0x94000000, 0xfc000800, "ai,b,x", CONDITIONAL},
 299 { "subio",      0x94000800, 0xfc000800, "ai,b,x", CONDITIONAL},
 300 { "comiclr",    0x90000000, 0xfc000800, "ai,b,x", CONDITIONAL},
 301
 302 /* Extract and Deposit Instructions */
 303
 304 { "vshd",       0xd0000000, 0xfc001fe0, ">x,b,t", CONDITIONAL},
 305 { "shd",        0xd0000800, 0xfc001c00, ">x,b,p,t", CONDITIONAL},
 306 { "vextru",     0xd0001000, 0xfc001fe0, ">b,T,x", CONDITIONAL},
 307 { "vextrs",     0xd0001400, 0xfc001fe0, ">b,T,x", CONDITIONAL},
 308 { "extru",      0xd0001800, 0xfc001c00, ">b,P,T,x", CONDITIONAL},
 309 { "extrs",      0xd0001c00, 0xfc001c00, ">b,P,T,x", CONDITIONAL},
 310 { "zvdep",      0xd4000000, 0xfc001fe0, ">x,T,b", CONDITIONAL},
 311 { "vdep",       0xd4000400, 0xfc001fe0, ">x,T,b", CONDITIONAL},
 312 { "zdep",       0xd4000800, 0xfc001c00, ">x,p,T,b", CONDITIONAL},
 313 { "dep",        0xd4000c00, 0xfc001c00, ">x,p,T,b", CONDITIONAL},
 314 { "zvdepi",     0xd4001000, 0xfc001fe0, ">5,T,b", CONDITIONAL},
 315 { "vdepi",      0xd4001400, 0xfc001fe0, ">5,T,b", CONDITIONAL},
 316 { "zdepi",      0xd4001800, 0xfc001c00, ">5,p,T,b", CONDITIONAL},
 317 { "depi",       0xd4001c00, 0xfc001c00, ">5,p,T,b", CONDITIONAL},
 318
 319 /* System Control Instructions */
 320
 321 { "break",      0x00000000, 0xfc001fe0, "r,A"},
 322 { "rfi",        0x00000c00, 0xffffffff, ""},
 323 { "rfir",       0x00000ca0, 0xffffffff, ""},
 324 { "ssm",        0x00000d60, 0xffe0ffe0, "R,t"},
 325 { "rsm",        0x00000e60, 0xffe0ffe0, "R,t"},
 326 { "mtsm",       0x00001860, 0xffe0ffff, "x"},
 327 { "ldsid",      0x000010a0, 0xfc1f3fe0, "(s,b),t"},
 328 { "ldsid",      0x000010a0, 0xfc1f3fe0, "(b),t"},
 329 { "mtsp",       0x00001820, 0xffe01fff, "x,S"},
 330 { "mtctl",      0x00001840, 0xfc00ffff, "x,^"},
 331 { "mfsp",       0x000004a0, 0xffff1fe0, "S,t"},
 332 { "mfctl",      0x000008a0, 0xfc1fffe0, "^,t"},
 333 { "sync",       0x00000400, 0xffffffff, ""},
 334 { "prober",     0x04001180, 0xfc003fe0, "(s,b),x,t"},
 335 { "prober",     0x04001180, 0xfc003fe0, "(b),x,t"},
 336 { "proberi",    0x04003180, 0xfc003fe0, "(s,b),R,t"},
 337 { "proberi",    0x04003180, 0xfc003fe0, "(b),R,t"},
 338 { "probew",     0x040011c0, 0xfc003fe0, "(s,b),x,t"},
 339 { "probew",     0x040011c0, 0xfc003fe0, "(b),x,t"},
 340 { "probewi",    0x040031c0, 0xfc003fe0, "(s,b),R,t"},
 341 { "probewi",    0x040031c0, 0xfc003fe0, "(b),R,t"},
 342 { "lpa",        0x04001340, 0xfc003fc0, "Zx(s,b),t"},
 343 { "lpa",        0x04001340, 0xfc003fc0, "Zx(b),t"},
 344 { "lha",        0x04001300, 0xfc003fc0, "Zx(s,b),t"},
 345 { "lha",        0x04001300, 0xfc003fc0, "Zx(b),t"},
 346 { "pdtlb",      0x04001200, 0xfc003fdf, "Zx(s,b)"},
 347 { "pdtlb",      0x04001200, 0xfc003fdf, "Zx(b)"},
 348 { "pitlb",      0x04000200, 0xfc003fdf, "Zx(s,b)"},
 349 { "pitlb",      0x04000200, 0xfc003fdf, "Zx(b)"},
 350 { "pdtlbe",     0x04001240, 0xfc003fdf, "Zx(s,b)"},
 351 { "pdtlbe",     0x04001240, 0xfc003fdf, "Zx(b)"},
 352 { "pitlbe",     0x04000240, 0xfc003fdf, "Zx(s,b)"},
 353 { "pitlbe",     0x04000240, 0xfc003fdf, "Zx(b)"},
 354 { "idtlba",     0x04001040, 0xfc003fff, "x,(s,b)"},
 355 { "idtlba",     0x04001040, 0xfc003fff, "x,(b)"},
 356 { "iitlba",     0x04000040, 0xfc003fff, "x,(s,b)"},
 357 { "iitlba",     0x04000040, 0xfc003fff, "x,(b)"},
 358 { "idtlbp",     0x04001000, 0xfc003fff, "x,(s,b)"},
 359 { "idtlbp",     0x04001000, 0xfc003fff, "x,(b)"},
 360 { "iitlbp",     0x04000000, 0xfc003fff, "x,(s,b)"},
 361 { "iitlbp",     0x04000000, 0xfc003fff, "x,(b)"},
 362 { "pdc",        0x04001380, 0xfc003fdf, "Zx(s,b)"},
 363 { "pdc",        0x04001380, 0xfc003fdf, "Zx(b)"},
 364 { "fdc",        0x04001280, 0xfc003fdf, "Zx(s,b)"},
 365 { "fdc",        0x04001280, 0xfc003fdf, "Zx(b)"},
 366 { "fic",        0x04000280, 0xfc003fdf, "Zx(s,b)"},
 367 { "fic",        0x04000280, 0xfc003fdf, "Zx(b)"},
 368 { "fdce",       0x040012c0, 0xfc003fdf, "Zx(s,b)"},
 369 { "fdce",       0x040012c0, 0xfc003fdf, "Zx(b)"},
 370 { "fice",       0x040002c0, 0xfc003fdf, "Zx(s,b)"},
 371 { "fice",       0x040002c0, 0xfc003fdf, "Zx(b)"},
 372 { "diag",       0x14000000, 0xfc000000, "D"},
 373
 374 /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
 375    the Timex FPU or the Mustang ERS (not sure which) manual.  */
 376 { "gfw",        0x04001680, 0xfc003fdf, "Zx(s,b)"},
 377 { "gfw",        0x04001680, 0xfc003fdf, "Zx(b)"},
 378 { "gfr",        0x04001a80, 0xfc003fdf, "Zx(s,b)"},
 379 { "gfr",        0x04001a80, 0xfc003fdf, "Zx(b)"},
 380
 381 /* Floating Point Coprocessor Instructions */
 382
 383 { "fldwx",      0x24000000, 0xfc001f80, "cx(s,b),v"},
 384 { "fldwx",      0x24000000, 0xfc001f80, "cx(b),v"},
 385 { "flddx",      0x2c000000, 0xfc001fc0, "cx(s,b),y"},
 386 { "flddx",      0x2c000000, 0xfc001fc0, "cx(b),y"},
 387 { "fstwx",      0x24000200, 0xfc001fc0, "cv,x(s,b)"},
 388 { "fstwx",      0x24000200, 0xfc001fc0, "cv,x(b)"},
 389 { "fstdx",      0x2c000200, 0xfc001fc0, "cy,x(s,b)"},
 390 { "fstdx",      0x2c000200, 0xfc001fc0, "cy,x(b)"},
 391 { "fstqx",      0x3c000200, 0xfc001fc0, "cy,x(s,b)"},
 392 { "fstqx",      0x3c000200, 0xfc001fc0, "cy,x(b)"},
 393 { "fldws",      0x24001000, 0xfc001f80, "C5(s,b),v"},
 394 { "fldws",      0x24001000, 0xfc001f80, "C5(b),v"},
 395 { "fldds",      0x2c001000, 0xfc001fc0, "C5(s,b),y"},
 396 { "fldds",      0x2c001000, 0xfc001fc0, "C5(b),y"},
 397 { "fstws",      0x24001200, 0xfc001f80, "Cv,5(s,b)"},
 398 { "fstws",      0x24001200, 0xfc001f80, "Cy,5(b)"},
 399 { "fstds",      0x2c001200, 0xfc001fc0, "Cy,5(s,b)"},
 400 { "fstds",      0x2c001200, 0xfc001fc0, "Cy,5(b)"},
 401 { "fstqs",      0x3c001200, 0xfc001fc0, "Cy,5(s,b)"},
 402 { "fstqs",      0x3c001200, 0xfc001fc0, "Cy,5(b)"},
 403 { "fadd",       0x30000600, 0xfc00e7e0, "FE,X,v"},
 404 { "fadd",       0x38000600, 0xfc00e720, "IJ,K,v"},
 405 { "fsub",       0x30002600, 0xfc00e7e0, "FE,X,v"},
 406 { "fsub",       0x38002600, 0xfc00e720, "IJ,K,v"},
 407 { "fmpy",       0x30004600, 0xfc00e7e0, "FE,X,v"},
 408 { "fmpy",       0x38004600, 0xfc00e720, "IJ,K,v"},
 409 { "fdiv",       0x30006600, 0xfc00e7e0, "FE,X,v"},
 410 { "fdiv",       0x38006600, 0xfc00e720, "IJ,K,v"},
 411 { "fsqrt",      0x30008000, 0xfc1fe7e0, "FE,v"},
 412 { "fsqrt",      0x38008000, 0xfc1fe720, "FJ,v"},
 413 { "fabs",       0x30006000, 0xfc1fe7e0, "FE,v"},
 414 { "fabs",       0x38006000, 0xfc1fe720, "FJ,v"},
 415 { "frem",       0x30008600, 0xfc00e7e0, "FE,X,v"},
 416 { "frem",       0x38008600, 0xfc00e720, "FJ,K,v"},
 417 { "frnd",       0x3000a000, 0xfc1fe7e0, "FE,v"},
 418 { "frnd",       0x3800a000, 0xfc1fe720, "FJ,v"},
 419 { "fcpy",       0x30004000, 0xfc1fe7e0, "FE,v"},
 420 { "fcpy",       0x38004000, 0xfc1fe720, "FJ,v"},
 421 { "fcnvff",     0x30000200, 0xfc1f87e0, "FGE,v"},
 422 { "fcnvff",     0x38000200, 0xfc1f8720, "FGJ,v"},
 423 { "fcnvxf",     0x30008200, 0xfc1f87e0, "FGE,v"},
 424 { "fcnvxf",     0x38008200, 0xfc1f8720, "FGJ,v"},
 425 { "fcnvfx",     0x30010200, 0xfc1f87e0, "FGE,v"},
 426 { "fcnvfx",     0x38010200, 0xfc1f8720, "FGJ,v"},
 427 { "fcnvfxt",    0x30018200, 0xfc1f87e0, "FGE,v"},
 428 { "fcnvfxt",    0x38018200, 0xfc1f8720, "FGJ,v"},
 429 { "fcmp",       0x30000400, 0xfc00e7e0, "FME,X"},
 430 { "fcmp",       0x38000400, 0xfc00e720, "IMJ,K"},
 431 { "xmpyu",      0x38004700, 0xfc00e720, "FE,X,v"},
 432 { "fmpyadd",    0x18000000, 0xfc000000, "H4,6,7,9,8"},
 433 { "fmpysub",    0x98000000, 0xfc000000, "H4,6,7,9,8"},
 434 { "ftest",      0x30002420, 0xffffffff, ""},
 435
 436
 437 /* Assist Instructions */
 438
 439 { "spop0",      0x10000000, 0xfc000600, ",f,ON", NORMAL},
 440 { "spop1",      0x10000200, 0xfc000600, ",f,oNt", NORMAL},
 441 { "spop2",      0x10000400, 0xfc000600, ",f,1Nb", NORMAL},
 442 { "spop3",      0x10000600, 0xfc000600, ",f,0Nx,b", NORMAL},
 443 { "copr",       0x30000000, 0xfc000000, ",u,2N", NORMAL},
 444 { "cldwx",      0x24000000, 0xfc001e00, ",ucx(s,b),t"},
 445 { "cldwx",      0x24000000, 0xfc001e00, ",ucx(b),t"},
 446 { "clddx",      0x2c000000, 0xfc001e00, ",ucx(s,b),t"},
 447 { "clddx",      0x2c000000, 0xfc001e00, ",ucx(b),t"},
 448 { "cstwx",      0x24000200, 0xfc001e00, ",uct,x(s,b)"},
 449 { "cstwx",      0x24000200, 0xfc001e00, ",uct,x(b)"},
 450 { "cstdx",      0x2c000200, 0xfc001e00, ",uct,x(s,b)"},
 451 { "cstdx",      0x2c000200, 0xfc001e00, ",uct,x(b)"},
 452 { "cldws",      0x24001000, 0xfc001e00, ",uC5(s,b),t"},
 453 { "cldws",      0x24001000, 0xfc001e00, ",uC5(b),t"},
 454 { "cldds",      0x2c001000, 0xfc001e00, ",uC5(s,b),t"},
 455 { "cldds",      0x2c001000, 0xfc001e00, ",uC5(b),t"},
 456 { "cstws",      0x24001200, 0xfc001e00, ",uCt,5(s,b)"},
 457 { "cstws",      0x24001200, 0xfc001e00, ",uCt,5(b)"},
 458 { "cstds",      0x2c001200, 0xfc001e00, ",uCt,5(s,b)"},
 459 { "cstds",      0x2c001200, 0xfc001e00, ",uCt,5(b)"},
 460 };
 461
 462 #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
 463
 464 /* SKV 12/18/92. Added some denotations for various operands. */
 465
 466 #define PA_IMM11_AT_31 'i'
 467 #define PA_IMM14_AT_31 'j'
 468 #define PA_IMM21_AT_31 'k'
 469 #define PA_DISP12 'w'
 470 #define PA_DISP17 'W'
 471
 472 #define N_HPPA_OPERAND_FORMATS 5