1 /* cris.h -- Header file for CRIS opcode and register tables.
2 Copyright (C) 2000-2017 Free Software Foundation, Inc.
3 Contributed by Axis Communications AB, Lund, Sweden.
4 Originally written for GAS 1.38.1 by Mikael Asker.
5 Updated, BFDized and GNUified by Hans-Peter Nilsson.
7 This file is part of GAS, GDB and the GNU binutils.
9 GAS, GDB, and GNU binutils is free software; you can redistribute it
10 and/or modify it under the terms of the GNU General Public License as
11 published by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GAS, GDB, and GNU binutils are distributed in the hope that they will be
15 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
24 #ifndef __CRIS_H_INCLUDED_
25 #define __CRIS_H_INCLUDED_
27 #if !defined(__STDC__) && !defined(const)
37 /* CPU version control of disassembly and assembly of instructions.
38 May affect how the instruction is assembled, at least the size of
39 immediate operands. */
40 enum cris_insn_version_usage
43 cris_ver_version_all=0,
45 /* Indeterminate (intended for disassembly only, or obsolete). */
48 /* Only for v0..3 (Etrax 1..4). */
51 /* Only for v3 or higher (ETRAX 4 and beyond). */
54 /* Only for v8 (Etrax 100). */
57 /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */
60 /* Only for v0..10. FIXME: Not sure what to do with this. */
63 /* Only for v0..10. */
66 /* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */
69 /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */
72 /* Only for v10 (ETRAX 100 LX) and same series. */
75 /* Only for v10 (ETRAX 100 LX) and same series. */
78 /* Only for v32 or higher (codename GUINNESS).
79 Of course some or all these of may change to cris_ver_v32p if/when
80 there's a new revision. */
85 /* Special registers. */
88 const char *const name;
91 /* The size of the register. */
92 unsigned int reg_size;
94 /* What CPU version the special register of that name is implemented
95 in. If cris_ver_warning, emit an unimplemented-warning. */
96 enum cris_insn_version_usage applicable_version;
98 /* There might be a specific warning for using a special register
100 const char *const warning;
102 extern const struct cris_spec_reg cris_spec_regs[];
105 /* Support registers (kind of special too, but not named as such). */
106 struct cris_support_reg
108 const char *const name;
111 extern const struct cris_support_reg cris_support_regs[];
115 /* The name of the condition. */
116 const char *const name;
118 /* What CPU version this condition name applies to. */
119 enum cris_insn_version_usage applicable_version;
121 extern const struct cris_cond15 cris_conds15[];
123 /* Opcode-dependent constants. */
124 #define AUTOINCR_BIT (0x04)
127 #define BDAP_QUICK_OPCODE (0x0100)
128 #define BDAP_QUICK_Z_BITS (0x0e00)
130 #define BIAP_OPCODE (0x0540)
131 #define BIAP_Z_BITS (0x0a80)
133 #define DIP_OPCODE (0x0970)
134 #define DIP_Z_BITS (0xf280)
136 #define BDAP_INDIR_LOW (0x40)
137 #define BDAP_INDIR_LOW_Z (0x80)
138 #define BDAP_INDIR_HIGH (0x09)
139 #define BDAP_INDIR_HIGH_Z (0x02)
141 #define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
142 #define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
143 #define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC)
144 #define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT)
146 /* No prefix must have this code for its "match" bits in the
147 opcode-table. "BCC .+2" will do nicely. */
148 #define NO_CRIS_PREFIX 0
150 /* Definitions for condition codes. */
170 /* A table of strings "cc", "cs"... indexed with condition code
172 extern const char *const cris_cc_strings[];
175 #define BRANCH_QUICK_LOW (0)
176 #define BRANCH_QUICK_HIGH (0)
177 #define BRANCH_QUICK_OPCODE (BRANCH_QUICK_HIGH * 0x0100 + BRANCH_QUICK_LOW)
178 #define BRANCH_QUICK_Z_BITS (0x0F00)
181 #define BA_QUICK_HIGH (BRANCH_QUICK_HIGH + CC_A * 0x10)
182 #define BA_QUICK_OPCODE (BA_QUICK_HIGH * 0x100 + BRANCH_QUICK_LOW)
185 #define BRANCH_PC_LOW (0xFF)
186 #define BRANCH_INCR_HIGH (0x0D)
187 #define BA_PC_INCR_OPCODE \
188 ((BRANCH_INCR_HIGH + CC_A * 0x10) * 0x0100 + BRANCH_PC_LOW)
191 /* Note that old versions generated special register 8 (in high bits)
192 and not-that-old versions recognized it as a jump-instruction.
193 That opcode now belongs to JUMPU. */
194 #define JUMP_INDIR_OPCODE (0x0930)
195 #define JUMP_INDIR_Z_BITS (0xf2c0)
196 #define JUMP_PC_INCR_OPCODE \
197 (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
199 #define MOVE_M_TO_PREG_OPCODE 0x0a30
200 #define MOVE_M_TO_PREG_ZBITS 0x01c0
203 #define MOVE_PC_INCR_OPCODE_PREFIX \
204 (((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4))
205 #define MOVE_PC_INCR_OPCODE_SUFFIX \
206 (MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8))
208 #define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
210 /* BA DWORD (V32). */
211 #define BA_DWORD_OPCODE (0x0EBF)
214 #define NOP_OPCODE (0x050F)
215 #define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE)
217 #define NOP_OPCODE_V32 (0x05B0)
218 #define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32)
220 /* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect
221 registers or flags. Unfortunately shuts off interrupts for one cycle
222 for < v32, but there doesn't seem to be any alternative without that
224 #define NOP_OPCODE_COMMON (0x630)
225 #define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON)
228 #define LAPC_DWORD_OPCODE (0x0D7F)
229 #define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE)
231 /* Structure of an opcode table entry. */
232 enum cris_imm_oprnd_size_type
234 /* No size is applicable. */
237 /* Always 32 bits. */
240 /* Indicated by size of special register. */
243 /* Indicated by size field, signed. */
246 /* Indicated by size field, unsigned. */
249 /* Indicated by size field, no sign implied. */
253 /* For GDB. FIXME: Is this the best way to handle opcode
257 cris_not_implemented_op = 0,
269 cris_dstep_logshift_mstep_neg_not_op,
270 cris_eight_bit_offset_branch_op,
271 cris_move_mem_to_reg_movem_op,
272 cris_move_reg_to_mem_movem_op,
273 cris_move_to_preg_op,
276 cris_none_reg_mode_add_sub_cmp_and_or_move_op,
277 cris_none_reg_mode_clear_test_op,
278 cris_none_reg_mode_jump_op,
279 cris_none_reg_mode_move_from_preg_op,
280 cris_quick_mode_add_sub_op,
281 cris_quick_mode_and_cmp_move_or_op,
282 cris_quick_mode_bdap_prefix,
283 cris_reg_mode_add_sub_cmp_and_or_move_op,
284 cris_reg_mode_clear_op,
285 cris_reg_mode_jump_op,
286 cris_reg_mode_move_from_preg_op,
287 cris_reg_mode_test_op,
289 cris_sixteen_bit_offset_branch_op,
290 cris_three_operand_add_sub_cmp_and_or_op,
291 cris_three_operand_bound_op,
292 cris_two_operand_bound_op,
298 /* The name of the insn. */
301 /* Bits that must be 1 for a match. */
304 /* Bits that must be 0 for a match. */
307 /* See the table in "opcodes/cris-opc.c". */
310 /* Nonzero if this is a delayed branch instruction. */
313 /* Size of immediate operands. */
314 enum cris_imm_oprnd_size_type imm_oprnd_size;
316 /* Indicates which version this insn was first implemented in. */
317 enum cris_insn_version_usage applicable_version;
319 /* What kind of operation this is. */
320 enum cris_op_type op;
322 extern const struct cris_opcode cris_opcodes[];
325 /* These macros are for the target-specific flags in disassemble_info
326 used at disassembly. */
328 /* This insn accesses memory. This flag is more trustworthy than
329 checking insn_type for "dis_dref" which does not work for
331 #define CRIS_DIS_FLAG_MEMREF (1 << 0)
333 /* The "target" field holds a register number. */
334 #define CRIS_DIS_FLAG_MEM_TARGET_IS_REG (1 << 1)
336 /* The "target2" field holds a register number; add it to "target". */
337 #define CRIS_DIS_FLAG_MEM_TARGET2_IS_REG (1 << 2)
339 /* Yet another add-on: the register in "target2" must be multiplied
340 by 2 before adding to "target". */
341 #define CRIS_DIS_FLAG_MEM_TARGET2_MULT2 (1 << 3)
343 /* Yet another add-on: the register in "target2" must be multiplied
344 by 4 (mutually exclusive with .._MULT2). */
345 #define CRIS_DIS_FLAG_MEM_TARGET2_MULT4 (1 << 4)
347 /* The register in "target2" is an indirect memory reference (of the
348 register there), add to "target". Assumed size is dword (mutually
349 exclusive with .._MULT[24]). */
350 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM (1 << 5)
352 /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "byte";
353 sign-extended before adding to "target". */
354 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE (1 << 6)
356 /* Add-on to CRIS_DIS_FLAG_MEM_TARGET2_MEM; the memory access is "word";
357 sign-extended before adding to "target". */
358 #define CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD (1 << 7)
360 #endif /* __CRIS_H_INCLUDED_ */
364 * eval: (c-set-style "gnu")
365 * indent-tabs-mode: t