1 /* bfin.h -- Header file for ADI Blackfin opcode table
2 Copyright 2005, 2010, 2011 Free Software Foundation, Inc.
4 This file is part of GDB, GAS, and the GNU binutils.
6 GDB, GAS, and the GNU binutils are free software; you can redistribute
7 them and/or modify them under the terms of the GNU General Public
8 License as published by the Free Software Foundation; either version 3,
9 or (at your option) any later version.
11 GDB, GAS, and the GNU binutils are distributed in the hope that they
12 will be useful, but WITHOUT ANY WARRANTY; without even the implied
13 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
14 the GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this file; see the file COPYING3. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
24 /* Common to all DSP32 instructions. */
25 #define BIT_MULTI_INS 0x0800
27 /* This just sets the multi instruction bit of a DSP32 instruction. */
28 #define SET_MULTI_INSTRUCTION_BIT(x) x->value |= BIT_MULTI_INS;
31 /* DSP instructions (32 bit) */
44 static inline int is_macmod_pmove(int x)
46 return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_S2RND)
47 || (x == M_ISS2) || (x == M_IU);
50 static inline int is_macmod_hmove(int x)
52 return (x == 0) || (x == M_IS) || (x == M_FU) || (x == M_IU) || (x == M_T)
53 || (x == M_TFU) || (x == M_S2RND) || (x == M_ISS2) || (x == M_IH);
57 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
58 | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
59 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
60 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
102 #define DSP32Mac_opcode 0xc0000000
103 #define DSP32Mac_src1_bits 0
104 #define DSP32Mac_src1_mask 0x7
105 #define DSP32Mac_src0_bits 3
106 #define DSP32Mac_src0_mask 0x7
107 #define DSP32Mac_dst_bits 6
108 #define DSP32Mac_dst_mask 0x7
109 #define DSP32Mac_h10_bits 9
110 #define DSP32Mac_h10_mask 0x1
111 #define DSP32Mac_h00_bits 10
112 #define DSP32Mac_h00_mask 0x1
113 #define DSP32Mac_op0_bits 11
114 #define DSP32Mac_op0_mask 0x3
115 #define DSP32Mac_w0_bits 13
116 #define DSP32Mac_w0_mask 0x1
117 #define DSP32Mac_h11_bits 14
118 #define DSP32Mac_h11_mask 0x1
119 #define DSP32Mac_h01_bits 15
120 #define DSP32Mac_h01_mask 0x1
121 #define DSP32Mac_op1_bits 16
122 #define DSP32Mac_op1_mask 0x3
123 #define DSP32Mac_w1_bits 18
124 #define DSP32Mac_w1_mask 0x1
125 #define DSP32Mac_p_bits 19
126 #define DSP32Mac_p_mask 0x1
127 #define DSP32Mac_MM_bits 20
128 #define DSP32Mac_MM_mask 0x1
129 #define DSP32Mac_mmod_bits 21
130 #define DSP32Mac_mmod_mask 0xf
131 #define DSP32Mac_code2_bits 25
132 #define DSP32Mac_code2_mask 0x3
133 #define DSP32Mac_M_bits 27
134 #define DSP32Mac_M_mask 0x1
135 #define DSP32Mac_code_bits 28
136 #define DSP32Mac_code_mask 0xf
138 #define init_DSP32Mac \
141 DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
142 DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
143 DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
144 DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
145 DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
146 DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
147 DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
148 DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
149 DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
150 DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
151 DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
152 DSP32Mac_p_bits, DSP32Mac_p_mask, \
153 DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
154 DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
155 DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
156 DSP32Mac_M_bits, DSP32Mac_M_mask, \
157 DSP32Mac_code_bits, DSP32Mac_code_mask \
161 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
162 | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
163 |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1......|
164 +----+----+---+---|---+----+----+---|---+---+---+---|---+---+---+---+
167 typedef DSP32Mac DSP32Mult;
168 #define DSP32Mult_opcode 0xc2000000
170 #define init_DSP32Mult \
173 DSP32Mac_src1_bits, DSP32Mac_src1_mask, \
174 DSP32Mac_src0_bits, DSP32Mac_src0_mask, \
175 DSP32Mac_dst_bits, DSP32Mac_dst_mask, \
176 DSP32Mac_h10_bits, DSP32Mac_h10_mask, \
177 DSP32Mac_h00_bits, DSP32Mac_h00_mask, \
178 DSP32Mac_op0_bits, DSP32Mac_op0_mask, \
179 DSP32Mac_w0_bits, DSP32Mac_w0_mask, \
180 DSP32Mac_h11_bits, DSP32Mac_h11_mask, \
181 DSP32Mac_h01_bits, DSP32Mac_h01_mask, \
182 DSP32Mac_op1_bits, DSP32Mac_op1_mask, \
183 DSP32Mac_w1_bits, DSP32Mac_w1_mask, \
184 DSP32Mac_p_bits, DSP32Mac_p_mask, \
185 DSP32Mac_MM_bits, DSP32Mac_MM_mask, \
186 DSP32Mac_mmod_bits, DSP32Mac_mmod_mask, \
187 DSP32Mac_code2_bits, DSP32Mac_code2_mask, \
188 DSP32Mac_M_bits, DSP32Mac_M_mask, \
189 DSP32Mac_code_bits, DSP32Mac_code_mask \
193 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
194 | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
195 |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
196 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
201 unsigned long opcode;
230 #define DSP32Alu_opcode 0xc4000000
231 #define DSP32Alu_src1_bits 0
232 #define DSP32Alu_src1_mask 0x7
233 #define DSP32Alu_src0_bits 3
234 #define DSP32Alu_src0_mask 0x7
235 #define DSP32Alu_dst1_bits 6
236 #define DSP32Alu_dst1_mask 0x7
237 #define DSP32Alu_dst0_bits 9
238 #define DSP32Alu_dst0_mask 0x7
239 #define DSP32Alu_x_bits 12
240 #define DSP32Alu_x_mask 0x1
241 #define DSP32Alu_s_bits 13
242 #define DSP32Alu_s_mask 0x1
243 #define DSP32Alu_aop_bits 14
244 #define DSP32Alu_aop_mask 0x3
245 #define DSP32Alu_aopcde_bits 16
246 #define DSP32Alu_aopcde_mask 0x1f
247 #define DSP32Alu_HL_bits 21
248 #define DSP32Alu_HL_mask 0x1
249 #define DSP32Alu_dontcare_bits 22
250 #define DSP32Alu_dontcare_mask 0x7
251 #define DSP32Alu_code2_bits 25
252 #define DSP32Alu_code2_mask 0x3
253 #define DSP32Alu_M_bits 27
254 #define DSP32Alu_M_mask 0x1
255 #define DSP32Alu_code_bits 28
256 #define DSP32Alu_code_mask 0xf
258 #define init_DSP32Alu \
261 DSP32Alu_src1_bits, DSP32Alu_src1_mask, \
262 DSP32Alu_src0_bits, DSP32Alu_src0_mask, \
263 DSP32Alu_dst1_bits, DSP32Alu_dst1_mask, \
264 DSP32Alu_dst0_bits, DSP32Alu_dst0_mask, \
265 DSP32Alu_x_bits, DSP32Alu_x_mask, \
266 DSP32Alu_s_bits, DSP32Alu_s_mask, \
267 DSP32Alu_aop_bits, DSP32Alu_aop_mask, \
268 DSP32Alu_aopcde_bits, DSP32Alu_aopcde_mask, \
269 DSP32Alu_HL_bits, DSP32Alu_HL_mask, \
270 DSP32Alu_dontcare_bits, DSP32Alu_dontcare_mask, \
271 DSP32Alu_code2_bits, DSP32Alu_code2_mask, \
272 DSP32Alu_M_bits, DSP32Alu_M_mask, \
273 DSP32Alu_code_bits, DSP32Alu_code_mask \
277 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
278 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
279 |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
280 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
285 unsigned long opcode;
310 #define DSP32Shift_opcode 0xc6000000
311 #define DSP32Shift_src1_bits 0
312 #define DSP32Shift_src1_mask 0x7
313 #define DSP32Shift_src0_bits 3
314 #define DSP32Shift_src0_mask 0x7
315 #define DSP32Shift_dst1_bits 6
316 #define DSP32Shift_dst1_mask 0x7
317 #define DSP32Shift_dst0_bits 9
318 #define DSP32Shift_dst0_mask 0x7
319 #define DSP32Shift_HLs_bits 12
320 #define DSP32Shift_HLs_mask 0x3
321 #define DSP32Shift_sop_bits 14
322 #define DSP32Shift_sop_mask 0x3
323 #define DSP32Shift_sopcde_bits 16
324 #define DSP32Shift_sopcde_mask 0x1f
325 #define DSP32Shift_dontcare_bits 21
326 #define DSP32Shift_dontcare_mask 0x3
327 #define DSP32Shift_code2_bits 23
328 #define DSP32Shift_code2_mask 0xf
329 #define DSP32Shift_M_bits 27
330 #define DSP32Shift_M_mask 0x1
331 #define DSP32Shift_code_bits 28
332 #define DSP32Shift_code_mask 0xf
334 #define init_DSP32Shift \
337 DSP32Shift_src1_bits, DSP32Shift_src1_mask, \
338 DSP32Shift_src0_bits, DSP32Shift_src0_mask, \
339 DSP32Shift_dst1_bits, DSP32Shift_dst1_mask, \
340 DSP32Shift_dst0_bits, DSP32Shift_dst0_mask, \
341 DSP32Shift_HLs_bits, DSP32Shift_HLs_mask, \
342 DSP32Shift_sop_bits, DSP32Shift_sop_mask, \
343 DSP32Shift_sopcde_bits, DSP32Shift_sopcde_mask, \
344 DSP32Shift_dontcare_bits, DSP32Shift_dontcare_mask, \
345 DSP32Shift_code2_bits, DSP32Shift_code2_mask, \
346 DSP32Shift_M_bits, DSP32Shift_M_mask, \
347 DSP32Shift_code_bits, DSP32Shift_code_mask \
351 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
352 | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
353 |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
354 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
359 unsigned long opcode;
382 #define DSP32ShiftImm_opcode 0xc6800000
383 #define DSP32ShiftImm_src1_bits 0
384 #define DSP32ShiftImm_src1_mask 0x7
385 #define DSP32ShiftImm_immag_bits 3
386 #define DSP32ShiftImm_immag_mask 0x3f
387 #define DSP32ShiftImm_dst0_bits 9
388 #define DSP32ShiftImm_dst0_mask 0x7
389 #define DSP32ShiftImm_HLs_bits 12
390 #define DSP32ShiftImm_HLs_mask 0x3
391 #define DSP32ShiftImm_sop_bits 14
392 #define DSP32ShiftImm_sop_mask 0x3
393 #define DSP32ShiftImm_sopcde_bits 16
394 #define DSP32ShiftImm_sopcde_mask 0x1f
395 #define DSP32ShiftImm_dontcare_bits 21
396 #define DSP32ShiftImm_dontcare_mask 0x3
397 #define DSP32ShiftImm_code2_bits 23
398 #define DSP32ShiftImm_code2_mask 0xf
399 #define DSP32ShiftImm_M_bits 27
400 #define DSP32ShiftImm_M_mask 0x1
401 #define DSP32ShiftImm_code_bits 28
402 #define DSP32ShiftImm_code_mask 0xf
404 #define init_DSP32ShiftImm \
406 DSP32ShiftImm_opcode, \
407 DSP32ShiftImm_src1_bits, DSP32ShiftImm_src1_mask, \
408 DSP32ShiftImm_immag_bits, DSP32ShiftImm_immag_mask, \
409 DSP32ShiftImm_dst0_bits, DSP32ShiftImm_dst0_mask, \
410 DSP32ShiftImm_HLs_bits, DSP32ShiftImm_HLs_mask, \
411 DSP32ShiftImm_sop_bits, DSP32ShiftImm_sop_mask, \
412 DSP32ShiftImm_sopcde_bits, DSP32ShiftImm_sopcde_mask, \
413 DSP32ShiftImm_dontcare_bits, DSP32ShiftImm_dontcare_mask, \
414 DSP32ShiftImm_code2_bits, DSP32ShiftImm_code2_mask, \
415 DSP32ShiftImm_M_bits, DSP32ShiftImm_M_mask, \
416 DSP32ShiftImm_code_bits, DSP32ShiftImm_code_mask \
422 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
423 | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
424 |.offset........................................................|
425 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
430 unsigned long opcode;
447 #define LDSTidxI_opcode 0xe4000000
448 #define LDSTidxI_offset_bits 0
449 #define LDSTidxI_offset_mask 0xffff
450 #define LDSTidxI_reg_bits 16
451 #define LDSTidxI_reg_mask 0x7
452 #define LDSTidxI_ptr_bits 19
453 #define LDSTidxI_ptr_mask 0x7
454 #define LDSTidxI_sz_bits 22
455 #define LDSTidxI_sz_mask 0x3
456 #define LDSTidxI_Z_bits 24
457 #define LDSTidxI_Z_mask 0x1
458 #define LDSTidxI_W_bits 25
459 #define LDSTidxI_W_mask 0x1
460 #define LDSTidxI_code_bits 26
461 #define LDSTidxI_code_mask 0x3f
463 #define init_LDSTidxI \
466 LDSTidxI_offset_bits, LDSTidxI_offset_mask, \
467 LDSTidxI_reg_bits, LDSTidxI_reg_mask, \
468 LDSTidxI_ptr_bits, LDSTidxI_ptr_mask, \
469 LDSTidxI_sz_bits, LDSTidxI_sz_mask, \
470 LDSTidxI_Z_bits, LDSTidxI_Z_mask, \
471 LDSTidxI_W_bits, LDSTidxI_W_mask, \
472 LDSTidxI_code_bits, LDSTidxI_code_mask \
477 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
478 | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
479 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
484 unsigned short opcode;
501 #define LDST_opcode 0x9000
502 #define LDST_reg_bits 0
503 #define LDST_reg_mask 0x7
504 #define LDST_ptr_bits 3
505 #define LDST_ptr_mask 0x7
506 #define LDST_Z_bits 6
507 #define LDST_Z_mask 0x1
508 #define LDST_aop_bits 7
509 #define LDST_aop_mask 0x3
510 #define LDST_W_bits 9
511 #define LDST_W_mask 0x1
512 #define LDST_sz_bits 10
513 #define LDST_sz_mask 0x3
514 #define LDST_code_bits 12
515 #define LDST_code_mask 0xf
520 LDST_reg_bits, LDST_reg_mask, \
521 LDST_ptr_bits, LDST_ptr_mask, \
522 LDST_Z_bits, LDST_Z_mask, \
523 LDST_aop_bits, LDST_aop_mask, \
524 LDST_W_bits, LDST_W_mask, \
525 LDST_sz_bits, LDST_sz_mask, \
526 LDST_code_bits, LDST_code_mask \
530 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
531 | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
532 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
537 unsigned short opcode;
552 #define LDSTii_opcode 0xa000
553 #define LDSTii_reg_bit 0
554 #define LDSTii_reg_mask 0x7
555 #define LDSTii_ptr_bit 3
556 #define LDSTii_ptr_mask 0x7
557 #define LDSTii_offset_bit 6
558 #define LDSTii_offset_mask 0xf
559 #define LDSTii_op_bit 10
560 #define LDSTii_op_mask 0x3
561 #define LDSTii_W_bit 12
562 #define LDSTii_W_mask 0x1
563 #define LDSTii_code_bit 13
564 #define LDSTii_code_mask 0x7
566 #define init_LDSTii \
569 LDSTii_reg_bit, LDSTii_reg_mask, \
570 LDSTii_ptr_bit, LDSTii_ptr_mask, \
571 LDSTii_offset_bit, LDSTii_offset_mask, \
572 LDSTii_op_bit, LDSTii_op_mask, \
573 LDSTii_W_bit, LDSTii_W_mask, \
574 LDSTii_code_bit, LDSTii_code_mask \
579 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
580 | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
581 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
586 unsigned short opcode;
597 #define LDSTiiFP_opcode 0xb800
598 #define LDSTiiFP_reg_bits 0
599 #define LDSTiiFP_reg_mask 0xf
600 #define LDSTiiFP_offset_bits 4
601 #define LDSTiiFP_offset_mask 0x1f
602 #define LDSTiiFP_W_bits 9
603 #define LDSTiiFP_W_mask 0x1
604 #define LDSTiiFP_code_bits 10
605 #define LDSTiiFP_code_mask 0x3f
607 #define init_LDSTiiFP \
610 LDSTiiFP_reg_bits, LDSTiiFP_reg_mask, \
611 LDSTiiFP_offset_bits, LDSTiiFP_offset_mask, \
612 LDSTiiFP_W_bits, LDSTiiFP_W_mask, \
613 LDSTiiFP_code_bits, LDSTiiFP_code_mask \
617 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
618 | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
619 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
624 unsigned short opcode;
639 #define DspLDST_opcode 0x9c00
640 #define DspLDST_reg_bits 0
641 #define DspLDST_reg_mask 0x7
642 #define DspLDST_i_bits 3
643 #define DspLDST_i_mask 0x3
644 #define DspLDST_m_bits 5
645 #define DspLDST_m_mask 0x3
646 #define DspLDST_aop_bits 7
647 #define DspLDST_aop_mask 0x3
648 #define DspLDST_W_bits 9
649 #define DspLDST_W_mask 0x1
650 #define DspLDST_code_bits 10
651 #define DspLDST_code_mask 0x3f
653 #define init_DspLDST \
656 DspLDST_reg_bits, DspLDST_reg_mask, \
657 DspLDST_i_bits, DspLDST_i_mask, \
658 DspLDST_m_bits, DspLDST_m_mask, \
659 DspLDST_aop_bits, DspLDST_aop_mask, \
660 DspLDST_W_bits, DspLDST_W_mask, \
661 DspLDST_code_bits, DspLDST_code_mask \
666 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
667 | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
668 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
673 unsigned short opcode;
688 #define LDSTpmod_opcode 0x8000
689 #define LDSTpmod_ptr_bits 0
690 #define LDSTpmod_ptr_mask 0x7
691 #define LDSTpmod_idx_bits 3
692 #define LDSTpmod_idx_mask 0x7
693 #define LDSTpmod_reg_bits 6
694 #define LDSTpmod_reg_mask 0x7
695 #define LDSTpmod_aop_bits 9
696 #define LDSTpmod_aop_mask 0x3
697 #define LDSTpmod_W_bits 11
698 #define LDSTpmod_W_mask 0x1
699 #define LDSTpmod_code_bits 12
700 #define LDSTpmod_code_mask 0xf
702 #define init_LDSTpmod \
705 LDSTpmod_ptr_bits, LDSTpmod_ptr_mask, \
706 LDSTpmod_idx_bits, LDSTpmod_idx_mask, \
707 LDSTpmod_reg_bits, LDSTpmod_reg_mask, \
708 LDSTpmod_aop_bits, LDSTpmod_aop_mask, \
709 LDSTpmod_W_bits, LDSTpmod_W_mask, \
710 LDSTpmod_code_bits, LDSTpmod_code_mask \
715 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
716 | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
717 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
722 unsigned short opcode;
733 #define LOGI2op_opcode 0x4800
734 #define LOGI2op_dst_bits 0
735 #define LOGI2op_dst_mask 0x7
736 #define LOGI2op_src_bits 3
737 #define LOGI2op_src_mask 0x1f
738 #define LOGI2op_opc_bits 8
739 #define LOGI2op_opc_mask 0x7
740 #define LOGI2op_code_bits 11
741 #define LOGI2op_code_mask 0x1f
743 #define init_LOGI2op \
746 LOGI2op_dst_bits, LOGI2op_dst_mask, \
747 LOGI2op_src_bits, LOGI2op_src_mask, \
748 LOGI2op_opc_bits, LOGI2op_opc_mask, \
749 LOGI2op_code_bits, LOGI2op_code_mask \
754 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
755 | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
756 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
761 unsigned short opcode;
772 #define ALU2op_opcode 0x4000
773 #define ALU2op_dst_bits 0
774 #define ALU2op_dst_mask 0x7
775 #define ALU2op_src_bits 3
776 #define ALU2op_src_mask 0x7
777 #define ALU2op_opc_bits 6
778 #define ALU2op_opc_mask 0xf
779 #define ALU2op_code_bits 10
780 #define ALU2op_code_mask 0x3f
782 #define init_ALU2op \
785 ALU2op_dst_bits, ALU2op_dst_mask, \
786 ALU2op_src_bits, ALU2op_src_mask, \
787 ALU2op_opc_bits, ALU2op_opc_mask, \
788 ALU2op_code_bits, ALU2op_code_mask \
793 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
794 | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
795 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
800 unsigned short opcode;
811 #define BRCC_opcode 0x1000
812 #define BRCC_offset_bits 0
813 #define BRCC_offset_mask 0x3ff
814 #define BRCC_B_bits 10
815 #define BRCC_B_mask 0x1
816 #define BRCC_T_bits 11
817 #define BRCC_T_mask 0x1
818 #define BRCC_code_bits 12
819 #define BRCC_code_mask 0xf
824 BRCC_offset_bits, BRCC_offset_mask, \
825 BRCC_B_bits, BRCC_B_mask, \
826 BRCC_T_bits, BRCC_T_mask, \
827 BRCC_code_bits, BRCC_code_mask \
832 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
833 | 0 | 0 | 1 | 0 |.offset........................................|
834 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
839 unsigned short opcode;
846 #define UJump_opcode 0x2000
847 #define UJump_offset_bits 0
848 #define UJump_offset_mask 0xfff
849 #define UJump_code_bits 12
850 #define UJump_code_mask 0xf
855 UJump_offset_bits, UJump_offset_mask, \
856 UJump_code_bits, UJump_code_mask \
861 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
862 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
863 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
868 unsigned short opcode;
877 #define ProgCtrl_opcode 0x0000
878 #define ProgCtrl_poprnd_bits 0
879 #define ProgCtrl_poprnd_mask 0xf
880 #define ProgCtrl_prgfunc_bits 4
881 #define ProgCtrl_prgfunc_mask 0xf
882 #define ProgCtrl_code_bits 8
883 #define ProgCtrl_code_mask 0xff
885 #define init_ProgCtrl \
888 ProgCtrl_poprnd_bits, ProgCtrl_poprnd_mask, \
889 ProgCtrl_prgfunc_bits, ProgCtrl_prgfunc_mask, \
890 ProgCtrl_code_bits, ProgCtrl_code_mask \
894 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
895 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
896 |.lsw...........................................................|
897 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
903 unsigned long opcode;
912 #define CALLa_opcode 0xe2000000
913 #define CALLa_addr_bits 0
914 #define CALLa_addr_mask 0xffffff
915 #define CALLa_S_bits 24
916 #define CALLa_S_mask 0x1
917 #define CALLa_code_bits 25
918 #define CALLa_code_mask 0x7f
923 CALLa_addr_bits, CALLa_addr_mask, \
924 CALLa_S_bits, CALLa_S_mask, \
925 CALLa_code_bits, CALLa_code_mask \
930 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
931 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
932 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
937 unsigned short opcode;
948 #define PseudoDbg_opcode 0xf800
949 #define PseudoDbg_reg_bits 0
950 #define PseudoDbg_reg_mask 0x7
951 #define PseudoDbg_grp_bits 3
952 #define PseudoDbg_grp_mask 0x7
953 #define PseudoDbg_fn_bits 6
954 #define PseudoDbg_fn_mask 0x3
955 #define PseudoDbg_code_bits 8
956 #define PseudoDbg_code_mask 0xff
958 #define init_PseudoDbg \
961 PseudoDbg_reg_bits, PseudoDbg_reg_mask, \
962 PseudoDbg_grp_bits, PseudoDbg_grp_mask, \
963 PseudoDbg_fn_bits, PseudoDbg_fn_mask, \
964 PseudoDbg_code_bits, PseudoDbg_code_mask \
968 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
969 | 1 | 1 | 1 | 1 | 0 | - | - | - | dbgop |.grp.......|.regtest...|
970 |.expected......................................................|
971 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
976 unsigned long opcode;
991 #define PseudoDbg_Assert_opcode 0xf0000000
992 #define PseudoDbg_Assert_expected_bits 0
993 #define PseudoDbg_Assert_expected_mask 0xffff
994 #define PseudoDbg_Assert_regtest_bits 16
995 #define PseudoDbg_Assert_regtest_mask 0x7
996 #define PseudoDbg_Assert_grp_bits 19
997 #define PseudoDbg_Assert_grp_mask 0x7
998 #define PseudoDbg_Assert_dbgop_bits 22
999 #define PseudoDbg_Assert_dbgop_mask 0x3
1000 #define PseudoDbg_Assert_dontcare_bits 24
1001 #define PseudoDbg_Assert_dontcare_mask 0x7
1002 #define PseudoDbg_Assert_code_bits 27
1003 #define PseudoDbg_Assert_code_mask 0x1f
1005 #define init_PseudoDbg_Assert \
1007 PseudoDbg_Assert_opcode, \
1008 PseudoDbg_Assert_expected_bits, PseudoDbg_Assert_expected_mask, \
1009 PseudoDbg_Assert_regtest_bits, PseudoDbg_Assert_regtest_mask, \
1010 PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask, \
1011 PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, \
1012 PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask, \
1013 PseudoDbg_Assert_code_bits, PseudoDbg_Assert_code_mask \
1017 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1018 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |.ch............................|
1019 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1024 unsigned short opcode;
1031 #define PseudoChr_opcode 0xf900
1032 #define PseudoChr_ch_bits 0
1033 #define PseudoChr_ch_mask 0xff
1034 #define PseudoChr_code_bits 8
1035 #define PseudoChr_code_mask 0xff
1037 #define init_PseudoChr \
1040 PseudoChr_ch_bits, PseudoChr_ch_mask, \
1041 PseudoChr_code_bits, PseudoChr_code_mask \
1045 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1046 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
1047 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1052 unsigned short opcode;
1063 #define CaCTRL_opcode 0x0240
1064 #define CaCTRL_reg_bits 0
1065 #define CaCTRL_reg_mask 0x7
1066 #define CaCTRL_op_bits 3
1067 #define CaCTRL_op_mask 0x3
1068 #define CaCTRL_a_bits 5
1069 #define CaCTRL_a_mask 0x1
1070 #define CaCTRL_code_bits 6
1071 #define CaCTRL_code_mask 0x3fff
1073 #define init_CaCTRL \
1076 CaCTRL_reg_bits, CaCTRL_reg_mask, \
1077 CaCTRL_op_bits, CaCTRL_op_mask, \
1078 CaCTRL_a_bits, CaCTRL_a_mask, \
1079 CaCTRL_code_bits, CaCTRL_code_mask \
1083 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1084 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
1085 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1090 unsigned short opcode;
1105 #define PushPopMultiple_opcode 0x0400
1106 #define PushPopMultiple_pr_bits 0
1107 #define PushPopMultiple_pr_mask 0x7
1108 #define PushPopMultiple_dr_bits 3
1109 #define PushPopMultiple_dr_mask 0x7
1110 #define PushPopMultiple_W_bits 6
1111 #define PushPopMultiple_W_mask 0x1
1112 #define PushPopMultiple_p_bits 7
1113 #define PushPopMultiple_p_mask 0x1
1114 #define PushPopMultiple_d_bits 8
1115 #define PushPopMultiple_d_mask 0x1
1116 #define PushPopMultiple_code_bits 8
1117 #define PushPopMultiple_code_mask 0x1
1119 #define init_PushPopMultiple \
1121 PushPopMultiple_opcode, \
1122 PushPopMultiple_pr_bits, PushPopMultiple_pr_mask, \
1123 PushPopMultiple_dr_bits, PushPopMultiple_dr_mask, \
1124 PushPopMultiple_W_bits, PushPopMultiple_W_mask, \
1125 PushPopMultiple_p_bits, PushPopMultiple_p_mask, \
1126 PushPopMultiple_d_bits, PushPopMultiple_d_mask, \
1127 PushPopMultiple_code_bits, PushPopMultiple_code_mask \
1131 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1132 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
1133 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1138 unsigned short opcode;
1149 #define PushPopReg_opcode 0x0100
1150 #define PushPopReg_reg_bits 0
1151 #define PushPopReg_reg_mask 0x7
1152 #define PushPopReg_grp_bits 3
1153 #define PushPopReg_grp_mask 0x7
1154 #define PushPopReg_W_bits 6
1155 #define PushPopReg_W_mask 0x1
1156 #define PushPopReg_code_bits 7
1157 #define PushPopReg_code_mask 0x1ff
1159 #define init_PushPopReg \
1161 PushPopReg_opcode, \
1162 PushPopReg_reg_bits, PushPopReg_reg_mask, \
1163 PushPopReg_grp_bits, PushPopReg_grp_mask, \
1164 PushPopReg_W_bits, PushPopReg_W_mask, \
1165 PushPopReg_code_bits, PushPopReg_code_mask, \
1169 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1170 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
1171 |.framesize.....................................................|
1172 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1177 unsigned long opcode;
1186 #define Linkage_opcode 0xe8000000
1187 #define Linkage_framesize_bits 0
1188 #define Linkage_framesize_mask 0xffff
1189 #define Linkage_R_bits 16
1190 #define Linkage_R_mask 0x1
1191 #define Linkage_code_bits 17
1192 #define Linkage_code_mask 0x7fff
1194 #define init_Linkage \
1197 Linkage_framesize_bits, Linkage_framesize_mask, \
1198 Linkage_R_bits, Linkage_R_mask, \
1199 Linkage_code_bits, Linkage_code_mask \
1203 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1204 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
1205 |.reg...........| - | - |.eoffset...............................|
1206 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1211 unsigned long opcode;
1228 #define LoopSetup_opcode 0xe0800000
1229 #define LoopSetup_eoffset_bits 0
1230 #define LoopSetup_eoffset_mask 0x3ff
1231 #define LoopSetup_dontcare_bits 10
1232 #define LoopSetup_dontcare_mask 0x3
1233 #define LoopSetup_reg_bits 12
1234 #define LoopSetup_reg_mask 0xf
1235 #define LoopSetup_soffset_bits 16
1236 #define LoopSetup_soffset_mask 0xf
1237 #define LoopSetup_c_bits 20
1238 #define LoopSetup_c_mask 0x1
1239 #define LoopSetup_rop_bits 21
1240 #define LoopSetup_rop_mask 0x3
1241 #define LoopSetup_code_bits 23
1242 #define LoopSetup_code_mask 0x1ff
1244 #define init_LoopSetup \
1247 LoopSetup_eoffset_bits, LoopSetup_eoffset_mask, \
1248 LoopSetup_dontcare_bits, LoopSetup_dontcare_mask, \
1249 LoopSetup_reg_bits, LoopSetup_reg_mask, \
1250 LoopSetup_soffset_bits, LoopSetup_soffset_mask, \
1251 LoopSetup_c_bits, LoopSetup_c_mask, \
1252 LoopSetup_rop_bits, LoopSetup_rop_mask, \
1253 LoopSetup_code_bits, LoopSetup_code_mask \
1257 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1258 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
1259 |.hword.........................................................|
1260 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1265 unsigned long opcode;
1282 #define LDIMMhalf_opcode 0xe1000000
1283 #define LDIMMhalf_hword_bits 0
1284 #define LDIMMhalf_hword_mask 0xffff
1285 #define LDIMMhalf_reg_bits 16
1286 #define LDIMMhalf_reg_mask 0x7
1287 #define LDIMMhalf_grp_bits 19
1288 #define LDIMMhalf_grp_mask 0x3
1289 #define LDIMMhalf_S_bits 21
1290 #define LDIMMhalf_S_mask 0x1
1291 #define LDIMMhalf_H_bits 22
1292 #define LDIMMhalf_H_mask 0x1
1293 #define LDIMMhalf_Z_bits 23
1294 #define LDIMMhalf_Z_mask 0x1
1295 #define LDIMMhalf_code_bits 24
1296 #define LDIMMhalf_code_mask 0xff
1298 #define init_LDIMMhalf \
1301 LDIMMhalf_hword_bits, LDIMMhalf_hword_mask, \
1302 LDIMMhalf_reg_bits, LDIMMhalf_reg_mask, \
1303 LDIMMhalf_grp_bits, LDIMMhalf_grp_mask, \
1304 LDIMMhalf_S_bits, LDIMMhalf_S_mask, \
1305 LDIMMhalf_H_bits, LDIMMhalf_H_mask, \
1306 LDIMMhalf_Z_bits, LDIMMhalf_Z_mask, \
1307 LDIMMhalf_code_bits, LDIMMhalf_code_mask \
1312 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1313 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
1314 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1319 unsigned short opcode;
1328 #define CC2dreg_opcode 0x0200
1329 #define CC2dreg_reg_bits 0
1330 #define CC2dreg_reg_mask 0x7
1331 #define CC2dreg_op_bits 3
1332 #define CC2dreg_op_mask 0x3
1333 #define CC2dreg_code_bits 5
1334 #define CC2dreg_code_mask 0x7fff
1336 #define init_CC2dreg \
1339 CC2dreg_reg_bits, CC2dreg_reg_mask, \
1340 CC2dreg_op_bits, CC2dreg_op_mask, \
1341 CC2dreg_code_bits, CC2dreg_code_mask \
1346 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1347 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
1348 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1353 unsigned short opcode;
1364 #define PTR2op_opcode 0x4400
1365 #define PTR2op_dst_bits 0
1366 #define PTR2op_dst_mask 0x7
1367 #define PTR2op_src_bits 3
1368 #define PTR2op_src_mask 0x7
1369 #define PTR2op_opc_bits 6
1370 #define PTR2op_opc_mask 0x7
1371 #define PTR2op_code_bits 9
1372 #define PTR2op_code_mask 0x7f
1374 #define init_PTR2op \
1377 PTR2op_dst_bits, PTR2op_dst_mask, \
1378 PTR2op_src_bits, PTR2op_src_mask, \
1379 PTR2op_opc_bits, PTR2op_opc_mask, \
1380 PTR2op_code_bits, PTR2op_code_mask \
1385 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1386 | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
1387 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1392 unsigned short opcode;
1405 #define COMP3op_opcode 0x5000
1406 #define COMP3op_src0_bits 0
1407 #define COMP3op_src0_mask 0x7
1408 #define COMP3op_src1_bits 3
1409 #define COMP3op_src1_mask 0x7
1410 #define COMP3op_dst_bits 6
1411 #define COMP3op_dst_mask 0x7
1412 #define COMP3op_opc_bits 9
1413 #define COMP3op_opc_mask 0x7
1414 #define COMP3op_code_bits 12
1415 #define COMP3op_code_mask 0xf
1417 #define init_COMP3op \
1420 COMP3op_src0_bits, COMP3op_src0_mask, \
1421 COMP3op_src1_bits, COMP3op_src1_mask, \
1422 COMP3op_dst_bits, COMP3op_dst_mask, \
1423 COMP3op_opc_bits, COMP3op_opc_mask, \
1424 COMP3op_code_bits, COMP3op_code_mask \
1428 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1429 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
1430 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1435 unsigned short opcode;
1450 #define CCmv_opcode 0x0600
1451 #define CCmv_src_bits 0
1452 #define CCmv_src_mask 0x7
1453 #define CCmv_dst_bits 3
1454 #define CCmv_dst_mask 0x7
1455 #define CCmv_s_bits 6
1456 #define CCmv_s_mask 0x1
1457 #define CCmv_d_bits 7
1458 #define CCmv_d_mask 0x1
1459 #define CCmv_T_bits 8
1460 #define CCmv_T_mask 0x1
1461 #define CCmv_code_bits 9
1462 #define CCmv_code_mask 0x7f
1467 CCmv_src_bits, CCmv_src_mask, \
1468 CCmv_dst_bits, CCmv_dst_mask, \
1469 CCmv_s_bits, CCmv_s_mask, \
1470 CCmv_d_bits, CCmv_d_mask, \
1471 CCmv_T_bits, CCmv_T_mask, \
1472 CCmv_code_bits, CCmv_code_mask \
1477 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1478 | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
1479 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1484 unsigned short opcode;
1499 #define CCflag_opcode 0x0800
1500 #define CCflag_x_bits 0
1501 #define CCflag_x_mask 0x7
1502 #define CCflag_y_bits 3
1503 #define CCflag_y_mask 0x7
1504 #define CCflag_G_bits 6
1505 #define CCflag_G_mask 0x1
1506 #define CCflag_opc_bits 7
1507 #define CCflag_opc_mask 0x7
1508 #define CCflag_I_bits 10
1509 #define CCflag_I_mask 0x1
1510 #define CCflag_code_bits 11
1511 #define CCflag_code_mask 0x1f
1513 #define init_CCflag \
1516 CCflag_x_bits, CCflag_x_mask, \
1517 CCflag_y_bits, CCflag_y_mask, \
1518 CCflag_G_bits, CCflag_G_mask, \
1519 CCflag_opc_bits, CCflag_opc_mask, \
1520 CCflag_I_bits, CCflag_I_mask, \
1521 CCflag_code_bits, CCflag_code_mask, \
1526 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1527 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
1528 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1533 unsigned short opcode;
1544 #define CC2stat_opcode 0x0300
1545 #define CC2stat_cbit_bits 0
1546 #define CC2stat_cbit_mask 0x1f
1547 #define CC2stat_op_bits 5
1548 #define CC2stat_op_mask 0x3
1549 #define CC2stat_D_bits 7
1550 #define CC2stat_D_mask 0x1
1551 #define CC2stat_code_bits 8
1552 #define CC2stat_code_mask 0xff
1554 #define init_CC2stat \
1557 CC2stat_cbit_bits, CC2stat_cbit_mask, \
1558 CC2stat_op_bits, CC2stat_op_mask, \
1559 CC2stat_D_bits, CC2stat_D_mask, \
1560 CC2stat_code_bits, CC2stat_code_mask \
1565 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1566 | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
1567 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1572 unsigned short opcode;
1585 #define RegMv_opcode 0x3000
1586 #define RegMv_src_bits 0
1587 #define RegMv_src_mask 0x7
1588 #define RegMv_dst_bits 3
1589 #define RegMv_dst_mask 0x7
1590 #define RegMv_gs_bits 6
1591 #define RegMv_gs_mask 0x7
1592 #define RegMv_gd_bits 9
1593 #define RegMv_gd_mask 0x7
1594 #define RegMv_code_bits 12
1595 #define RegMv_code_mask 0xf
1597 #define init_RegMv \
1600 RegMv_src_bits, RegMv_src_mask, \
1601 RegMv_dst_bits, RegMv_dst_mask, \
1602 RegMv_gs_bits, RegMv_gs_mask, \
1603 RegMv_gd_bits, RegMv_gd_mask, \
1604 RegMv_code_bits, RegMv_code_mask \
1609 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1610 | 0 | 1 | 1 | 0 | 0 |.op|.isrc......................|.dst.......|
1611 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1616 unsigned short opcode;
1627 #define COMPI2opD_opcode 0x6000
1628 #define COMPI2opD_dst_bits 0
1629 #define COMPI2opD_dst_mask 0x7
1630 #define COMPI2opD_src_bits 3
1631 #define COMPI2opD_src_mask 0x7f
1632 #define COMPI2opD_op_bits 10
1633 #define COMPI2opD_op_mask 0x1
1634 #define COMPI2opD_code_bits 11
1635 #define COMPI2opD_code_mask 0x1f
1637 #define init_COMPI2opD \
1640 COMPI2opD_dst_bits, COMPI2opD_dst_mask, \
1641 COMPI2opD_src_bits, COMPI2opD_src_mask, \
1642 COMPI2opD_op_bits, COMPI2opD_op_mask, \
1643 COMPI2opD_code_bits, COMPI2opD_code_mask \
1647 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1648 | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
1649 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1652 typedef COMPI2opD COMPI2opP;
1654 #define COMPI2opP_opcode 0x6800
1655 #define COMPI2opP_dst_bits 0
1656 #define COMPI2opP_dst_mask 0x7
1657 #define COMPI2opP_src_bits 3
1658 #define COMPI2opP_src_mask 0x7f
1659 #define COMPI2opP_op_bits 10
1660 #define COMPI2opP_op_mask 0x1
1661 #define COMPI2opP_code_bits 11
1662 #define COMPI2opP_code_mask 0x1f
1664 #define init_COMPI2opP \
1667 COMPI2opP_dst_bits, COMPI2opP_dst_mask, \
1668 COMPI2opP_src_bits, COMPI2opP_src_mask, \
1669 COMPI2opP_op_bits, COMPI2opP_op_mask, \
1670 COMPI2opP_code_bits, COMPI2opP_code_mask \
1675 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1676 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
1677 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1682 unsigned short opcode;
1697 #define DagMODim_opcode 0x9e60
1698 #define DagMODim_i_bits 0
1699 #define DagMODim_i_mask 0x3
1700 #define DagMODim_m_bits 2
1701 #define DagMODim_m_mask 0x3
1702 #define DagMODim_op_bits 4
1703 #define DagMODim_op_mask 0x1
1704 #define DagMODim_code2_bits 5
1705 #define DagMODim_code2_mask 0x3
1706 #define DagMODim_br_bits 7
1707 #define DagMODim_br_mask 0x1
1708 #define DagMODim_code_bits 8
1709 #define DagMODim_code_mask 0xff
1711 #define init_DagMODim \
1714 DagMODim_i_bits, DagMODim_i_mask, \
1715 DagMODim_m_bits, DagMODim_m_mask, \
1716 DagMODim_op_bits, DagMODim_op_mask, \
1717 DagMODim_code2_bits, DagMODim_code2_mask, \
1718 DagMODim_br_bits, DagMODim_br_mask, \
1719 DagMODim_code_bits, DagMODim_code_mask \
1723 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1724 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
1725 +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
1730 unsigned short opcode;
1739 #define DagMODik_opcode 0x9f60
1740 #define DagMODik_i_bits 0
1741 #define DagMODik_i_mask 0x3
1742 #define DagMODik_op_bits 2
1743 #define DagMODik_op_mask 0x3
1744 #define DagMODik_code_bits 3
1745 #define DagMODik_code_mask 0xfff
1747 #define init_DagMODik \
1750 DagMODik_i_bits, DagMODik_i_mask, \
1751 DagMODik_op_bits, DagMODik_op_mask, \
1752 DagMODik_code_bits, DagMODik_code_mask \